diff options
author | Ingo Molnar <mingo@elte.hu> | 2008-11-20 03:03:38 -0500 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2008-11-20 03:03:38 -0500 |
commit | 90accd6fabf9b2fa2705945a4c601877a75d43bf (patch) | |
tree | d393cb54f0228b1313139e4e14adf4f5cf236b59 /arch/mips/include/asm/mach-pnx833x | |
parent | b43d196c4d3fe46d6dda7c987c47792612b80b1b (diff) | |
parent | ee2f6cc7f9ea2542ad46070ed62ba7aa04d08871 (diff) |
Merge branch 'linus' into x86/memory-corruption-check
Diffstat (limited to 'arch/mips/include/asm/mach-pnx833x')
-rw-r--r-- | arch/mips/include/asm/mach-pnx833x/gpio.h | 172 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-pnx833x/irq-mapping.h | 126 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-pnx833x/irq.h | 53 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-pnx833x/pnx833x.h | 202 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-pnx833x/war.h | 25 |
5 files changed, 578 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-pnx833x/gpio.h b/arch/mips/include/asm/mach-pnx833x/gpio.h new file mode 100644 index 000000000000..8de0eb9c98a3 --- /dev/null +++ b/arch/mips/include/asm/mach-pnx833x/gpio.h | |||
@@ -0,0 +1,172 @@ | |||
1 | /* | ||
2 | * gpio.h: GPIO Support for PNX833X. | ||
3 | * | ||
4 | * Copyright 2008 NXP Semiconductors | ||
5 | * Chris Steel <chris.steel@nxp.com> | ||
6 | * Daniel Laird <daniel.j.laird@nxp.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software | ||
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
21 | */ | ||
22 | #ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H | ||
23 | #define __ASM_MIPS_MACH_PNX833X_GPIO_H | ||
24 | |||
25 | /* BIG FAT WARNING: races danger! | ||
26 | No protections exist here. Current users are only early init code, | ||
27 | when locking is not needed because no cuncurency yet exists there, | ||
28 | and GPIO IRQ dispatcher, which does locking. | ||
29 | However, if many uses will ever happen, proper locking will be needed | ||
30 | - including locking between different uses | ||
31 | */ | ||
32 | |||
33 | #include "pnx833x.h" | ||
34 | |||
35 | #define SET_REG_BIT(reg, bit) do { (reg |= (1 << (bit))); } while (0) | ||
36 | #define CLEAR_REG_BIT(reg, bit) do { (reg &= ~(1 << (bit))); } while (0) | ||
37 | |||
38 | /* Initialize GPIO to a known state */ | ||
39 | static inline void pnx833x_gpio_init(void) | ||
40 | { | ||
41 | PNX833X_PIO_DIR = 0; | ||
42 | PNX833X_PIO_DIR2 = 0; | ||
43 | PNX833X_PIO_SEL = 0; | ||
44 | PNX833X_PIO_SEL2 = 0; | ||
45 | PNX833X_PIO_INT_EDGE = 0; | ||
46 | PNX833X_PIO_INT_HI = 0; | ||
47 | PNX833X_PIO_INT_LO = 0; | ||
48 | |||
49 | /* clear any GPIO interrupt requests */ | ||
50 | PNX833X_PIO_INT_CLEAR = 0xffff; | ||
51 | PNX833X_PIO_INT_CLEAR = 0; | ||
52 | PNX833X_PIO_INT_ENABLE = 0; | ||
53 | } | ||
54 | |||
55 | /* Select GPIO direction for a pin */ | ||
56 | static inline void pnx833x_gpio_select_input(unsigned int pin) | ||
57 | { | ||
58 | if (pin < 32) | ||
59 | CLEAR_REG_BIT(PNX833X_PIO_DIR, pin); | ||
60 | else | ||
61 | CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31); | ||
62 | } | ||
63 | static inline void pnx833x_gpio_select_output(unsigned int pin) | ||
64 | { | ||
65 | if (pin < 32) | ||
66 | SET_REG_BIT(PNX833X_PIO_DIR, pin); | ||
67 | else | ||
68 | SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31); | ||
69 | } | ||
70 | |||
71 | /* Select GPIO or alternate function for a pin */ | ||
72 | static inline void pnx833x_gpio_select_function_io(unsigned int pin) | ||
73 | { | ||
74 | if (pin < 32) | ||
75 | CLEAR_REG_BIT(PNX833X_PIO_SEL, pin); | ||
76 | else | ||
77 | CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31); | ||
78 | } | ||
79 | static inline void pnx833x_gpio_select_function_alt(unsigned int pin) | ||
80 | { | ||
81 | if (pin < 32) | ||
82 | SET_REG_BIT(PNX833X_PIO_SEL, pin); | ||
83 | else | ||
84 | SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31); | ||
85 | } | ||
86 | |||
87 | /* Read GPIO pin */ | ||
88 | static inline int pnx833x_gpio_read(unsigned int pin) | ||
89 | { | ||
90 | if (pin < 32) | ||
91 | return (PNX833X_PIO_IN >> pin) & 1; | ||
92 | else | ||
93 | return (PNX833X_PIO_IN2 >> (pin & 31)) & 1; | ||
94 | } | ||
95 | |||
96 | /* Write GPIO pin */ | ||
97 | static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin) | ||
98 | { | ||
99 | if (pin < 32) { | ||
100 | if (val) | ||
101 | SET_REG_BIT(PNX833X_PIO_OUT, pin); | ||
102 | else | ||
103 | CLEAR_REG_BIT(PNX833X_PIO_OUT, pin); | ||
104 | } else { | ||
105 | if (val) | ||
106 | SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31); | ||
107 | else | ||
108 | CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31); | ||
109 | } | ||
110 | } | ||
111 | |||
112 | /* Configure GPIO interrupt */ | ||
113 | #define GPIO_INT_NONE 0 | ||
114 | #define GPIO_INT_LEVEL_LOW 1 | ||
115 | #define GPIO_INT_LEVEL_HIGH 2 | ||
116 | #define GPIO_INT_EDGE_RISING 3 | ||
117 | #define GPIO_INT_EDGE_FALLING 4 | ||
118 | #define GPIO_INT_EDGE_BOTH 5 | ||
119 | static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin) | ||
120 | { | ||
121 | switch (when) { | ||
122 | case GPIO_INT_LEVEL_LOW: | ||
123 | CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); | ||
124 | CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); | ||
125 | SET_REG_BIT(PNX833X_PIO_INT_LO, pin); | ||
126 | break; | ||
127 | case GPIO_INT_LEVEL_HIGH: | ||
128 | CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); | ||
129 | SET_REG_BIT(PNX833X_PIO_INT_HI, pin); | ||
130 | CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); | ||
131 | break; | ||
132 | case GPIO_INT_EDGE_RISING: | ||
133 | SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); | ||
134 | SET_REG_BIT(PNX833X_PIO_INT_HI, pin); | ||
135 | CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); | ||
136 | break; | ||
137 | case GPIO_INT_EDGE_FALLING: | ||
138 | SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); | ||
139 | CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); | ||
140 | SET_REG_BIT(PNX833X_PIO_INT_LO, pin); | ||
141 | break; | ||
142 | case GPIO_INT_EDGE_BOTH: | ||
143 | SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); | ||
144 | SET_REG_BIT(PNX833X_PIO_INT_HI, pin); | ||
145 | SET_REG_BIT(PNX833X_PIO_INT_LO, pin); | ||
146 | break; | ||
147 | default: | ||
148 | CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); | ||
149 | CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); | ||
150 | CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); | ||
151 | break; | ||
152 | } | ||
153 | } | ||
154 | |||
155 | /* Enable/disable GPIO interrupt */ | ||
156 | static inline void pnx833x_gpio_enable_irq(unsigned int pin) | ||
157 | { | ||
158 | SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin); | ||
159 | } | ||
160 | static inline void pnx833x_gpio_disable_irq(unsigned int pin) | ||
161 | { | ||
162 | CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin); | ||
163 | } | ||
164 | |||
165 | /* Clear GPIO interrupt request */ | ||
166 | static inline void pnx833x_gpio_clear_irq(unsigned int pin) | ||
167 | { | ||
168 | SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin); | ||
169 | CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin); | ||
170 | } | ||
171 | |||
172 | #endif | ||
diff --git a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h new file mode 100644 index 000000000000..657f089b1724 --- /dev/null +++ b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h | |||
@@ -0,0 +1,126 @@ | |||
1 | |||
2 | /* | ||
3 | * irq.h: IRQ mappings for PNX833X. | ||
4 | * | ||
5 | * Copyright 2008 NXP Semiconductors | ||
6 | * Chris Steel <chris.steel@nxp.com> | ||
7 | * Daniel Laird <daniel.j.laird@nxp.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | * This program is distributed in the hope that it will be useful, | ||
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
17 | * GNU General Public License for more details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this program; if not, write to the Free Software | ||
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
22 | */ | ||
23 | |||
24 | #ifndef __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H | ||
25 | #define __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H | ||
26 | /* | ||
27 | * The "IRQ numbers" are completely virtual. | ||
28 | * | ||
29 | * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48. | ||
30 | * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt, | ||
31 | * numbers 49..64 for (virtual) GPIO interrupts. | ||
32 | * | ||
33 | * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57, | ||
34 | * connected to PIC, which uses core hardware interrupt 2, and also | ||
35 | * a timer interrupt through hardware interrupt 5. | ||
36 | * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt, | ||
37 | * numbers 65..80 for (virtual) GPIO interrupts. | ||
38 | * | ||
39 | */ | ||
40 | #include <irq.h> | ||
41 | |||
42 | #define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) | ||
43 | |||
44 | /* Interrupts supported by PIC */ | ||
45 | #define PNX833X_PIC_I2C0_INT (PNX833X_PIC_IRQ_BASE + 1) | ||
46 | #define PNX833X_PIC_I2C1_INT (PNX833X_PIC_IRQ_BASE + 2) | ||
47 | #define PNX833X_PIC_UART0_INT (PNX833X_PIC_IRQ_BASE + 3) | ||
48 | #define PNX833X_PIC_UART1_INT (PNX833X_PIC_IRQ_BASE + 4) | ||
49 | #define PNX833X_PIC_TS_IN0_DV_INT (PNX833X_PIC_IRQ_BASE + 5) | ||
50 | #define PNX833X_PIC_TS_IN0_DMA_INT (PNX833X_PIC_IRQ_BASE + 6) | ||
51 | #define PNX833X_PIC_GPIO_INT (PNX833X_PIC_IRQ_BASE + 7) | ||
52 | #define PNX833X_PIC_AUDIO_DEC_INT (PNX833X_PIC_IRQ_BASE + 8) | ||
53 | #define PNX833X_PIC_VIDEO_DEC_INT (PNX833X_PIC_IRQ_BASE + 9) | ||
54 | #define PNX833X_PIC_CONFIG_INT (PNX833X_PIC_IRQ_BASE + 10) | ||
55 | #define PNX833X_PIC_AOI_INT (PNX833X_PIC_IRQ_BASE + 11) | ||
56 | #define PNX833X_PIC_SYNC_INT (PNX833X_PIC_IRQ_BASE + 12) | ||
57 | #define PNX8330_PIC_SPU_INT (PNX833X_PIC_IRQ_BASE + 13) | ||
58 | #define PNX8335_PIC_SATA_INT (PNX833X_PIC_IRQ_BASE + 13) | ||
59 | #define PNX833X_PIC_OSD_INT (PNX833X_PIC_IRQ_BASE + 14) | ||
60 | #define PNX833X_PIC_DISP1_INT (PNX833X_PIC_IRQ_BASE + 15) | ||
61 | #define PNX833X_PIC_DEINTERLACER_INT (PNX833X_PIC_IRQ_BASE + 16) | ||
62 | #define PNX833X_PIC_DISPLAY2_INT (PNX833X_PIC_IRQ_BASE + 17) | ||
63 | #define PNX833X_PIC_VC_INT (PNX833X_PIC_IRQ_BASE + 18) | ||
64 | #define PNX833X_PIC_SC_INT (PNX833X_PIC_IRQ_BASE + 19) | ||
65 | #define PNX833X_PIC_IDE_INT (PNX833X_PIC_IRQ_BASE + 20) | ||
66 | #define PNX833X_PIC_IDE_DMA_INT (PNX833X_PIC_IRQ_BASE + 21) | ||
67 | #define PNX833X_PIC_TS_IN1_DV_INT (PNX833X_PIC_IRQ_BASE + 22) | ||
68 | #define PNX833X_PIC_TS_IN1_DMA_INT (PNX833X_PIC_IRQ_BASE + 23) | ||
69 | #define PNX833X_PIC_SGDX_DMA_INT (PNX833X_PIC_IRQ_BASE + 24) | ||
70 | #define PNX833X_PIC_TS_OUT_INT (PNX833X_PIC_IRQ_BASE + 25) | ||
71 | #define PNX833X_PIC_IR_INT (PNX833X_PIC_IRQ_BASE + 26) | ||
72 | #define PNX833X_PIC_VMSP1_INT (PNX833X_PIC_IRQ_BASE + 27) | ||
73 | #define PNX833X_PIC_VMSP2_INT (PNX833X_PIC_IRQ_BASE + 28) | ||
74 | #define PNX833X_PIC_PIBC_INT (PNX833X_PIC_IRQ_BASE + 29) | ||
75 | #define PNX833X_PIC_TS_IN0_TRD_INT (PNX833X_PIC_IRQ_BASE + 30) | ||
76 | #define PNX833X_PIC_SGDX_TPD_INT (PNX833X_PIC_IRQ_BASE + 31) | ||
77 | #define PNX833X_PIC_USB_INT (PNX833X_PIC_IRQ_BASE + 32) | ||
78 | #define PNX833X_PIC_TS_IN1_TRD_INT (PNX833X_PIC_IRQ_BASE + 33) | ||
79 | #define PNX833X_PIC_CLOCK_INT (PNX833X_PIC_IRQ_BASE + 34) | ||
80 | #define PNX833X_PIC_SGDX_PARSER_INT (PNX833X_PIC_IRQ_BASE + 35) | ||
81 | #define PNX833X_PIC_VMSP_DMA_INT (PNX833X_PIC_IRQ_BASE + 36) | ||
82 | |||
83 | #if defined(CONFIG_SOC_PNX8335) | ||
84 | #define PNX8335_PIC_MIU_INT (PNX833X_PIC_IRQ_BASE + 37) | ||
85 | #define PNX8335_PIC_AVCHIP_IRQ_INT (PNX833X_PIC_IRQ_BASE + 38) | ||
86 | #define PNX8335_PIC_SYNC_HD_INT (PNX833X_PIC_IRQ_BASE + 39) | ||
87 | #define PNX8335_PIC_DISP_HD_INT (PNX833X_PIC_IRQ_BASE + 40) | ||
88 | #define PNX8335_PIC_DISP_SCALER_INT (PNX833X_PIC_IRQ_BASE + 41) | ||
89 | #define PNX8335_PIC_OSD_HD1_INT (PNX833X_PIC_IRQ_BASE + 42) | ||
90 | #define PNX8335_PIC_DTL_WRITER_Y_INT (PNX833X_PIC_IRQ_BASE + 43) | ||
91 | #define PNX8335_PIC_DTL_WRITER_C_INT (PNX833X_PIC_IRQ_BASE + 44) | ||
92 | #define PNX8335_PIC_DTL_EMULATOR_Y_IR_INT (PNX833X_PIC_IRQ_BASE + 45) | ||
93 | #define PNX8335_PIC_DTL_EMULATOR_C_IR_INT (PNX833X_PIC_IRQ_BASE + 46) | ||
94 | #define PNX8335_PIC_DENC_TTX_INT (PNX833X_PIC_IRQ_BASE + 47) | ||
95 | #define PNX8335_PIC_MMI_SIF0_INT (PNX833X_PIC_IRQ_BASE + 48) | ||
96 | #define PNX8335_PIC_MMI_SIF1_INT (PNX833X_PIC_IRQ_BASE + 49) | ||
97 | #define PNX8335_PIC_MMI_CDMMU_INT (PNX833X_PIC_IRQ_BASE + 50) | ||
98 | #define PNX8335_PIC_PIBCS_INT (PNX833X_PIC_IRQ_BASE + 51) | ||
99 | #define PNX8335_PIC_ETHERNET_INT (PNX833X_PIC_IRQ_BASE + 52) | ||
100 | #define PNX8335_PIC_VMSP1_0_INT (PNX833X_PIC_IRQ_BASE + 53) | ||
101 | #define PNX8335_PIC_VMSP1_1_INT (PNX833X_PIC_IRQ_BASE + 54) | ||
102 | #define PNX8335_PIC_VMSP1_DMA_INT (PNX833X_PIC_IRQ_BASE + 55) | ||
103 | #define PNX8335_PIC_TDGR_DE_INT (PNX833X_PIC_IRQ_BASE + 56) | ||
104 | #define PNX8335_PIC_IR1_IRQ_INT (PNX833X_PIC_IRQ_BASE + 57) | ||
105 | #endif | ||
106 | |||
107 | /* GPIO interrupts */ | ||
108 | #define PNX833X_GPIO_0_INT (PNX833X_GPIO_IRQ_BASE + 0) | ||
109 | #define PNX833X_GPIO_1_INT (PNX833X_GPIO_IRQ_BASE + 1) | ||
110 | #define PNX833X_GPIO_2_INT (PNX833X_GPIO_IRQ_BASE + 2) | ||
111 | #define PNX833X_GPIO_3_INT (PNX833X_GPIO_IRQ_BASE + 3) | ||
112 | #define PNX833X_GPIO_4_INT (PNX833X_GPIO_IRQ_BASE + 4) | ||
113 | #define PNX833X_GPIO_5_INT (PNX833X_GPIO_IRQ_BASE + 5) | ||
114 | #define PNX833X_GPIO_6_INT (PNX833X_GPIO_IRQ_BASE + 6) | ||
115 | #define PNX833X_GPIO_7_INT (PNX833X_GPIO_IRQ_BASE + 7) | ||
116 | #define PNX833X_GPIO_8_INT (PNX833X_GPIO_IRQ_BASE + 8) | ||
117 | #define PNX833X_GPIO_9_INT (PNX833X_GPIO_IRQ_BASE + 9) | ||
118 | #define PNX833X_GPIO_10_INT (PNX833X_GPIO_IRQ_BASE + 10) | ||
119 | #define PNX833X_GPIO_11_INT (PNX833X_GPIO_IRQ_BASE + 11) | ||
120 | #define PNX833X_GPIO_12_INT (PNX833X_GPIO_IRQ_BASE + 12) | ||
121 | #define PNX833X_GPIO_13_INT (PNX833X_GPIO_IRQ_BASE + 13) | ||
122 | #define PNX833X_GPIO_14_INT (PNX833X_GPIO_IRQ_BASE + 14) | ||
123 | #define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15) | ||
124 | |||
125 | #endif | ||
126 | |||
diff --git a/arch/mips/include/asm/mach-pnx833x/irq.h b/arch/mips/include/asm/mach-pnx833x/irq.h new file mode 100644 index 000000000000..745114b1d8d5 --- /dev/null +++ b/arch/mips/include/asm/mach-pnx833x/irq.h | |||
@@ -0,0 +1,53 @@ | |||
1 | /* | ||
2 | * irq.h: IRQ mappings for PNX833X. | ||
3 | * | ||
4 | * Copyright 2008 NXP Semiconductors | ||
5 | * Chris Steel <chris.steel@nxp.com> | ||
6 | * Daniel Laird <daniel.j.laird@nxp.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software | ||
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
21 | */ | ||
22 | |||
23 | #ifndef __ASM_MIPS_MACH_PNX833X_IRQ_H | ||
24 | #define __ASM_MIPS_MACH_PNX833X_IRQ_H | ||
25 | /* | ||
26 | * The "IRQ numbers" are completely virtual. | ||
27 | * | ||
28 | * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48. | ||
29 | * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt, | ||
30 | * numbers 49..64 for (virtual) GPIO interrupts. | ||
31 | * | ||
32 | * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57, | ||
33 | * connected to PIC, which uses core hardware interrupt 2, and also | ||
34 | * a timer interrupt through hardware interrupt 5. | ||
35 | * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt, | ||
36 | * numbers 65..80 for (virtual) GPIO interrupts. | ||
37 | * | ||
38 | */ | ||
39 | #if defined(CONFIG_SOC_PNX8335) | ||
40 | #define PNX833X_PIC_NUM_IRQ 58 | ||
41 | #else | ||
42 | #define PNX833X_PIC_NUM_IRQ 37 | ||
43 | #endif | ||
44 | |||
45 | #define MIPS_CPU_NUM_IRQ 8 | ||
46 | #define PNX833X_GPIO_NUM_IRQ 16 | ||
47 | |||
48 | #define MIPS_CPU_IRQ_BASE 0 | ||
49 | #define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ) | ||
50 | #define PNX833X_GPIO_IRQ_BASE (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ) | ||
51 | #define NR_IRQS (MIPS_CPU_NUM_IRQ + PNX833X_PIC_NUM_IRQ + PNX833X_GPIO_NUM_IRQ) | ||
52 | |||
53 | #endif | ||
diff --git a/arch/mips/include/asm/mach-pnx833x/pnx833x.h b/arch/mips/include/asm/mach-pnx833x/pnx833x.h new file mode 100644 index 000000000000..100f52870e3c --- /dev/null +++ b/arch/mips/include/asm/mach-pnx833x/pnx833x.h | |||
@@ -0,0 +1,202 @@ | |||
1 | /* | ||
2 | * pnx833x.h: Register mappings for PNX833X. | ||
3 | * | ||
4 | * Copyright 2008 NXP Semiconductors | ||
5 | * Chris Steel <chris.steel@nxp.com> | ||
6 | * Daniel Laird <daniel.j.laird@nxp.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software | ||
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
21 | */ | ||
22 | #ifndef __ASM_MIPS_MACH_PNX833X_PNX833X_H | ||
23 | #define __ASM_MIPS_MACH_PNX833X_PNX833X_H | ||
24 | |||
25 | /* All regs are accessed in KSEG1 */ | ||
26 | #define PNX833X_BASE (0xa0000000ul + 0x17E00000ul) | ||
27 | |||
28 | #define PNX833X_REG(offs) (*((volatile unsigned long *)(PNX833X_BASE + offs))) | ||
29 | |||
30 | /* Registers are named exactly as in PNX833X docs, just with PNX833X_ prefix */ | ||
31 | |||
32 | /* Read access to multibit fields */ | ||
33 | #define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field) | ||
34 | #define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field) | ||
35 | |||
36 | /* Use PNX833X_FIELD to extract a field from val */ | ||
37 | #define PNX_FIELD(cpu, val, reg, field) \ | ||
38 | (((val) & PNX##cpu##_##reg##_##field##_MASK) >> \ | ||
39 | PNX##cpu##_##reg##_##field##_SHIFT) | ||
40 | #define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field) | ||
41 | #define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field) | ||
42 | #define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field) | ||
43 | |||
44 | /* Use PNX833X_REGFIELD to extract a field from a register */ | ||
45 | #define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field) | ||
46 | #define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field) | ||
47 | #define PNX8335_REGFIELD(reg, field) PNX8335_FIELD(PNX8335_##reg, reg, field) | ||
48 | |||
49 | |||
50 | #define PNX_WRITEFIELD(cpu, val, reg, field) \ | ||
51 | (PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \ | ||
52 | ((val) << PNX##cpu##_##reg##_##field##_SHIFT)) | ||
53 | #define PNX833X_WRITEFIELD(val, reg, field) \ | ||
54 | PNX_WRITEFIELD(833X, val, reg, field) | ||
55 | #define PNX8330_WRITEFIELD(val, reg, field) \ | ||
56 | PNX_WRITEFIELD(8330, val, reg, field) | ||
57 | #define PNX8335_WRITEFIELD(val, reg, field) \ | ||
58 | PNX_WRITEFIELD(8335, val, reg, field) | ||
59 | |||
60 | |||
61 | /* Macros to detect CPU type */ | ||
62 | |||
63 | #define PNX833X_CONFIG_MODULE_ID PNX833X_REG(0x7FFC) | ||
64 | #define PNX833X_CONFIG_MODULE_ID_MAJREV_MASK 0x0000f000 | ||
65 | #define PNX833X_CONFIG_MODULE_ID_MAJREV_SHIFT 12 | ||
66 | #define PNX8330_CONFIG_MODULE_MAJREV 4 | ||
67 | #define PNX8335_CONFIG_MODULE_MAJREV 5 | ||
68 | #define CPU_IS_PNX8330 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \ | ||
69 | PNX8330_CONFIG_MODULE_MAJREV) | ||
70 | #define CPU_IS_PNX8335 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \ | ||
71 | PNX8335_CONFIG_MODULE_MAJREV) | ||
72 | |||
73 | |||
74 | |||
75 | #define PNX833X_RESET_CONTROL PNX833X_REG(0x8004) | ||
76 | #define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014) | ||
77 | |||
78 | #define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs)) | ||
79 | #define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0) | ||
80 | #define PNX833X_PIC_INT_SRC PNX833X_PIC_REG(0x4) | ||
81 | #define PNX833X_PIC_INT_SRC_INT_SRC_MASK 0x00000FF8ul /* bits 11:3 */ | ||
82 | #define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3 | ||
83 | #define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq)) | ||
84 | |||
85 | #define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228) | ||
86 | #define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */ | ||
87 | #define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */ | ||
88 | #define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3 | ||
89 | |||
90 | #define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020) | ||
91 | #define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f | ||
92 | #define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_SHIFT 0 | ||
93 | |||
94 | #define PNX833X_CONFIG_MUX PNX833X_REG(0x7004) | ||
95 | #define PNX833X_CONFIG_MUX_IDE_MUX 0x00000080 /* bit 7 */ | ||
96 | |||
97 | #define PNX8330_CONFIG_POLYFUSE_7 PNX833X_REG(0x7040) | ||
98 | #define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_MASK 0x00180000 | ||
99 | #define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_SHIFT 19 | ||
100 | |||
101 | #define PNX833X_PIO_IN PNX833X_REG(0xF000) | ||
102 | #define PNX833X_PIO_OUT PNX833X_REG(0xF004) | ||
103 | #define PNX833X_PIO_DIR PNX833X_REG(0xF008) | ||
104 | #define PNX833X_PIO_SEL PNX833X_REG(0xF014) | ||
105 | #define PNX833X_PIO_INT_EDGE PNX833X_REG(0xF020) | ||
106 | #define PNX833X_PIO_INT_HI PNX833X_REG(0xF024) | ||
107 | #define PNX833X_PIO_INT_LO PNX833X_REG(0xF028) | ||
108 | #define PNX833X_PIO_INT_STATUS PNX833X_REG(0xFFE0) | ||
109 | #define PNX833X_PIO_INT_ENABLE PNX833X_REG(0xFFE4) | ||
110 | #define PNX833X_PIO_INT_CLEAR PNX833X_REG(0xFFE8) | ||
111 | #define PNX833X_PIO_IN2 PNX833X_REG(0xF05C) | ||
112 | #define PNX833X_PIO_OUT2 PNX833X_REG(0xF060) | ||
113 | #define PNX833X_PIO_DIR2 PNX833X_REG(0xF064) | ||
114 | #define PNX833X_PIO_SEL2 PNX833X_REG(0xF068) | ||
115 | |||
116 | #define PNX833X_UART0_PORTS_START (PNX833X_BASE + 0xB000) | ||
117 | #define PNX833X_UART0_PORTS_END (PNX833X_BASE + 0xBFFF) | ||
118 | #define PNX833X_UART1_PORTS_START (PNX833X_BASE + 0xC000) | ||
119 | #define PNX833X_UART1_PORTS_END (PNX833X_BASE + 0xCFFF) | ||
120 | |||
121 | #define PNX833X_USB_PORTS_START (PNX833X_BASE + 0x19000) | ||
122 | #define PNX833X_USB_PORTS_END (PNX833X_BASE + 0x19FFF) | ||
123 | |||
124 | #define PNX833X_CONFIG_USB PNX833X_REG(0x7008) | ||
125 | |||
126 | #define PNX833X_I2C0_PORTS_START (PNX833X_BASE + 0xD000) | ||
127 | #define PNX833X_I2C0_PORTS_END (PNX833X_BASE + 0xDFFF) | ||
128 | #define PNX833X_I2C1_PORTS_START (PNX833X_BASE + 0xE000) | ||
129 | #define PNX833X_I2C1_PORTS_END (PNX833X_BASE + 0xEFFF) | ||
130 | |||
131 | #define PNX833X_IDE_PORTS_START (PNX833X_BASE + 0x1A000) | ||
132 | #define PNX833X_IDE_PORTS_END (PNX833X_BASE + 0x1AFFF) | ||
133 | #define PNX833X_IDE_MODULE_ID PNX833X_REG(0x1AFFC) | ||
134 | |||
135 | #define PNX833X_IDE_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 | ||
136 | #define PNX833X_IDE_MODULE_ID_MODULE_ID_SHIFT 16 | ||
137 | #define PNX833X_IDE_MODULE_ID_VALUE 0xA009 | ||
138 | |||
139 | |||
140 | #define PNX833X_MIU_SEL0 PNX833X_REG(0x2004) | ||
141 | #define PNX833X_MIU_SEL0_TIMING PNX833X_REG(0x2008) | ||
142 | #define PNX833X_MIU_SEL1 PNX833X_REG(0x200C) | ||
143 | #define PNX833X_MIU_SEL1_TIMING PNX833X_REG(0x2010) | ||
144 | #define PNX833X_MIU_SEL2 PNX833X_REG(0x2014) | ||
145 | #define PNX833X_MIU_SEL2_TIMING PNX833X_REG(0x2018) | ||
146 | #define PNX833X_MIU_SEL3 PNX833X_REG(0x201C) | ||
147 | #define PNX833X_MIU_SEL3_TIMING PNX833X_REG(0x2020) | ||
148 | |||
149 | #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14) | ||
150 | #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14 | ||
151 | |||
152 | #define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7) | ||
153 | #define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7 | ||
154 | |||
155 | #define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9) | ||
156 | #define PNX833X_MIU_SEL0_BURST_PAGE_LEN_SHIFT 9 | ||
157 | |||
158 | #define PNX833X_MIU_CONFIG_SPI PNX833X_REG(0x2000) | ||
159 | |||
160 | #define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3) | ||
161 | #define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3 | ||
162 | |||
163 | #define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2) | ||
164 | #define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2 | ||
165 | |||
166 | #define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1) | ||
167 | #define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1 | ||
168 | |||
169 | #define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0) | ||
170 | #define PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT 0 | ||
171 | |||
172 | #define PNX833X_WRITE_CONFIG_SPI(opcode, data_enable, addr_enable, sync) \ | ||
173 | (PNX833X_MIU_CONFIG_SPI = \ | ||
174 | ((opcode) << PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT) | \ | ||
175 | ((data_enable) << PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT) | \ | ||
176 | ((addr_enable) << PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT) | \ | ||
177 | ((sync) << PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT)) | ||
178 | |||
179 | #define PNX8335_IP3902_PORTS_START (PNX833X_BASE + 0x2F000) | ||
180 | #define PNX8335_IP3902_PORTS_END (PNX833X_BASE + 0x2FFFF) | ||
181 | #define PNX8335_IP3902_MODULE_ID PNX833X_REG(0x2FFFC) | ||
182 | |||
183 | #define PNX8335_IP3902_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 | ||
184 | #define PNX8335_IP3902_MODULE_ID_MODULE_ID_SHIFT 16 | ||
185 | #define PNX8335_IP3902_MODULE_ID_VALUE 0x3902 | ||
186 | |||
187 | /* I/O location(gets remapped)*/ | ||
188 | #define PNX8335_NAND_BASE 0x18000000 | ||
189 | /* I/O location with CLE high */ | ||
190 | #define PNX8335_NAND_CLE_MASK 0x00100000 | ||
191 | /* I/O location with ALE high */ | ||
192 | #define PNX8335_NAND_ALE_MASK 0x00010000 | ||
193 | |||
194 | #define PNX8335_SATA_PORTS_START (PNX833X_BASE + 0x2E000) | ||
195 | #define PNX8335_SATA_PORTS_END (PNX833X_BASE + 0x2EFFF) | ||
196 | #define PNX8335_SATA_MODULE_ID PNX833X_REG(0x2EFFC) | ||
197 | |||
198 | #define PNX8335_SATA_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 | ||
199 | #define PNX8335_SATA_MODULE_ID_MODULE_ID_SHIFT 16 | ||
200 | #define PNX8335_SATA_MODULE_ID_VALUE 0xA099 | ||
201 | |||
202 | #endif | ||
diff --git a/arch/mips/include/asm/mach-pnx833x/war.h b/arch/mips/include/asm/mach-pnx833x/war.h new file mode 100644 index 000000000000..82cd1e97bc2e --- /dev/null +++ b/arch/mips/include/asm/mach-pnx833x/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_PNX833X_WAR_H | ||
9 | #define __ASM_MIPS_MACH_PNX833X_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */ | ||