diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2013-01-22 06:59:30 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2013-02-01 04:00:22 -0500 |
commit | 7034228792cc561e79ff8600f02884bd4c80e287 (patch) | |
tree | 89b77af37d087d9de236fc5d21f60bf552d0a2c6 /arch/mips/include/asm/mach-pnx833x/pnx833x.h | |
parent | 405ab01c70e18058d9c01a1256769a61fc65413e (diff) |
MIPS: Whitespace cleanup.
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-pnx833x/pnx833x.h')
-rw-r--r-- | arch/mips/include/asm/mach-pnx833x/pnx833x.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/include/asm/mach-pnx833x/pnx833x.h b/arch/mips/include/asm/mach-pnx833x/pnx833x.h index 100f52870e3c..e6fc3a9d594a 100644 --- a/arch/mips/include/asm/mach-pnx833x/pnx833x.h +++ b/arch/mips/include/asm/mach-pnx833x/pnx833x.h | |||
@@ -73,7 +73,7 @@ | |||
73 | 73 | ||
74 | 74 | ||
75 | #define PNX833X_RESET_CONTROL PNX833X_REG(0x8004) | 75 | #define PNX833X_RESET_CONTROL PNX833X_REG(0x8004) |
76 | #define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014) | 76 | #define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014) |
77 | 77 | ||
78 | #define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs)) | 78 | #define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs)) |
79 | #define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0) | 79 | #define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0) |
@@ -82,10 +82,10 @@ | |||
82 | #define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3 | 82 | #define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3 |
83 | #define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq)) | 83 | #define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq)) |
84 | 84 | ||
85 | #define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228) | 85 | #define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228) |
86 | #define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */ | 86 | #define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */ |
87 | #define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */ | 87 | #define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */ |
88 | #define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3 | 88 | #define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3 |
89 | 89 | ||
90 | #define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020) | 90 | #define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020) |
91 | #define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f | 91 | #define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f |
@@ -149,7 +149,7 @@ | |||
149 | #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14) | 149 | #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14) |
150 | #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14 | 150 | #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14 |
151 | 151 | ||
152 | #define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7) | 152 | #define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7) |
153 | #define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7 | 153 | #define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7 |
154 | 154 | ||
155 | #define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9) | 155 | #define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9) |
@@ -160,10 +160,10 @@ | |||
160 | #define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3) | 160 | #define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3) |
161 | #define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3 | 161 | #define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3 |
162 | 162 | ||
163 | #define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2) | 163 | #define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2) |
164 | #define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2 | 164 | #define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2 |
165 | 165 | ||
166 | #define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1) | 166 | #define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1) |
167 | #define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1 | 167 | #define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1 |
168 | 168 | ||
169 | #define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0) | 169 | #define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0) |