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authorRalf Baechle <ralf@linux-mips.org>2008-09-16 13:48:51 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 11:18:52 -0400
commit384740dc49ea651ba350704d13ff6be9976e37fe (patch)
treea6e80cad287ccae7a86d81bfa692fc96889c88ed /arch/mips/include/asm/mach-pb1x00
parente8c7c482347574ecdd45c43e32c332d5fc2ece61 (diff)
MIPS: Move headfiles to new location below arch/mips/include
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-pb1x00')
-rw-r--r--arch/mips/include/asm/mach-pb1x00/mc146818rtc.h34
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1000.h87
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1100.h85
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1200.h259
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1500.h49
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1550.h177
6 files changed, 691 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
new file mode 100644
index 000000000000..622c58710e5b
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
@@ -0,0 +1,34 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1998, 2001, 03 by Ralf Baechle
7 *
8 * RTC routines for PC style attached Dallas chip.
9 */
10#ifndef __ASM_MACH_AU1XX_MC146818RTC_H
11#define __ASM_MACH_AU1XX_MC146818RTC_H
12
13#include <asm/io.h>
14#include <asm/mach-au1x00/au1000.h>
15
16#define RTC_PORT(x) (0x0c000000 + (x))
17#define RTC_IRQ 8
18#define PB1500_RTC_ADDR 0x0c000000
19
20static inline unsigned char CMOS_READ(unsigned long offset)
21{
22 offset <<= 2;
23 return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff);
24}
25
26static inline void CMOS_WRITE(unsigned char data, unsigned long offset)
27{
28 offset <<= 2;
29 au_writel(data, offset + PB1500_RTC_ADDR);
30}
31
32#define RTC_ALWAYS_BCD 1
33
34#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h
new file mode 100644
index 000000000000..6d1ff9060e44
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/pb1000.h
@@ -0,0 +1,87 @@
1/*
2 * Alchemy Semi Pb1000 Referrence Board
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 *
24 *
25 */
26#ifndef __ASM_PB1000_H
27#define __ASM_PB1000_H
28
29/* PCMCIA PB1000 specific defines */
30#define PCMCIA_MAX_SOCK 1
31#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
32
33#define PB1000_PCR 0xBE000000
34# define PCR_SLOT_0_VPP0 (1 << 0)
35# define PCR_SLOT_0_VPP1 (1 << 1)
36# define PCR_SLOT_0_VCC0 (1 << 2)
37# define PCR_SLOT_0_VCC1 (1 << 3)
38# define PCR_SLOT_0_RST (1 << 4)
39# define PCR_SLOT_1_VPP0 (1 << 8)
40# define PCR_SLOT_1_VPP1 (1 << 9)
41# define PCR_SLOT_1_VCC0 (1 << 10)
42# define PCR_SLOT_1_VCC1 (1 << 11)
43# define PCR_SLOT_1_RST (1 << 12)
44
45#define PB1000_MDR 0xBE000004
46# define MDR_PI (1 << 5) /* PCMCIA int latch */
47# define MDR_EPI (1 << 14) /* enable PCMCIA int */
48# define MDR_CPI (1 << 15) /* clear PCMCIA int */
49
50#define PB1000_ACR1 0xBE000008
51# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */
52# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */
53# define ACR1_SLOT_0_READY (1 << 2) /* ready */
54# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */
55# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */
56# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */
57# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */
58# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */
59# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */
60# define ACR1_SLOT_1_READY (1 << 10) /* ready */
61# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */
62# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */
63# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */
64# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */
65
66#define CPLD_AUX0 0xBE00000C
67#define CPLD_AUX1 0xBE000010
68#define CPLD_AUX2 0xBE000014
69
70/* Voltage levels */
71
72/* VPPEN1 - VPPEN0 */
73#define VPP_GND ((0 << 1) | (0 << 0))
74#define VPP_5V ((1 << 1) | (0 << 0))
75#define VPP_3V ((0 << 1) | (1 << 0))
76#define VPP_12V ((0 << 1) | (1 << 0))
77#define VPP_HIZ ((1 << 1) | (1 << 0))
78
79/* VCCEN1 - VCCEN0 */
80#define VCC_3V ((0 << 1) | (1 << 0))
81#define VCC_5V ((1 << 1) | (0 << 0))
82#define VCC_HIZ ((0 << 1) | (0 << 0))
83
84/* VPP/VCC */
85#define SET_VCC_VPP(VCC, VPP, SLOT) \
86 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
87#endif /* __ASM_PB1000_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1100.h b/arch/mips/include/asm/mach-pb1x00/pb1100.h
new file mode 100644
index 000000000000..b1a60f1cbd02
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/pb1100.h
@@ -0,0 +1,85 @@
1/*
2 * Alchemy Semi Pb1100 Referrence Board
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 *
24 *
25 */
26#ifndef __ASM_PB1100_H
27#define __ASM_PB1100_H
28
29#define PB1100_IDENT 0xAE000000
30#define BOARD_STATUS_REG 0xAE000004
31# define PB1100_ROM_SEL (1 << 15)
32# define PB1100_ROM_SIZ (1 << 14)
33# define PB1100_SWAP_BOOT (1 << 13)
34# define PB1100_FLASH_WP (1 << 12)
35# define PB1100_ROM_H_STS (1 << 11)
36# define PB1100_ROM_L_STS (1 << 10)
37# define PB1100_FLASH_H_STS (1 << 9)
38# define PB1100_FLASH_L_STS (1 << 8)
39# define PB1100_SRAM_SIZ (1 << 7)
40# define PB1100_TSC_BUSY (1 << 6)
41# define PB1100_PCMCIA_VS_MASK (3 << 4)
42# define PB1100_RS232_CD (1 << 3)
43# define PB1100_RS232_CTS (1 << 2)
44# define PB1100_RS232_DSR (1 << 1)
45# define PB1100_RS232_RI (1 << 0)
46
47#define PB1100_IRDA_RS232 0xAE00000C
48# define PB1100_IRDA_FULL (0 << 14) /* full power */
49# define PB1100_IRDA_SHUTDOWN (1 << 14)
50# define PB1100_IRDA_TT (2 << 14) /* 2/3 power */
51# define PB1100_IRDA_OT (3 << 14) /* 1/3 power */
52# define PB1100_IRDA_FIR (1 << 13)
53
54#define PCMCIA_BOARD_REG 0xAE000010
55# define PB1100_SD_WP1_RO (1 << 15) /* read only */
56# define PB1100_SD_WP0_RO (1 << 14) /* read only */
57# define PB1100_SD_PWR1 (1 << 11) /* applies power to SD1 */
58# define PB1100_SD_PWR0 (1 << 10) /* applies power to SD0 */
59# define PB1100_SEL_SD_CONN1 (1 << 9)
60# define PB1100_SEL_SD_CONN0 (1 << 8)
61# define PC_DEASSERT_RST (1 << 7)
62# define PC_DRV_EN (1 << 4)
63
64#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
65
66#define PB1100_RST_VDDI 0xAE00001C
67# define PB1100_SOFT_RESET (1 << 15) /* clear to reset the board */
68# define PB1100_VDDI_MASK 0x1F
69
70#define PB1100_LEDS 0xAE000018
71
72/*
73 * 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
74 * 7:0 is the LED Display's decimal points.
75 */
76#define PB1100_HEX_LED 0xAE000018
77
78/* PCMCIA Pb1100 specific defines */
79#define PCMCIA_MAX_SOCK 0
80#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
81
82/* VPP/VCC */
83#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
84
85#endif /* __ASM_PB1100_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
new file mode 100644
index 000000000000..c8618df88cb5
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h
@@ -0,0 +1,259 @@
1/*
2 * AMD Alchemy Pb1200 Referrence Board
3 * Board Registers defines.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 *
23 */
24#ifndef __ASM_PB1200_H
25#define __ASM_PB1200_H
26
27#include <linux/types.h>
28#include <asm/mach-au1x00/au1xxx_psc.h>
29
30#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
31#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
32#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
33#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
34
35/*
36 * SPI and SMB are muxed on the Pb1200 board.
37 * Refer to board documentation.
38 */
39#define SPI_PSC_BASE PSC0_BASE_ADDR
40#define SMBUS_PSC_BASE PSC0_BASE_ADDR
41/*
42 * AC97 and I2S are muxed on the Pb1200 board.
43 * Refer to board documentation.
44 */
45#define AC97_PSC_BASE PSC1_BASE_ADDR
46#define I2S_PSC_BASE PSC1_BASE_ADDR
47
48#define BCSR_KSEG1_ADDR 0xAD800000
49
50typedef volatile struct
51{
52 /*00*/ u16 whoami;
53 u16 reserved0;
54 /*04*/ u16 status;
55 u16 reserved1;
56 /*08*/ u16 switches;
57 u16 reserved2;
58 /*0C*/ u16 resets;
59 u16 reserved3;
60
61 /*10*/ u16 pcmcia;
62 u16 reserved4;
63 /*14*/ u16 board;
64 u16 reserved5;
65 /*18*/ u16 disk_leds;
66 u16 reserved6;
67 /*1C*/ u16 system;
68 u16 reserved7;
69
70 /*20*/ u16 intclr;
71 u16 reserved8;
72 /*24*/ u16 intset;
73 u16 reserved9;
74 /*28*/ u16 intclr_mask;
75 u16 reserved10;
76 /*2C*/ u16 intset_mask;
77 u16 reserved11;
78
79 /*30*/ u16 sig_status;
80 u16 reserved12;
81 /*34*/ u16 int_status;
82 u16 reserved13;
83 /*38*/ u16 reserved14;
84 u16 reserved15;
85 /*3C*/ u16 reserved16;
86 u16 reserved17;
87
88} BCSR;
89
90static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
91
92/*
93 * Register bit definitions for the BCSRs
94 */
95#define BCSR_WHOAMI_DCID 0x000F
96#define BCSR_WHOAMI_CPLD 0x00F0
97#define BCSR_WHOAMI_BOARD 0x0F00
98
99#define BCSR_STATUS_PCMCIA0VS 0x0003
100#define BCSR_STATUS_PCMCIA1VS 0x000C
101#define BCSR_STATUS_SWAPBOOT 0x0040
102#define BCSR_STATUS_FLASHBUSY 0x0100
103#define BCSR_STATUS_IDECBLID 0x0200
104#define BCSR_STATUS_SD0WP 0x0400
105#define BCSR_STATUS_SD1WP 0x0800
106#define BCSR_STATUS_U0RXD 0x1000
107#define BCSR_STATUS_U1RXD 0x2000
108
109#define BCSR_SWITCHES_OCTAL 0x00FF
110#define BCSR_SWITCHES_DIP_1 0x0080
111#define BCSR_SWITCHES_DIP_2 0x0040
112#define BCSR_SWITCHES_DIP_3 0x0020
113#define BCSR_SWITCHES_DIP_4 0x0010
114#define BCSR_SWITCHES_DIP_5 0x0008
115#define BCSR_SWITCHES_DIP_6 0x0004
116#define BCSR_SWITCHES_DIP_7 0x0002
117#define BCSR_SWITCHES_DIP_8 0x0001
118#define BCSR_SWITCHES_ROTARY 0x0F00
119
120#define BCSR_RESETS_ETH 0x0001
121#define BCSR_RESETS_CAMERA 0x0002
122#define BCSR_RESETS_DC 0x0004
123#define BCSR_RESETS_IDE 0x0008
124/* not resets but in the same register */
125#define BCSR_RESETS_WSCFSM 0x0800
126#define BCSR_RESETS_PCS0MUX 0x1000
127#define BCSR_RESETS_PCS1MUX 0x2000
128#define BCSR_RESETS_SPISEL 0x4000
129#define BCSR_RESETS_SD1MUX 0x8000
130
131#define BCSR_PCMCIA_PC0VPP 0x0003
132#define BCSR_PCMCIA_PC0VCC 0x000C
133#define BCSR_PCMCIA_PC0DRVEN 0x0010
134#define BCSR_PCMCIA_PC0RST 0x0080
135#define BCSR_PCMCIA_PC1VPP 0x0300
136#define BCSR_PCMCIA_PC1VCC 0x0C00
137#define BCSR_PCMCIA_PC1DRVEN 0x1000
138#define BCSR_PCMCIA_PC1RST 0x8000
139
140#define BCSR_BOARD_LCDVEE 0x0001
141#define BCSR_BOARD_LCDVDD 0x0002
142#define BCSR_BOARD_LCDBL 0x0004
143#define BCSR_BOARD_CAMSNAP 0x0010
144#define BCSR_BOARD_CAMPWR 0x0020
145#define BCSR_BOARD_SD0PWR 0x0040
146#define BCSR_BOARD_SD1PWR 0x0080
147
148#define BCSR_LEDS_DECIMALS 0x00FF
149#define BCSR_LEDS_LED0 0x0100
150#define BCSR_LEDS_LED1 0x0200
151#define BCSR_LEDS_LED2 0x0400
152#define BCSR_LEDS_LED3 0x0800
153
154#define BCSR_SYSTEM_VDDI 0x001F
155#define BCSR_SYSTEM_POWEROFF 0x4000
156#define BCSR_SYSTEM_RESET 0x8000
157
158/* Bit positions for the different interrupt sources */
159#define BCSR_INT_IDE 0x0001
160#define BCSR_INT_ETH 0x0002
161#define BCSR_INT_PC0 0x0004
162#define BCSR_INT_PC0STSCHG 0x0008
163#define BCSR_INT_PC1 0x0010
164#define BCSR_INT_PC1STSCHG 0x0020
165#define BCSR_INT_DC 0x0040
166#define BCSR_INT_FLASHBUSY 0x0080
167#define BCSR_INT_PC0INSERT 0x0100
168#define BCSR_INT_PC0EJECT 0x0200
169#define BCSR_INT_PC1INSERT 0x0400
170#define BCSR_INT_PC1EJECT 0x0800
171#define BCSR_INT_SD0INSERT 0x1000
172#define BCSR_INT_SD0EJECT 0x2000
173#define BCSR_INT_SD1INSERT 0x4000
174#define BCSR_INT_SD1EJECT 0x8000
175
176#define SMC91C111_PHYS_ADDR 0x0D000300
177#define SMC91C111_INT PB1200_ETH_INT
178
179#define IDE_PHYS_ADDR 0x0C800000
180#define IDE_REG_SHIFT 5
181#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
182#define IDE_INT PB1200_IDE_INT
183#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
184#define IDE_RQSIZE 128
185
186#define NAND_PHYS_ADDR 0x1C000000
187
188/*
189 * Timing values as described in databook, * ns value stripped of
190 * lower 2 bits.
191 * These defines are here rather than an Au1200 generic file because
192 * the parts chosen on another board may be different and may require
193 * different timings.
194 */
195#define NAND_T_H (18 >> 2)
196#define NAND_T_PUL (30 >> 2)
197#define NAND_T_SU (30 >> 2)
198#define NAND_T_WH (30 >> 2)
199
200/* Bitfield shift amounts */
201#define NAND_T_H_SHIFT 0
202#define NAND_T_PUL_SHIFT 4
203#define NAND_T_SU_SHIFT 8
204#define NAND_T_WH_SHIFT 12
205
206#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
207 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
208 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
209 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
210
211/*
212 * External Interrupts for Pb1200 as of 8/6/2004.
213 * Bit positions in the CPLD registers can be calculated by taking
214 * the interrupt define and subtracting the PB1200_INT_BEGIN value.
215 *
216 * Example: IDE bis pos is = 64 - 64
217 * ETH bit pos is = 65 - 64
218 */
219enum external_pb1200_ints {
220 PB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
221
222 PB1200_IDE_INT = PB1200_INT_BEGIN,
223 PB1200_ETH_INT,
224 PB1200_PC0_INT,
225 PB1200_PC0_STSCHG_INT,
226 PB1200_PC1_INT,
227 PB1200_PC1_STSCHG_INT,
228 PB1200_DC_INT,
229 PB1200_FLASHBUSY_INT,
230 PB1200_PC0_INSERT_INT,
231 PB1200_PC0_EJECT_INT,
232 PB1200_PC1_INSERT_INT,
233 PB1200_PC1_EJECT_INT,
234 PB1200_SD0_INSERT_INT,
235 PB1200_SD0_EJECT_INT,
236 PB1200_SD1_INSERT_INT,
237 PB1200_SD1_EJECT_INT,
238
239 PB1200_INT_END = PB1200_INT_BEGIN + 15
240};
241
242/*
243 * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
244 */
245#define PCMCIA_MAX_SOCK 1
246#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
247
248/* VPP/VCC */
249#define SET_VCC_VPP(VCC, VPP, SLOT) \
250 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
251
252#define BOARD_PC0_INT PB1200_PC0_INT
253#define BOARD_PC1_INT PB1200_PC1_INT
254#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
255
256/* NAND chip select */
257#define NAND_CS 1
258
259#endif /* __ASM_PB1200_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1500.h b/arch/mips/include/asm/mach-pb1x00/pb1500.h
new file mode 100644
index 000000000000..da51a2eb7b82
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/pb1500.h
@@ -0,0 +1,49 @@
1/*
2 * Alchemy Semi Pb1500 Referrence Board
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 *
24 *
25 */
26#ifndef __ASM_PB1500_H
27#define __ASM_PB1500_H
28
29#define IDENT_BOARD_REG 0xAE000000
30#define BOARD_STATUS_REG 0xAE000004
31#define PCI_BOARD_REG 0xAE000010
32#define PCMCIA_BOARD_REG 0xAE000010
33# define PC_DEASSERT_RST 0x80
34# define PC_DRV_EN 0x10
35#define PB1500_G_CONTROL 0xAE000014
36#define PB1500_RST_VDDI 0xAE00001C
37#define PB1500_LEDS 0xAE000018
38
39#define PB1500_HEX_LED 0xAF000004
40#define PB1500_HEX_LED_BLANK 0xAF000008
41
42/* PCMCIA Pb1500 specific defines */
43#define PCMCIA_MAX_SOCK 0
44#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
45
46/* VPP/VCC */
47#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
48
49#endif /* __ASM_PB1500_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
new file mode 100644
index 000000000000..6704a11497db
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -0,0 +1,177 @@
1/*
2 * AMD Alchemy Semi PB1550 Referrence Board
3 * Board Registers defines.
4 *
5 * Copyright 2004 Embedded Edge LLC.
6 * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_PB1550_H
28#define __ASM_PB1550_H
29
30#include <linux/types.h>
31#include <asm/mach-au1x00/au1xxx_psc.h>
32
33#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
34#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
37
38#define SPI_PSC_BASE PSC0_BASE_ADDR
39#define AC97_PSC_BASE PSC1_BASE_ADDR
40#define SMBUS_PSC_BASE PSC2_BASE_ADDR
41#define I2S_PSC_BASE PSC3_BASE_ADDR
42
43#define BCSR_PHYS_ADDR 0xAF000000
44
45typedef volatile struct
46{
47 /*00*/ u16 whoami;
48 u16 reserved0;
49 /*04*/ u16 status;
50 u16 reserved1;
51 /*08*/ u16 switches;
52 u16 reserved2;
53 /*0C*/ u16 resets;
54 u16 reserved3;
55 /*10*/ u16 pcmcia;
56 u16 reserved4;
57 /*14*/ u16 pci;
58 u16 reserved5;
59 /*18*/ u16 leds;
60 u16 reserved6;
61 /*1C*/ u16 system;
62 u16 reserved7;
63
64} BCSR;
65
66static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
67
68/*
69 * Register bit definitions for the BCSRs
70 */
71#define BCSR_WHOAMI_DCID 0x000F
72#define BCSR_WHOAMI_CPLD 0x00F0
73#define BCSR_WHOAMI_BOARD 0x0F00
74
75#define BCSR_STATUS_PCMCIA0VS 0x0003
76#define BCSR_STATUS_PCMCIA1VS 0x000C
77#define BCSR_STATUS_PCMCIA0FI 0x0010
78#define BCSR_STATUS_PCMCIA1FI 0x0020
79#define BCSR_STATUS_SWAPBOOT 0x0040
80#define BCSR_STATUS_SRAMWIDTH 0x0080
81#define BCSR_STATUS_FLASHBUSY 0x0100
82#define BCSR_STATUS_ROMBUSY 0x0200
83#define BCSR_STATUS_USBOTGID 0x0800
84#define BCSR_STATUS_U0RXD 0x1000
85#define BCSR_STATUS_U1RXD 0x2000
86#define BCSR_STATUS_U3RXD 0x8000
87
88#define BCSR_SWITCHES_OCTAL 0x00FF
89#define BCSR_SWITCHES_DIP_1 0x0080
90#define BCSR_SWITCHES_DIP_2 0x0040
91#define BCSR_SWITCHES_DIP_3 0x0020
92#define BCSR_SWITCHES_DIP_4 0x0010
93#define BCSR_SWITCHES_DIP_5 0x0008
94#define BCSR_SWITCHES_DIP_6 0x0004
95#define BCSR_SWITCHES_DIP_7 0x0002
96#define BCSR_SWITCHES_DIP_8 0x0001
97#define BCSR_SWITCHES_ROTARY 0x0F00
98
99#define BCSR_RESETS_PHY0 0x0001
100#define BCSR_RESETS_PHY1 0x0002
101#define BCSR_RESETS_DC 0x0004
102#define BCSR_RESETS_WSC 0x2000
103#define BCSR_RESETS_SPISEL 0x4000
104#define BCSR_RESETS_DMAREQ 0x8000
105
106#define BCSR_PCMCIA_PC0VPP 0x0003
107#define BCSR_PCMCIA_PC0VCC 0x000C
108#define BCSR_PCMCIA_PC0DRVEN 0x0010
109#define BCSR_PCMCIA_PC0RST 0x0080
110#define BCSR_PCMCIA_PC1VPP 0x0300
111#define BCSR_PCMCIA_PC1VCC 0x0C00
112#define BCSR_PCMCIA_PC1DRVEN 0x1000
113#define BCSR_PCMCIA_PC1RST 0x8000
114
115#define BCSR_PCI_M66EN 0x0001
116#define BCSR_PCI_M33 0x0100
117#define BCSR_PCI_EXTERNARB 0x0200
118#define BCSR_PCI_GPIO200RST 0x0400
119#define BCSR_PCI_CLKOUT 0x0800
120#define BCSR_PCI_CFGHOST 0x1000
121
122#define BCSR_LEDS_DECIMALS 0x00FF
123#define BCSR_LEDS_LED0 0x0100
124#define BCSR_LEDS_LED1 0x0200
125#define BCSR_LEDS_LED2 0x0400
126#define BCSR_LEDS_LED3 0x0800
127
128#define BCSR_SYSTEM_VDDI 0x001F
129#define BCSR_SYSTEM_POWEROFF 0x4000
130#define BCSR_SYSTEM_RESET 0x8000
131
132#define PCMCIA_MAX_SOCK 1
133#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
134
135/* VPP/VCC */
136#define SET_VCC_VPP(VCC, VPP, SLOT) \
137 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
138
139#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
140#define PB1550_BOTH_BANKS
141#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
142#define PB1550_BOOT_ONLY
143#elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
144#define PB1550_USER_ONLY
145#endif
146
147/*
148 * Timing values as described in databook, * ns value stripped of
149 * lower 2 bits.
150 * These defines are here rather than an SOC1550 generic file because
151 * the parts chosen on another board may be different and may require
152 * different timings.
153 */
154#define NAND_T_H (18 >> 2)
155#define NAND_T_PUL (30 >> 2)
156#define NAND_T_SU (30 >> 2)
157#define NAND_T_WH (30 >> 2)
158
159/* Bitfield shift amounts */
160#define NAND_T_H_SHIFT 0
161#define NAND_T_PUL_SHIFT 4
162#define NAND_T_SU_SHIFT 8
163#define NAND_T_WH_SHIFT 12
164
165#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
166 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
167 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
168 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
169
170#define NAND_CS 1
171
172/* Should be done by YAMON */
173#define NAND_STCFG 0x00400005 /* 8-bit NAND */
174#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
175#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
176
177#endif /* __ASM_PB1550_H */
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