aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/include/asm/mach-loongson/cs5536
diff options
context:
space:
mode:
authorRalf Baechle <ralf@linux-mips.org>2013-01-22 06:59:30 -0500
committerRalf Baechle <ralf@linux-mips.org>2013-02-01 04:00:22 -0500
commit7034228792cc561e79ff8600f02884bd4c80e287 (patch)
tree89b77af37d087d9de236fc5d21f60bf552d0a2c6 /arch/mips/include/asm/mach-loongson/cs5536
parent405ab01c70e18058d9c01a1256769a61fc65413e (diff)
MIPS: Whitespace cleanup.
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-loongson/cs5536')
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536.h422
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h2
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h122
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h4
4 files changed, 275 insertions, 275 deletions
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
index 2a8e2bb5d539..a0ee0cb775ad 100644
--- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
@@ -5,8 +5,8 @@
5 * Author : jlliu <liujl@lemote.com> 5 * Author : jlliu <liujl@lemote.com>
6 */ 6 */
7 7
8#ifndef _CS5536_H 8#ifndef _CS5536_H
9#define _CS5536_H 9#define _CS5536_H
10 10
11#include <linux/types.h> 11#include <linux/types.h>
12 12
@@ -16,237 +16,237 @@ extern void _wrmsr(u32 msr, u32 hi, u32 lo);
16/* 16/*
17 * MSR module base 17 * MSR module base
18 */ 18 */
19#define CS5536_SB_MSR_BASE (0x00000000) 19#define CS5536_SB_MSR_BASE (0x00000000)
20#define CS5536_GLIU_MSR_BASE (0x10000000) 20#define CS5536_GLIU_MSR_BASE (0x10000000)
21#define CS5536_ILLEGAL_MSR_BASE (0x20000000) 21#define CS5536_ILLEGAL_MSR_BASE (0x20000000)
22#define CS5536_USB_MSR_BASE (0x40000000) 22#define CS5536_USB_MSR_BASE (0x40000000)
23#define CS5536_IDE_MSR_BASE (0x60000000) 23#define CS5536_IDE_MSR_BASE (0x60000000)
24#define CS5536_DIVIL_MSR_BASE (0x80000000) 24#define CS5536_DIVIL_MSR_BASE (0x80000000)
25#define CS5536_ACC_MSR_BASE (0xa0000000) 25#define CS5536_ACC_MSR_BASE (0xa0000000)
26#define CS5536_UNUSED_MSR_BASE (0xc0000000) 26#define CS5536_UNUSED_MSR_BASE (0xc0000000)
27#define CS5536_GLCP_MSR_BASE (0xe0000000) 27#define CS5536_GLCP_MSR_BASE (0xe0000000)
28 28
29#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset)) 29#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset))
30#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset)) 30#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset))
31#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset)) 31#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset))
32#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset)) 32#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset))
33#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset)) 33#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset))
34#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset)) 34#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset))
35#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset)) 35#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset))
36#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset)) 36#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset))
37#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset)) 37#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset))
38 38
39/* 39/*
40 * BAR SPACE OF VIRTUAL PCI : 40 * BAR SPACE OF VIRTUAL PCI :
41 * range for pci probe use, length is the actual size. 41 * range for pci probe use, length is the actual size.
42 */ 42 */
43/* IO space for all DIVIL modules */ 43/* IO space for all DIVIL modules */
44#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */ 44#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */
45#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */ 45#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */
46#define CS5536_SMB_RANGE 0xfffffff8 46#define CS5536_SMB_RANGE 0xfffffff8
47#define CS5536_SMB_LENGTH 0x08 47#define CS5536_SMB_LENGTH 0x08
48#define CS5536_GPIO_RANGE 0xffffff00 48#define CS5536_GPIO_RANGE 0xffffff00
49#define CS5536_GPIO_LENGTH 0x100 49#define CS5536_GPIO_LENGTH 0x100
50#define CS5536_MFGPT_RANGE 0xffffffc0 50#define CS5536_MFGPT_RANGE 0xffffffc0
51#define CS5536_MFGPT_LENGTH 0x40 51#define CS5536_MFGPT_LENGTH 0x40
52#define CS5536_ACPI_RANGE 0xffffffe0 52#define CS5536_ACPI_RANGE 0xffffffe0
53#define CS5536_ACPI_LENGTH 0x20 53#define CS5536_ACPI_LENGTH 0x20
54#define CS5536_PMS_RANGE 0xffffff80 54#define CS5536_PMS_RANGE 0xffffff80
55#define CS5536_PMS_LENGTH 0x80 55#define CS5536_PMS_LENGTH 0x80
56/* IO space for IDE */ 56/* IO space for IDE */
57#define CS5536_IDE_RANGE 0xfffffff0 57#define CS5536_IDE_RANGE 0xfffffff0
58#define CS5536_IDE_LENGTH 0x10 58#define CS5536_IDE_LENGTH 0x10
59/* IO space for ACC */ 59/* IO space for ACC */
60#define CS5536_ACC_RANGE 0xffffff80 60#define CS5536_ACC_RANGE 0xffffff80
61#define CS5536_ACC_LENGTH 0x80 61#define CS5536_ACC_LENGTH 0x80
62/* MEM space for ALL USB modules */ 62/* MEM space for ALL USB modules */
63#define CS5536_OHCI_RANGE 0xfffff000 63#define CS5536_OHCI_RANGE 0xfffff000
64#define CS5536_OHCI_LENGTH 0x1000 64#define CS5536_OHCI_LENGTH 0x1000
65#define CS5536_EHCI_RANGE 0xfffff000 65#define CS5536_EHCI_RANGE 0xfffff000
66#define CS5536_EHCI_LENGTH 0x1000 66#define CS5536_EHCI_LENGTH 0x1000
67 67
68/* 68/*
69 * PCI MSR ACCESS 69 * PCI MSR ACCESS
70 */ 70 */
71#define PCI_MSR_CTRL 0xF0 71#define PCI_MSR_CTRL 0xF0
72#define PCI_MSR_ADDR 0xF4 72#define PCI_MSR_ADDR 0xF4
73#define PCI_MSR_DATA_LO 0xF8 73#define PCI_MSR_DATA_LO 0xF8
74#define PCI_MSR_DATA_HI 0xFC 74#define PCI_MSR_DATA_HI 0xFC
75 75
76/**************** MSR *****************************/ 76/**************** MSR *****************************/
77 77
78/* 78/*
79 * GLIU STANDARD MSR 79 * GLIU STANDARD MSR
80 */ 80 */
81#define GLIU_CAP 0x00 81#define GLIU_CAP 0x00
82#define GLIU_CONFIG 0x01 82#define GLIU_CONFIG 0x01
83#define GLIU_SMI 0x02 83#define GLIU_SMI 0x02
84#define GLIU_ERROR 0x03 84#define GLIU_ERROR 0x03
85#define GLIU_PM 0x04 85#define GLIU_PM 0x04
86#define GLIU_DIAG 0x05 86#define GLIU_DIAG 0x05
87 87
88/* 88/*
89 * GLIU SPEC. MSR 89 * GLIU SPEC. MSR
90 */ 90 */
91#define GLIU_P2D_BM0 0x20 91#define GLIU_P2D_BM0 0x20
92#define GLIU_P2D_BM1 0x21 92#define GLIU_P2D_BM1 0x21
93#define GLIU_P2D_BM2 0x22 93#define GLIU_P2D_BM2 0x22
94#define GLIU_P2D_BMK0 0x23 94#define GLIU_P2D_BMK0 0x23
95#define GLIU_P2D_BMK1 0x24 95#define GLIU_P2D_BMK1 0x24
96#define GLIU_P2D_BM3 0x25 96#define GLIU_P2D_BM3 0x25
97#define GLIU_P2D_BM4 0x26 97#define GLIU_P2D_BM4 0x26
98#define GLIU_COH 0x80 98#define GLIU_COH 0x80
99#define GLIU_PAE 0x81 99#define GLIU_PAE 0x81
100#define GLIU_ARB 0x82 100#define GLIU_ARB 0x82
101#define GLIU_ASMI 0x83 101#define GLIU_ASMI 0x83
102#define GLIU_AERR 0x84 102#define GLIU_AERR 0x84
103#define GLIU_DEBUG 0x85 103#define GLIU_DEBUG 0x85
104#define GLIU_PHY_CAP 0x86 104#define GLIU_PHY_CAP 0x86
105#define GLIU_NOUT_RESP 0x87 105#define GLIU_NOUT_RESP 0x87
106#define GLIU_NOUT_WDATA 0x88 106#define GLIU_NOUT_WDATA 0x88
107#define GLIU_WHOAMI 0x8B 107#define GLIU_WHOAMI 0x8B
108#define GLIU_SLV_DIS 0x8C 108#define GLIU_SLV_DIS 0x8C
109#define GLIU_IOD_BM0 0xE0 109#define GLIU_IOD_BM0 0xE0
110#define GLIU_IOD_BM1 0xE1 110#define GLIU_IOD_BM1 0xE1
111#define GLIU_IOD_BM2 0xE2 111#define GLIU_IOD_BM2 0xE2
112#define GLIU_IOD_BM3 0xE3 112#define GLIU_IOD_BM3 0xE3
113#define GLIU_IOD_BM4 0xE4 113#define GLIU_IOD_BM4 0xE4
114#define GLIU_IOD_BM5 0xE5 114#define GLIU_IOD_BM5 0xE5
115#define GLIU_IOD_BM6 0xE6 115#define GLIU_IOD_BM6 0xE6
116#define GLIU_IOD_BM7 0xE7 116#define GLIU_IOD_BM7 0xE7
117#define GLIU_IOD_BM8 0xE8 117#define GLIU_IOD_BM8 0xE8
118#define GLIU_IOD_BM9 0xE9 118#define GLIU_IOD_BM9 0xE9
119#define GLIU_IOD_SC0 0xEA 119#define GLIU_IOD_SC0 0xEA
120#define GLIU_IOD_SC1 0xEB 120#define GLIU_IOD_SC1 0xEB
121#define GLIU_IOD_SC2 0xEC 121#define GLIU_IOD_SC2 0xEC
122#define GLIU_IOD_SC3 0xED 122#define GLIU_IOD_SC3 0xED
123#define GLIU_IOD_SC4 0xEE 123#define GLIU_IOD_SC4 0xEE
124#define GLIU_IOD_SC5 0xEF 124#define GLIU_IOD_SC5 0xEF
125#define GLIU_IOD_SC6 0xF0 125#define GLIU_IOD_SC6 0xF0
126#define GLIU_IOD_SC7 0xF1 126#define GLIU_IOD_SC7 0xF1
127 127
128/* 128/*
129 * SB STANDARD 129 * SB STANDARD
130 */ 130 */
131#define SB_CAP 0x00 131#define SB_CAP 0x00
132#define SB_CONFIG 0x01 132#define SB_CONFIG 0x01
133#define SB_SMI 0x02 133#define SB_SMI 0x02
134#define SB_ERROR 0x03 134#define SB_ERROR 0x03
135#define SB_MAR_ERR_EN 0x00000001 135#define SB_MAR_ERR_EN 0x00000001
136#define SB_TAR_ERR_EN 0x00000002 136#define SB_TAR_ERR_EN 0x00000002
137#define SB_RSVD_BIT1 0x00000004 137#define SB_RSVD_BIT1 0x00000004
138#define SB_EXCEP_ERR_EN 0x00000008 138#define SB_EXCEP_ERR_EN 0x00000008
139#define SB_SYSE_ERR_EN 0x00000010 139#define SB_SYSE_ERR_EN 0x00000010
140#define SB_PARE_ERR_EN 0x00000020 140#define SB_PARE_ERR_EN 0x00000020
141#define SB_TAS_ERR_EN 0x00000040 141#define SB_TAS_ERR_EN 0x00000040
142#define SB_MAR_ERR_FLAG 0x00010000 142#define SB_MAR_ERR_FLAG 0x00010000
143#define SB_TAR_ERR_FLAG 0x00020000 143#define SB_TAR_ERR_FLAG 0x00020000
144#define SB_RSVD_BIT2 0x00040000 144#define SB_RSVD_BIT2 0x00040000
145#define SB_EXCEP_ERR_FLAG 0x00080000 145#define SB_EXCEP_ERR_FLAG 0x00080000
146#define SB_SYSE_ERR_FLAG 0x00100000 146#define SB_SYSE_ERR_FLAG 0x00100000
147#define SB_PARE_ERR_FLAG 0x00200000 147#define SB_PARE_ERR_FLAG 0x00200000
148#define SB_TAS_ERR_FLAG 0x00400000 148#define SB_TAS_ERR_FLAG 0x00400000
149#define SB_PM 0x04 149#define SB_PM 0x04
150#define SB_DIAG 0x05 150#define SB_DIAG 0x05
151 151
152/* 152/*
153 * SB SPEC. 153 * SB SPEC.
154 */ 154 */
155#define SB_CTRL 0x10 155#define SB_CTRL 0x10
156#define SB_R0 0x20 156#define SB_R0 0x20
157#define SB_R1 0x21 157#define SB_R1 0x21
158#define SB_R2 0x22 158#define SB_R2 0x22
159#define SB_R3 0x23 159#define SB_R3 0x23
160#define SB_R4 0x24 160#define SB_R4 0x24
161#define SB_R5 0x25 161#define SB_R5 0x25
162#define SB_R6 0x26 162#define SB_R6 0x26
163#define SB_R7 0x27 163#define SB_R7 0x27
164#define SB_R8 0x28 164#define SB_R8 0x28
165#define SB_R9 0x29 165#define SB_R9 0x29
166#define SB_R10 0x2A 166#define SB_R10 0x2A
167#define SB_R11 0x2B 167#define SB_R11 0x2B
168#define SB_R12 0x2C 168#define SB_R12 0x2C
169#define SB_R13 0x2D 169#define SB_R13 0x2D
170#define SB_R14 0x2E 170#define SB_R14 0x2E
171#define SB_R15 0x2F 171#define SB_R15 0x2F
172 172
173/* 173/*
174 * GLCP STANDARD 174 * GLCP STANDARD
175 */ 175 */
176#define GLCP_CAP 0x00 176#define GLCP_CAP 0x00
177#define GLCP_CONFIG 0x01 177#define GLCP_CONFIG 0x01
178#define GLCP_SMI 0x02 178#define GLCP_SMI 0x02
179#define GLCP_ERROR 0x03 179#define GLCP_ERROR 0x03
180#define GLCP_PM 0x04 180#define GLCP_PM 0x04
181#define GLCP_DIAG 0x05 181#define GLCP_DIAG 0x05
182 182
183/* 183/*
184 * GLCP SPEC. 184 * GLCP SPEC.
185 */ 185 */
186#define GLCP_CLK_DIS_DELAY 0x08 186#define GLCP_CLK_DIS_DELAY 0x08
187#define GLCP_PM_CLK_DISABLE 0x09 187#define GLCP_PM_CLK_DISABLE 0x09
188#define GLCP_GLB_PM 0x0B 188#define GLCP_GLB_PM 0x0B
189#define GLCP_DBG_OUT 0x0C 189#define GLCP_DBG_OUT 0x0C
190#define GLCP_RSVD1 0x0D 190#define GLCP_RSVD1 0x0D
191#define GLCP_SOFT_COM 0x0E 191#define GLCP_SOFT_COM 0x0E
192#define SOFT_BAR_SMB_FLAG 0x00000001 192#define SOFT_BAR_SMB_FLAG 0x00000001
193#define SOFT_BAR_GPIO_FLAG 0x00000002 193#define SOFT_BAR_GPIO_FLAG 0x00000002
194#define SOFT_BAR_MFGPT_FLAG 0x00000004 194#define SOFT_BAR_MFGPT_FLAG 0x00000004
195#define SOFT_BAR_IRQ_FLAG 0x00000008 195#define SOFT_BAR_IRQ_FLAG 0x00000008
196#define SOFT_BAR_PMS_FLAG 0x00000010 196#define SOFT_BAR_PMS_FLAG 0x00000010
197#define SOFT_BAR_ACPI_FLAG 0x00000020 197#define SOFT_BAR_ACPI_FLAG 0x00000020
198#define SOFT_BAR_IDE_FLAG 0x00000400 198#define SOFT_BAR_IDE_FLAG 0x00000400
199#define SOFT_BAR_ACC_FLAG 0x00000800 199#define SOFT_BAR_ACC_FLAG 0x00000800
200#define SOFT_BAR_OHCI_FLAG 0x00001000 200#define SOFT_BAR_OHCI_FLAG 0x00001000
201#define SOFT_BAR_EHCI_FLAG 0x00002000 201#define SOFT_BAR_EHCI_FLAG 0x00002000
202#define GLCP_RSVD2 0x0F 202#define GLCP_RSVD2 0x0F
203#define GLCP_CLK_OFF 0x10 203#define GLCP_CLK_OFF 0x10
204#define GLCP_CLK_ACTIVE 0x11 204#define GLCP_CLK_ACTIVE 0x11
205#define GLCP_CLK_DISABLE 0x12 205#define GLCP_CLK_DISABLE 0x12
206#define GLCP_CLK4ACK 0x13 206#define GLCP_CLK4ACK 0x13
207#define GLCP_SYS_RST 0x14 207#define GLCP_SYS_RST 0x14
208#define GLCP_RSVD3 0x15 208#define GLCP_RSVD3 0x15
209#define GLCP_DBG_CLK_CTRL 0x16 209#define GLCP_DBG_CLK_CTRL 0x16
210#define GLCP_CHIP_REV_ID 0x17 210#define GLCP_CHIP_REV_ID 0x17
211 211
212/* PIC */ 212/* PIC */
213#define PIC_YSEL_LOW 0x20 213#define PIC_YSEL_LOW 0x20
214#define PIC_YSEL_LOW_USB_SHIFT 8 214#define PIC_YSEL_LOW_USB_SHIFT 8
215#define PIC_YSEL_LOW_ACC_SHIFT 16 215#define PIC_YSEL_LOW_ACC_SHIFT 16
216#define PIC_YSEL_LOW_FLASH_SHIFT 24 216#define PIC_YSEL_LOW_FLASH_SHIFT 24
217#define PIC_YSEL_HIGH 0x21 217#define PIC_YSEL_HIGH 0x21
218#define PIC_ZSEL_LOW 0x22 218#define PIC_ZSEL_LOW 0x22
219#define PIC_ZSEL_HIGH 0x23 219#define PIC_ZSEL_HIGH 0x23
220#define PIC_IRQM_PRIM 0x24 220#define PIC_IRQM_PRIM 0x24
221#define PIC_IRQM_LPC 0x25 221#define PIC_IRQM_LPC 0x25
222#define PIC_XIRR_STS_LOW 0x26 222#define PIC_XIRR_STS_LOW 0x26
223#define PIC_XIRR_STS_HIGH 0x27 223#define PIC_XIRR_STS_HIGH 0x27
224#define PCI_SHDW 0x34 224#define PCI_SHDW 0x34
225 225
226/* 226/*
227 * DIVIL STANDARD 227 * DIVIL STANDARD
228 */ 228 */
229#define DIVIL_CAP 0x00 229#define DIVIL_CAP 0x00
230#define DIVIL_CONFIG 0x01 230#define DIVIL_CONFIG 0x01
231#define DIVIL_SMI 0x02 231#define DIVIL_SMI 0x02
232#define DIVIL_ERROR 0x03 232#define DIVIL_ERROR 0x03
233#define DIVIL_PM 0x04 233#define DIVIL_PM 0x04
234#define DIVIL_DIAG 0x05 234#define DIVIL_DIAG 0x05
235 235
236/* 236/*
237 * DIVIL SPEC. 237 * DIVIL SPEC.
238 */ 238 */
239#define DIVIL_LBAR_IRQ 0x08 239#define DIVIL_LBAR_IRQ 0x08
240#define DIVIL_LBAR_KEL 0x09 240#define DIVIL_LBAR_KEL 0x09
241#define DIVIL_LBAR_SMB 0x0B 241#define DIVIL_LBAR_SMB 0x0B
242#define DIVIL_LBAR_GPIO 0x0C 242#define DIVIL_LBAR_GPIO 0x0C
243#define DIVIL_LBAR_MFGPT 0x0D 243#define DIVIL_LBAR_MFGPT 0x0D
244#define DIVIL_LBAR_ACPI 0x0E 244#define DIVIL_LBAR_ACPI 0x0E
245#define DIVIL_LBAR_PMS 0x0F 245#define DIVIL_LBAR_PMS 0x0F
246#define DIVIL_LEG_IO 0x14 246#define DIVIL_LEG_IO 0x14
247#define DIVIL_BALL_OPTS 0x15 247#define DIVIL_BALL_OPTS 0x15
248#define DIVIL_SOFT_IRQ 0x16 248#define DIVIL_SOFT_IRQ 0x16
249#define DIVIL_SOFT_RESET 0x17 249#define DIVIL_SOFT_RESET 0x17
250 250
251/* MFGPT */ 251/* MFGPT */
252#define MFGPT_IRQ 0x28 252#define MFGPT_IRQ 0x28
@@ -254,52 +254,52 @@ extern void _wrmsr(u32 msr, u32 hi, u32 lo);
254/* 254/*
255 * IDE STANDARD 255 * IDE STANDARD
256 */ 256 */
257#define IDE_CAP 0x00 257#define IDE_CAP 0x00
258#define IDE_CONFIG 0x01 258#define IDE_CONFIG 0x01
259#define IDE_SMI 0x02 259#define IDE_SMI 0x02
260#define IDE_ERROR 0x03 260#define IDE_ERROR 0x03
261#define IDE_PM 0x04 261#define IDE_PM 0x04
262#define IDE_DIAG 0x05 262#define IDE_DIAG 0x05
263 263
264/* 264/*
265 * IDE SPEC. 265 * IDE SPEC.
266 */ 266 */
267#define IDE_IO_BAR 0x08 267#define IDE_IO_BAR 0x08
268#define IDE_CFG 0x10 268#define IDE_CFG 0x10
269#define IDE_DTC 0x12 269#define IDE_DTC 0x12
270#define IDE_CAST 0x13 270#define IDE_CAST 0x13
271#define IDE_ETC 0x14 271#define IDE_ETC 0x14
272#define IDE_INTERNAL_PM 0x15 272#define IDE_INTERNAL_PM 0x15
273 273
274/* 274/*
275 * ACC STANDARD 275 * ACC STANDARD
276 */ 276 */
277#define ACC_CAP 0x00 277#define ACC_CAP 0x00
278#define ACC_CONFIG 0x01 278#define ACC_CONFIG 0x01
279#define ACC_SMI 0x02 279#define ACC_SMI 0x02
280#define ACC_ERROR 0x03 280#define ACC_ERROR 0x03
281#define ACC_PM 0x04 281#define ACC_PM 0x04
282#define ACC_DIAG 0x05 282#define ACC_DIAG 0x05
283 283
284/* 284/*
285 * USB STANDARD 285 * USB STANDARD
286 */ 286 */
287#define USB_CAP 0x00 287#define USB_CAP 0x00
288#define USB_CONFIG 0x01 288#define USB_CONFIG 0x01
289#define USB_SMI 0x02 289#define USB_SMI 0x02
290#define USB_ERROR 0x03 290#define USB_ERROR 0x03
291#define USB_PM 0x04 291#define USB_PM 0x04
292#define USB_DIAG 0x05 292#define USB_DIAG 0x05
293 293
294/* 294/*
295 * USB SPEC. 295 * USB SPEC.
296 */ 296 */
297#define USB_OHCI 0x08 297#define USB_OHCI 0x08
298#define USB_EHCI 0x09 298#define USB_EHCI 0x09
299 299
300/****************** NATIVE ***************************/ 300/****************** NATIVE ***************************/
301/* GPIO : I/O SPACE; REG : 32BITS */ 301/* GPIO : I/O SPACE; REG : 32BITS */
302#define GPIOL_OUT_VAL 0x00 302#define GPIOL_OUT_VAL 0x00
303#define GPIOL_OUT_EN 0x04 303#define GPIOL_OUT_EN 0x04
304 304
305#endif /* _CS5536_H */ 305#endif /* _CS5536_H */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
index 4b493d6772c2..021d0172dad6 100644
--- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
@@ -25,7 +25,7 @@ static inline void __maybe_unused enable_mfgpt0_counter(void)
25#endif 25#endif
26 26
27#define MFGPT_TICK_RATE 14318000 27#define MFGPT_TICK_RATE 14318000
28#define COMPARE ((MFGPT_TICK_RATE + HZ/2) / HZ) 28#define COMPARE ((MFGPT_TICK_RATE + HZ/2) / HZ)
29 29
30#define MFGPT_BASE mfgpt_base 30#define MFGPT_BASE mfgpt_base
31#define MFGPT0_CMP2 (MFGPT_BASE + 2) 31#define MFGPT0_CMP2 (MFGPT_BASE + 2)
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
index 0dca9c89ee7c..8a7ecb4d5c64 100644
--- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
@@ -8,8 +8,8 @@
8 * Author : jlliu, liujl@lemote.com 8 * Author : jlliu, liujl@lemote.com
9 */ 9 */
10 10
11#ifndef _CS5536_PCI_H 11#ifndef _CS5536_PCI_H
12#define _CS5536_PCI_H 12#define _CS5536_PCI_H
13 13
14#include <linux/types.h> 14#include <linux/types.h>
15#include <linux/pci_regs.h> 15#include <linux/pci_regs.h>
@@ -17,20 +17,20 @@
17extern void cs5536_pci_conf_write4(int function, int reg, u32 value); 17extern void cs5536_pci_conf_write4(int function, int reg, u32 value);
18extern u32 cs5536_pci_conf_read4(int function, int reg); 18extern u32 cs5536_pci_conf_read4(int function, int reg);
19 19
20#define CS5536_ACC_INTR 9 20#define CS5536_ACC_INTR 9
21#define CS5536_IDE_INTR 14 21#define CS5536_IDE_INTR 14
22#define CS5536_USB_INTR 11 22#define CS5536_USB_INTR 11
23#define CS5536_MFGPT_INTR 5 23#define CS5536_MFGPT_INTR 5
24#define CS5536_UART1_INTR 4 24#define CS5536_UART1_INTR 4
25#define CS5536_UART2_INTR 3 25#define CS5536_UART2_INTR 3
26 26
27/************** PCI BUS DEVICE FUNCTION ***************/ 27/************** PCI BUS DEVICE FUNCTION ***************/
28 28
29/* 29/*
30 * PCI bus device function 30 * PCI bus device function
31 */ 31 */
32#define PCI_BUS_CS5536 0 32#define PCI_BUS_CS5536 0
33#define PCI_IDSEL_CS5536 14 33#define PCI_IDSEL_CS5536 14
34 34
35/********** STANDARD PCI-2.2 EXPANSION ****************/ 35/********** STANDARD PCI-2.2 EXPANSION ****************/
36 36
@@ -45,21 +45,21 @@ extern u32 cs5536_pci_conf_read4(int function, int reg);
45 (((mod_dev_id) << 16) | (sys_vendor_id)) 45 (((mod_dev_id) << 16) | (sys_vendor_id))
46 46
47/* VENDOR ID */ 47/* VENDOR ID */
48#define CS5536_VENDOR_ID 0x1022 48#define CS5536_VENDOR_ID 0x1022
49 49
50/* DEVICE ID */ 50/* DEVICE ID */
51#define CS5536_ISA_DEVICE_ID 0x2090 51#define CS5536_ISA_DEVICE_ID 0x2090
52#define CS5536_IDE_DEVICE_ID 0x209a 52#define CS5536_IDE_DEVICE_ID 0x209a
53#define CS5536_ACC_DEVICE_ID 0x2093 53#define CS5536_ACC_DEVICE_ID 0x2093
54#define CS5536_OHCI_DEVICE_ID 0x2094 54#define CS5536_OHCI_DEVICE_ID 0x2094
55#define CS5536_EHCI_DEVICE_ID 0x2095 55#define CS5536_EHCI_DEVICE_ID 0x2095
56 56
57/* CLASS CODE : CLASS SUB-CLASS INTERFACE */ 57/* CLASS CODE : CLASS SUB-CLASS INTERFACE */
58#define CS5536_ISA_CLASS_CODE 0x060100 58#define CS5536_ISA_CLASS_CODE 0x060100
59#define CS5536_IDE_CLASS_CODE 0x010180 59#define CS5536_IDE_CLASS_CODE 0x010180
60#define CS5536_ACC_CLASS_CODE 0x040100 60#define CS5536_ACC_CLASS_CODE 0x040100
61#define CS5536_OHCI_CLASS_CODE 0x0C0310 61#define CS5536_OHCI_CLASS_CODE 0x0C0310
62#define CS5536_EHCI_CLASS_CODE 0x0C0320 62#define CS5536_EHCI_CLASS_CODE 0x0C0320
63 63
64/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */ 64/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */
65 65
@@ -67,40 +67,40 @@ extern u32 cs5536_pci_conf_read4(int function, int reg);
67 ((PCI_NONE_BIST << 24) | ((header_type) << 16) \ 67 ((PCI_NONE_BIST << 24) | ((header_type) << 16) \
68 | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE); 68 | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE);
69 69
70#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */ 70#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */
71#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */ 71#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */
72#define PCI_NORMAL_HEADER_TYPE 0x00 72#define PCI_NORMAL_HEADER_TYPE 0x00
73#define PCI_NORMAL_LATENCY_TIMER 0x00 73#define PCI_NORMAL_LATENCY_TIMER 0x00
74#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */ 74#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */
75 75
76/* BAR */ 76/* BAR */
77#define PCI_BAR0_REG 0x10 77#define PCI_BAR0_REG 0x10
78#define PCI_BAR1_REG 0x14 78#define PCI_BAR1_REG 0x14
79#define PCI_BAR2_REG 0x18 79#define PCI_BAR2_REG 0x18
80#define PCI_BAR3_REG 0x1c 80#define PCI_BAR3_REG 0x1c
81#define PCI_BAR4_REG 0x20 81#define PCI_BAR4_REG 0x20
82#define PCI_BAR5_REG 0x24 82#define PCI_BAR5_REG 0x24
83#define PCI_BAR_COUNT 6 83#define PCI_BAR_COUNT 6
84#define PCI_BAR_RANGE_MASK 0xFFFFFFFF 84#define PCI_BAR_RANGE_MASK 0xFFFFFFFF
85 85
86/* CARDBUS CIS POINTER */ 86/* CARDBUS CIS POINTER */
87#define PCI_CARDBUS_CIS_POINTER 0x00000000 87#define PCI_CARDBUS_CIS_POINTER 0x00000000
88 88
89/* SUBSYSTEM VENDOR ID */ 89/* SUBSYSTEM VENDOR ID */
90#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID 90#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID
91 91
92/* SUBSYSTEM ID */ 92/* SUBSYSTEM ID */
93#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID 93#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID
94#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID 94#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID
95#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID 95#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID
96#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID 96#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID
97#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID 97#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID
98 98
99/* EXPANSION ROM BAR */ 99/* EXPANSION ROM BAR */
100#define PCI_EXPANSION_ROM_BAR 0x00000000 100#define PCI_EXPANSION_ROM_BAR 0x00000000
101 101
102/* CAPABILITIES POINTER */ 102/* CAPABILITIES POINTER */
103#define PCI_CAPLIST_POINTER 0x00000000 103#define PCI_CAPLIST_POINTER 0x00000000
104#define PCI_CAPLIST_USB_POINTER 0x40 104#define PCI_CAPLIST_USB_POINTER 0x40
105/* INTERRUPT */ 105/* INTERRUPT */
106 106
@@ -108,46 +108,46 @@ extern u32 cs5536_pci_conf_read4(int function, int reg);
108 ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \ 108 ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \
109 ((pin) << 8) | (mod_intr)) 109 ((pin) << 8) | (mod_intr))
110 110
111#define PCI_MAX_LATENCY 0x40 111#define PCI_MAX_LATENCY 0x40
112#define PCI_MIN_GRANT 0x00 112#define PCI_MIN_GRANT 0x00
113#define PCI_DEFAULT_PIN 0x01 113#define PCI_DEFAULT_PIN 0x01
114 114
115/*********** EXPANSION PCI REG ************************/ 115/*********** EXPANSION PCI REG ************************/
116 116
117/* 117/*
118 * ISA EXPANSION 118 * ISA EXPANSION
119 */ 119 */
120#define PCI_UART1_INT_REG 0x50 120#define PCI_UART1_INT_REG 0x50
121#define PCI_UART2_INT_REG 0x54 121#define PCI_UART2_INT_REG 0x54
122#define PCI_ISA_FIXUP_REG 0x58 122#define PCI_ISA_FIXUP_REG 0x58
123 123
124/* 124/*
125 * IDE EXPANSION 125 * IDE EXPANSION
126 */ 126 */
127#define PCI_IDE_CFG_REG 0x40 127#define PCI_IDE_CFG_REG 0x40
128#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF 128#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF
129#define PCI_IDE_DTC_REG 0x48 129#define PCI_IDE_DTC_REG 0x48
130#define PCI_IDE_CAST_REG 0x4C 130#define PCI_IDE_CAST_REG 0x4C
131#define PCI_IDE_ETC_REG 0x50 131#define PCI_IDE_ETC_REG 0x50
132#define PCI_IDE_PM_REG 0x54 132#define PCI_IDE_PM_REG 0x54
133#define PCI_IDE_INT_REG 0x60 133#define PCI_IDE_INT_REG 0x60
134 134
135/* 135/*
136 * ACC EXPANSION 136 * ACC EXPANSION
137 */ 137 */
138#define PCI_ACC_INT_REG 0x50 138#define PCI_ACC_INT_REG 0x50
139 139
140/* 140/*
141 * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI 141 * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI
142 */ 142 */
143#define PCI_OHCI_PM_REG 0x40 143#define PCI_OHCI_PM_REG 0x40
144#define PCI_OHCI_INT_REG 0x50 144#define PCI_OHCI_INT_REG 0x50
145 145
146/* 146/*
147 * EHCI EXPANSION 147 * EHCI EXPANSION
148 */ 148 */
149#define PCI_EHCI_LEGSMIEN_REG 0x50 149#define PCI_EHCI_LEGSMIEN_REG 0x50
150#define PCI_EHCI_LEGSMISTS_REG 0x54 150#define PCI_EHCI_LEGSMISTS_REG 0x54
151#define PCI_EHCI_FLADJ_REG 0x60 151#define PCI_EHCI_FLADJ_REG 0x60
152 152
153#endif /* _CS5536_PCI_H_ */ 153#endif /* _CS5536_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
index 21c4ecedebe7..1f17c1815ee5 100644
--- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
@@ -5,8 +5,8 @@
5 * Author: Wu Zhangjin <wuzhangjin@gmail.com> 5 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
6 */ 6 */
7 7
8#ifndef _CS5536_VSM_H 8#ifndef _CS5536_VSM_H
9#define _CS5536_VSM_H 9#define _CS5536_VSM_H
10 10
11#include <linux/types.h> 11#include <linux/types.h>
12 12
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 07:02:30 -0500