diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-12-17 19:38:06 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-12-17 19:38:06 -0500 |
commit | dbfc985195410dad803c845743c63cd73bd1fe32 (patch) | |
tree | 6bf6dbecb92539285ebb89948e63e691a0947941 /arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h | |
parent | 7c508e50be47737b9a72d0f15c3ef1146925e2d2 (diff) | |
parent | 606d62fa02cf1da43c6e21521650fff07a2e56d1 (diff) |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (71 commits)
MIPS: Lasat: Fix botched changes to sysctl code.
RTC: rtc-cmos.c: Fix warning on MIPS
MIPS: Cleanup random differences beween lmo and Linus' kernel.
MIPS: No longer hardwire CONFIG_EMBEDDED to y
MIPS: Fix and enhance built-in kernel command line
MIPS: eXcite: Remove platform.
MIPS: Loongson: Cleanups of serial port support
MIPS: Lemote 2F: Suspend CS5536 MFGPT Timer
MIPS: Excite: move iodev_remove to .devexit.text
MIPS: Lasat: Convert to proc_fops / seq_file
MIPS: Cleanup signal code initialization
MIPS: Modularize COP2 handling
MIPS: Move EARLY_PRINTK to Kconfig.debug
MIPS: Yeeloong 2F: Cleanup reset logic using the new ec_write function
MIPS: Yeeloong 2F: Add LID open event as the wakeup event
MIPS: Yeeloong 2F: Add basic EC operations
MIPS: Move several variables from .bss to .init.data
MIPS: Tracing: Make function graph tracer work with -mmcount-ra-address
MIPS: Tracing: Reserve $12(t0) for mcount-ra-address of gcc 4.5
MIPS: Tracing: Make ftrace for MIPS work without -fno-omit-frame-pointer
...
Diffstat (limited to 'arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h')
-rw-r--r-- | arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h | 153 |
1 files changed, 153 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h new file mode 100644 index 000000000000..0dca9c89ee7c --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h | |||
@@ -0,0 +1,153 @@ | |||
1 | /* | ||
2 | * the definition file of cs5536 Virtual Support Module(VSM). | ||
3 | * pci configuration space can be accessed through the VSM, so | ||
4 | * there is no need of the MSR read/write now, except the spec. | ||
5 | * MSR registers which are not implemented yet. | ||
6 | * | ||
7 | * Copyright (C) 2007 Lemote Inc. | ||
8 | * Author : jlliu, liujl@lemote.com | ||
9 | */ | ||
10 | |||
11 | #ifndef _CS5536_PCI_H | ||
12 | #define _CS5536_PCI_H | ||
13 | |||
14 | #include <linux/types.h> | ||
15 | #include <linux/pci_regs.h> | ||
16 | |||
17 | extern void cs5536_pci_conf_write4(int function, int reg, u32 value); | ||
18 | extern u32 cs5536_pci_conf_read4(int function, int reg); | ||
19 | |||
20 | #define CS5536_ACC_INTR 9 | ||
21 | #define CS5536_IDE_INTR 14 | ||
22 | #define CS5536_USB_INTR 11 | ||
23 | #define CS5536_MFGPT_INTR 5 | ||
24 | #define CS5536_UART1_INTR 4 | ||
25 | #define CS5536_UART2_INTR 3 | ||
26 | |||
27 | /************** PCI BUS DEVICE FUNCTION ***************/ | ||
28 | |||
29 | /* | ||
30 | * PCI bus device function | ||
31 | */ | ||
32 | #define PCI_BUS_CS5536 0 | ||
33 | #define PCI_IDSEL_CS5536 14 | ||
34 | |||
35 | /********** STANDARD PCI-2.2 EXPANSION ****************/ | ||
36 | |||
37 | /* | ||
38 | * PCI configuration space | ||
39 | * we have to virtualize the PCI configure space head, so we should | ||
40 | * define the necessary IDs and some others. | ||
41 | */ | ||
42 | |||
43 | /* CONFIG of PCI VENDOR ID*/ | ||
44 | #define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \ | ||
45 | (((mod_dev_id) << 16) | (sys_vendor_id)) | ||
46 | |||
47 | /* VENDOR ID */ | ||
48 | #define CS5536_VENDOR_ID 0x1022 | ||
49 | |||
50 | /* DEVICE ID */ | ||
51 | #define CS5536_ISA_DEVICE_ID 0x2090 | ||
52 | #define CS5536_IDE_DEVICE_ID 0x209a | ||
53 | #define CS5536_ACC_DEVICE_ID 0x2093 | ||
54 | #define CS5536_OHCI_DEVICE_ID 0x2094 | ||
55 | #define CS5536_EHCI_DEVICE_ID 0x2095 | ||
56 | |||
57 | /* CLASS CODE : CLASS SUB-CLASS INTERFACE */ | ||
58 | #define CS5536_ISA_CLASS_CODE 0x060100 | ||
59 | #define CS5536_IDE_CLASS_CODE 0x010180 | ||
60 | #define CS5536_ACC_CLASS_CODE 0x040100 | ||
61 | #define CS5536_OHCI_CLASS_CODE 0x0C0310 | ||
62 | #define CS5536_EHCI_CLASS_CODE 0x0C0320 | ||
63 | |||
64 | /* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */ | ||
65 | |||
66 | #define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer) \ | ||
67 | ((PCI_NONE_BIST << 24) | ((header_type) << 16) \ | ||
68 | | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE); | ||
69 | |||
70 | #define PCI_NONE_BIST 0x00 /* RO not implemented yet. */ | ||
71 | #define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */ | ||
72 | #define PCI_NORMAL_HEADER_TYPE 0x00 | ||
73 | #define PCI_NORMAL_LATENCY_TIMER 0x00 | ||
74 | #define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */ | ||
75 | |||
76 | /* BAR */ | ||
77 | #define PCI_BAR0_REG 0x10 | ||
78 | #define PCI_BAR1_REG 0x14 | ||
79 | #define PCI_BAR2_REG 0x18 | ||
80 | #define PCI_BAR3_REG 0x1c | ||
81 | #define PCI_BAR4_REG 0x20 | ||
82 | #define PCI_BAR5_REG 0x24 | ||
83 | #define PCI_BAR_COUNT 6 | ||
84 | #define PCI_BAR_RANGE_MASK 0xFFFFFFFF | ||
85 | |||
86 | /* CARDBUS CIS POINTER */ | ||
87 | #define PCI_CARDBUS_CIS_POINTER 0x00000000 | ||
88 | |||
89 | /* SUBSYSTEM VENDOR ID */ | ||
90 | #define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID | ||
91 | |||
92 | /* SUBSYSTEM ID */ | ||
93 | #define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID | ||
94 | #define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID | ||
95 | #define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID | ||
96 | #define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID | ||
97 | #define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID | ||
98 | |||
99 | /* EXPANSION ROM BAR */ | ||
100 | #define PCI_EXPANSION_ROM_BAR 0x00000000 | ||
101 | |||
102 | /* CAPABILITIES POINTER */ | ||
103 | #define PCI_CAPLIST_POINTER 0x00000000 | ||
104 | #define PCI_CAPLIST_USB_POINTER 0x40 | ||
105 | /* INTERRUPT */ | ||
106 | |||
107 | #define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \ | ||
108 | ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \ | ||
109 | ((pin) << 8) | (mod_intr)) | ||
110 | |||
111 | #define PCI_MAX_LATENCY 0x40 | ||
112 | #define PCI_MIN_GRANT 0x00 | ||
113 | #define PCI_DEFAULT_PIN 0x01 | ||
114 | |||
115 | /*********** EXPANSION PCI REG ************************/ | ||
116 | |||
117 | /* | ||
118 | * ISA EXPANSION | ||
119 | */ | ||
120 | #define PCI_UART1_INT_REG 0x50 | ||
121 | #define PCI_UART2_INT_REG 0x54 | ||
122 | #define PCI_ISA_FIXUP_REG 0x58 | ||
123 | |||
124 | /* | ||
125 | * IDE EXPANSION | ||
126 | */ | ||
127 | #define PCI_IDE_CFG_REG 0x40 | ||
128 | #define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF | ||
129 | #define PCI_IDE_DTC_REG 0x48 | ||
130 | #define PCI_IDE_CAST_REG 0x4C | ||
131 | #define PCI_IDE_ETC_REG 0x50 | ||
132 | #define PCI_IDE_PM_REG 0x54 | ||
133 | #define PCI_IDE_INT_REG 0x60 | ||
134 | |||
135 | /* | ||
136 | * ACC EXPANSION | ||
137 | */ | ||
138 | #define PCI_ACC_INT_REG 0x50 | ||
139 | |||
140 | /* | ||
141 | * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI | ||
142 | */ | ||
143 | #define PCI_OHCI_PM_REG 0x40 | ||
144 | #define PCI_OHCI_INT_REG 0x50 | ||
145 | |||
146 | /* | ||
147 | * EHCI EXPANSION | ||
148 | */ | ||
149 | #define PCI_EHCI_LEGSMIEN_REG 0x50 | ||
150 | #define PCI_EHCI_LEGSMISTS_REG 0x54 | ||
151 | #define PCI_EHCI_FLADJ_REG 0x60 | ||
152 | |||
153 | #endif /* _CS5536_PCI_H_ */ | ||