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authorJohn Crispin <blogic@openwrt.org>2012-04-19 10:23:14 -0400
committerRalf Baechle <ralf@linux-mips.org>2012-05-26 14:52:57 -0400
commit009d6914f14d6c12a073e9ff8506a53047c308e7 (patch)
tree53ea742badb13e0ff55722b97ecce91ed26002b0 /arch/mips/include/asm/mach-lantiq/xway
parentd41ced01f21ddd2c3a01531bb9edf6c41064e9fc (diff)
MIPS: lantiq: remove orphaned code
Now that all drivers are converted to OF we are able to remove some remaining pieces of orphaned code. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3841/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-lantiq/xway')
-rw-r--r--arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h44
-rw-r--r--arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h90
2 files changed, 3 insertions, 131 deletions
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
index b4465a888e20..aa0b3b866f84 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
@@ -17,50 +17,8 @@
17#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128) 17#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
18#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) 18#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
19 19
20#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8))
21#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1)
22#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2)
23
24#define LTQ_ASC_ASE_TIR INT_NUM_IM2_IRL0
25#define LTQ_ASC_ASE_RIR (INT_NUM_IM2_IRL0 + 2)
26#define LTQ_ASC_ASE_EIR (INT_NUM_IM2_IRL0 + 3)
27
28#define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
29#define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
30#define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
31
32#define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
33#define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23)
34
35#define LTQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
36#define LTQ_USB_INT (INT_NUM_IM1_IRL0 + 22)
37#define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
38
39#define MIPS_CPU_TIMER_IRQ 7
40
41#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0) 20#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
42#define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
43#define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
44#define LTQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
45#define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
46#define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
47#define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
48#define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
49#define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
50#define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
51#define LTQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
52#define LTQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
53#define LTQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
54#define LTQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
55#define LTQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
56#define LTQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
57#define LTQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
58#define LTQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
59#define LTQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
60#define LTQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
61
62#define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24)
63 21
64#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14) 22#define MIPS_CPU_TIMER_IRQ 7
65 23
66#endif 24#endif
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index d0d40a42327c..6a2df709c576 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -44,11 +44,6 @@
44#define SOC_TYPE_VR9_2 0x05 /* v1.2 */ 44#define SOC_TYPE_VR9_2 0x05 /* v1.2 */
45#define SOC_TYPE_AMAZON_SE 0x06 45#define SOC_TYPE_AMAZON_SE 0x06
46 46
47/* ASC0/1 - serial port */
48#define LTQ_ASC0_BASE_ADDR 0x1E100400
49#define LTQ_ASC1_BASE_ADDR 0x1E100C00
50#define LTQ_ASC_SIZE 0x400
51
52/* BOOT_SEL - find what boot media we have */ 47/* BOOT_SEL - find what boot media we have */
53#define BS_EXT_ROM 0x0 48#define BS_EXT_ROM 0x0
54#define BS_FLASH 0x1 49#define BS_FLASH 0x1
@@ -68,23 +63,10 @@ extern __iomem void *ltq_cgu_membase;
68 * during early_printk no ioremap is possible 63 * during early_printk no ioremap is possible
69 * lets use KSEG1 instead 64 * lets use KSEG1 instead
70 */ 65 */
66#define LTQ_ASC1_BASE_ADDR 0x1E100C00
71#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR) 67#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
72 68
73/* RCU - reset control unit */
74#define LTQ_RCU_BASE_ADDR 0x1F203000
75#define LTQ_RCU_SIZE 0x1000
76
77/* GPTU - general purpose timer unit */
78#define LTQ_GPTU_BASE_ADDR 0x18000300
79#define LTQ_GPTU_SIZE 0x100
80
81/* EBU - external bus unit */ 69/* EBU - external bus unit */
82#define LTQ_EBU_GPIO_START 0x14000000
83#define LTQ_EBU_GPIO_SIZE 0x1000
84
85#define LTQ_EBU_BASE_ADDR 0x1E105300
86#define LTQ_EBU_SIZE 0x100
87
88#define LTQ_EBU_BUSCON0 0x0060 70#define LTQ_EBU_BUSCON0 0x0060
89#define LTQ_EBU_PCC_CON 0x0090 71#define LTQ_EBU_PCC_CON 0x0090
90#define LTQ_EBU_PCC_IEN 0x00A4 72#define LTQ_EBU_PCC_IEN 0x00A4
@@ -93,85 +75,17 @@ extern __iomem void *ltq_cgu_membase;
93#define LTQ_EBU_ADDRSEL1 0x0024 75#define LTQ_EBU_ADDRSEL1 0x0024
94#define EBU_WRDIS 0x80000000 76#define EBU_WRDIS 0x80000000
95 77
96/* CGU - clock generation unit */
97#define LTQ_CGU_BASE_ADDR 0x1F103000
98#define LTQ_CGU_SIZE 0x1000
99
100/* ICU - interrupt control unit */
101#define LTQ_ICU_BASE_ADDR 0x1F880200
102#define LTQ_ICU_SIZE 0x100
103
104/* EIU - external interrupt unit */
105#define LTQ_EIU_BASE_ADDR 0x1F101000
106#define LTQ_EIU_SIZE 0x1000
107
108/* PMU - power management unit */
109#define LTQ_PMU_BASE_ADDR 0x1F102000
110#define LTQ_PMU_SIZE 0x1000
111
112#define PMU_DMA 0x0020
113#define PMU_USB 0x8041
114#define PMU_LED 0x0800
115#define PMU_GPT 0x1000
116#define PMU_PPE 0x2000
117#define PMU_FPI 0x4000
118#define PMU_SWITCH 0x10000000
119
120/* ETOP - ethernet */
121#define LTQ_ETOP_BASE_ADDR 0x1E180000
122#define LTQ_ETOP_SIZE 0x40000
123
124/* DMA */
125#define LTQ_DMA_BASE_ADDR 0x1E104100
126#define LTQ_DMA_SIZE 0x800
127
128/* PCI */
129#define PCI_CR_BASE_ADDR 0x1E105400
130#define PCI_CR_SIZE 0x400
131
132/* WDT */ 78/* WDT */
133#define LTQ_WDT_BASE_ADDR 0x1F8803F0
134#define LTQ_WDT_SIZE 0x10
135
136#define LTQ_RST_CAUSE_WDTRST 0x20 79#define LTQ_RST_CAUSE_WDTRST 0x20
137 80
138/* STP - serial to parallel conversion unit */
139#define LTQ_STP_BASE_ADDR 0x1E100BB0
140#define LTQ_STP_SIZE 0x40
141
142/* GPIO */
143#define LTQ_GPIO0_BASE_ADDR 0x1E100B10
144#define LTQ_GPIO1_BASE_ADDR 0x1E100B40
145#define LTQ_GPIO2_BASE_ADDR 0x1E100B70
146#define LTQ_GPIO_SIZE 0x30
147
148/* SSC */
149#define LTQ_SSC_BASE_ADDR 0x1e100800
150#define LTQ_SSC_SIZE 0x100
151
152/* MEI - dsl core */
153#define LTQ_MEI_BASE_ADDR 0x1E116000
154
155/* DEU - data encryption unit */
156#define LTQ_DEU_BASE_ADDR 0x1E103100
157
158/* MPS - multi processor unit (voice) */ 81/* MPS - multi processor unit (voice) */
159#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) 82#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
160#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) 83#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
161 84
162/* request a non-gpio and set the PIO config */ 85/* request a non-gpio and set the PIO config */
86#define PMU_PPE BIT(13)
163extern void ltq_pmu_enable(unsigned int module); 87extern void ltq_pmu_enable(unsigned int module);
164extern void ltq_pmu_disable(unsigned int module); 88extern void ltq_pmu_disable(unsigned int module);
165 89
166static inline int ltq_is_ar9(void)
167{
168 return (ltq_get_soc_type() == SOC_TYPE_AR9);
169}
170
171static inline int ltq_is_vr9(void)
172{
173 return (ltq_get_soc_type() == SOC_TYPE_VR9);
174}
175
176#endif /* CONFIG_SOC_TYPE_XWAY */ 90#endif /* CONFIG_SOC_TYPE_XWAY */
177#endif /* _LTQ_XWAY_H__ */ 91#endif /* _LTQ_XWAY_H__ */
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