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authorMichal Marek <mmarek@suse.cz>2010-10-12 09:09:06 -0400
committerMichal Marek <mmarek@suse.cz>2010-10-12 09:09:06 -0400
commit239060b93bb30a4ad55f1ecaa512464a035cc5ba (patch)
tree77f79810e57d4fc24356eca0cd6db463e8994128 /arch/mips/include/asm/mach-cavium-octeon
parent1408b15b98635a13bad2e2a50b3c2ae2ccdf625b (diff)
parente9203c988234aa512bd45ca32b52e21c7bbfc414 (diff)
Merge branch 'kbuild/rc-fixes' into kbuild/kconfig
We need to revert the temporary hack in 71ebc01, hence the merge.
Diffstat (limited to 'arch/mips/include/asm/mach-cavium-octeon')
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h15
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/irq.h66
2 files changed, 8 insertions, 73 deletions
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index bbf054042395..b952fc7215e2 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -61,21 +61,18 @@
61 61
62#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS) 62#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
63 63
64#define ARCH_HAS_READ_CURRENT_TIMER 1
65#define ARCH_HAS_IRQ_PER_CPU 1 64#define ARCH_HAS_IRQ_PER_CPU 1
66#define ARCH_HAS_SPINLOCK_PREFETCH 1 65#define ARCH_HAS_SPINLOCK_PREFETCH 1
67#define spin_lock_prefetch(x) prefetch(x) 66#define spin_lock_prefetch(x) prefetch(x)
68#define PREFETCH_STRIDE 128 67#define PREFETCH_STRIDE 128
69 68
70static inline int read_current_timer(unsigned long *result) 69#ifdef __OCTEON__
71{ 70/*
72 asm volatile ("rdhwr %0,$31\n" 71 * All gcc versions that have OCTEON support define __OCTEON__ and have the
73#ifndef CONFIG_64BIT 72 * __builtin_popcount support.
74 "\tsll %0, 0" 73 */
74#define ARCH_HAS_USABLE_BUILTIN_POPCOUNT 1
75#endif 75#endif
76 : "=r" (*result));
77 return 0;
78}
79 76
80static inline int octeon_has_saa(void) 77static inline int octeon_has_saa(void)
81{ 78{
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index d32220fbf4f1..6ddab8aef644 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -172,71 +172,9 @@
172#ifdef CONFIG_PCI_MSI 172#ifdef CONFIG_PCI_MSI
173/* 152 - 215 represent the MSI interrupts 0-63 */ 173/* 152 - 215 represent the MSI interrupts 0-63 */
174#define OCTEON_IRQ_MSI_BIT0 152 174#define OCTEON_IRQ_MSI_BIT0 152
175#define OCTEON_IRQ_MSI_BIT1 153 175#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
176#define OCTEON_IRQ_MSI_BIT2 154
177#define OCTEON_IRQ_MSI_BIT3 155
178#define OCTEON_IRQ_MSI_BIT4 156
179#define OCTEON_IRQ_MSI_BIT5 157
180#define OCTEON_IRQ_MSI_BIT6 158
181#define OCTEON_IRQ_MSI_BIT7 159
182#define OCTEON_IRQ_MSI_BIT8 160
183#define OCTEON_IRQ_MSI_BIT9 161
184#define OCTEON_IRQ_MSI_BIT10 162
185#define OCTEON_IRQ_MSI_BIT11 163
186#define OCTEON_IRQ_MSI_BIT12 164
187#define OCTEON_IRQ_MSI_BIT13 165
188#define OCTEON_IRQ_MSI_BIT14 166
189#define OCTEON_IRQ_MSI_BIT15 167
190#define OCTEON_IRQ_MSI_BIT16 168
191#define OCTEON_IRQ_MSI_BIT17 169
192#define OCTEON_IRQ_MSI_BIT18 170
193#define OCTEON_IRQ_MSI_BIT19 171
194#define OCTEON_IRQ_MSI_BIT20 172
195#define OCTEON_IRQ_MSI_BIT21 173
196#define OCTEON_IRQ_MSI_BIT22 174
197#define OCTEON_IRQ_MSI_BIT23 175
198#define OCTEON_IRQ_MSI_BIT24 176
199#define OCTEON_IRQ_MSI_BIT25 177
200#define OCTEON_IRQ_MSI_BIT26 178
201#define OCTEON_IRQ_MSI_BIT27 179
202#define OCTEON_IRQ_MSI_BIT28 180
203#define OCTEON_IRQ_MSI_BIT29 181
204#define OCTEON_IRQ_MSI_BIT30 182
205#define OCTEON_IRQ_MSI_BIT31 183
206#define OCTEON_IRQ_MSI_BIT32 184
207#define OCTEON_IRQ_MSI_BIT33 185
208#define OCTEON_IRQ_MSI_BIT34 186
209#define OCTEON_IRQ_MSI_BIT35 187
210#define OCTEON_IRQ_MSI_BIT36 188
211#define OCTEON_IRQ_MSI_BIT37 189
212#define OCTEON_IRQ_MSI_BIT38 190
213#define OCTEON_IRQ_MSI_BIT39 191
214#define OCTEON_IRQ_MSI_BIT40 192
215#define OCTEON_IRQ_MSI_BIT41 193
216#define OCTEON_IRQ_MSI_BIT42 194
217#define OCTEON_IRQ_MSI_BIT43 195
218#define OCTEON_IRQ_MSI_BIT44 196
219#define OCTEON_IRQ_MSI_BIT45 197
220#define OCTEON_IRQ_MSI_BIT46 198
221#define OCTEON_IRQ_MSI_BIT47 199
222#define OCTEON_IRQ_MSI_BIT48 200
223#define OCTEON_IRQ_MSI_BIT49 201
224#define OCTEON_IRQ_MSI_BIT50 202
225#define OCTEON_IRQ_MSI_BIT51 203
226#define OCTEON_IRQ_MSI_BIT52 204
227#define OCTEON_IRQ_MSI_BIT53 205
228#define OCTEON_IRQ_MSI_BIT54 206
229#define OCTEON_IRQ_MSI_BIT55 207
230#define OCTEON_IRQ_MSI_BIT56 208
231#define OCTEON_IRQ_MSI_BIT57 209
232#define OCTEON_IRQ_MSI_BIT58 210
233#define OCTEON_IRQ_MSI_BIT59 211
234#define OCTEON_IRQ_MSI_BIT60 212
235#define OCTEON_IRQ_MSI_BIT61 213
236#define OCTEON_IRQ_MSI_BIT62 214
237#define OCTEON_IRQ_MSI_BIT63 215
238 176
239#define OCTEON_IRQ_LAST 216 177#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
240#else 178#else
241#define OCTEON_IRQ_LAST 152 179#define OCTEON_IRQ_LAST 152
242#endif 180#endif