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authorMaxime Bizon <mbizon@freebox.fr>2009-08-18 08:23:37 -0400
committerRalf Baechle <ralf@linux-mips.org>2009-09-17 14:07:52 -0400
commite7300d04bd0809eb7ea10a2ed8c729459f816e36 (patch)
tree8af589d3954c09323d3f74e69aa6fabbb32e049e /arch/mips/include/asm/mach-bcm63xx
parent0de663ef8627f35fda9106a8faaca512f29e493e (diff)
MIPS: BCM63xx: Add support for the Broadcom BCM63xx family of SOCs.
Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-bcm63xx')
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h12
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h11
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h538
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h10
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h13
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h45
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h6
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h22
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h93
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h15
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h773
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h11
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h60
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h51
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/gpio.h15
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/war.h25
16 files changed, 1700 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h
new file mode 100644
index 000000000000..fa3e7e617b09
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h
@@ -0,0 +1,12 @@
1#ifndef BCM63XX_BOARD_H_
2#define BCM63XX_BOARD_H_
3
4const char *board_get_name(void);
5
6void board_prom_init(void);
7
8void board_setup(void);
9
10int board_register_devices(void);
11
12#endif /* ! BCM63XX_BOARD_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h
new file mode 100644
index 000000000000..8fcf8df4418a
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h
@@ -0,0 +1,11 @@
1#ifndef BCM63XX_CLK_H_
2#define BCM63XX_CLK_H_
3
4struct clk {
5 void (*set)(struct clk *, int);
6 unsigned int rate;
7 unsigned int usage;
8 int id;
9};
10
11#endif /* ! BCM63XX_CLK_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
new file mode 100644
index 000000000000..b12c4aca2cc9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -0,0 +1,538 @@
1#ifndef BCM63XX_CPU_H_
2#define BCM63XX_CPU_H_
3
4#include <linux/types.h>
5#include <linux/init.h>
6
7/*
8 * Macro to fetch bcm63xx cpu id and revision, should be optimized at
9 * compile time if only one CPU support is enabled (idea stolen from
10 * arm mach-types)
11 */
12#define BCM6338_CPU_ID 0x6338
13#define BCM6345_CPU_ID 0x6345
14#define BCM6348_CPU_ID 0x6348
15#define BCM6358_CPU_ID 0x6358
16
17void __init bcm63xx_cpu_init(void);
18u16 __bcm63xx_get_cpu_id(void);
19u16 bcm63xx_get_cpu_rev(void);
20unsigned int bcm63xx_get_cpu_freq(void);
21
22#ifdef CONFIG_BCM63XX_CPU_6338
23# ifdef bcm63xx_get_cpu_id
24# undef bcm63xx_get_cpu_id
25# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
26# define BCMCPU_RUNTIME_DETECT
27# else
28# define bcm63xx_get_cpu_id() BCM6338_CPU_ID
29# endif
30# define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
31#else
32# define BCMCPU_IS_6338() (0)
33#endif
34
35#ifdef CONFIG_BCM63XX_CPU_6345
36# ifdef bcm63xx_get_cpu_id
37# undef bcm63xx_get_cpu_id
38# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
39# define BCMCPU_RUNTIME_DETECT
40# else
41# define bcm63xx_get_cpu_id() BCM6345_CPU_ID
42# endif
43# define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
44#else
45# define BCMCPU_IS_6345() (0)
46#endif
47
48#ifdef CONFIG_BCM63XX_CPU_6348
49# ifdef bcm63xx_get_cpu_id
50# undef bcm63xx_get_cpu_id
51# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
52# define BCMCPU_RUNTIME_DETECT
53# else
54# define bcm63xx_get_cpu_id() BCM6348_CPU_ID
55# endif
56# define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
57#else
58# define BCMCPU_IS_6348() (0)
59#endif
60
61#ifdef CONFIG_BCM63XX_CPU_6358
62# ifdef bcm63xx_get_cpu_id
63# undef bcm63xx_get_cpu_id
64# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
65# define BCMCPU_RUNTIME_DETECT
66# else
67# define bcm63xx_get_cpu_id() BCM6358_CPU_ID
68# endif
69# define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
70#else
71# define BCMCPU_IS_6358() (0)
72#endif
73
74#ifndef bcm63xx_get_cpu_id
75#error "No CPU support configured"
76#endif
77
78/*
79 * While registers sets are (mostly) the same across 63xx CPU, base
80 * address of these sets do change.
81 */
82enum bcm63xx_regs_set {
83 RSET_DSL_LMEM = 0,
84 RSET_PERF,
85 RSET_TIMER,
86 RSET_WDT,
87 RSET_UART0,
88 RSET_GPIO,
89 RSET_SPI,
90 RSET_UDC0,
91 RSET_OHCI0,
92 RSET_OHCI_PRIV,
93 RSET_USBH_PRIV,
94 RSET_MPI,
95 RSET_PCMCIA,
96 RSET_DSL,
97 RSET_ENET0,
98 RSET_ENET1,
99 RSET_ENETDMA,
100 RSET_EHCI0,
101 RSET_SDRAM,
102 RSET_MEMC,
103 RSET_DDR,
104};
105
106#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
107#define RSET_DSL_SIZE 4096
108#define RSET_WDT_SIZE 12
109#define RSET_ENET_SIZE 2048
110#define RSET_ENETDMA_SIZE 2048
111#define RSET_UART_SIZE 24
112#define RSET_UDC_SIZE 256
113#define RSET_OHCI_SIZE 256
114#define RSET_EHCI_SIZE 256
115#define RSET_PCMCIA_SIZE 12
116
117/*
118 * 6338 register sets base address
119 */
120#define BCM_6338_DSL_LMEM_BASE (0xfff00000)
121#define BCM_6338_PERF_BASE (0xfffe0000)
122#define BCM_6338_BB_BASE (0xfffe0100)
123#define BCM_6338_TIMER_BASE (0xfffe0200)
124#define BCM_6338_WDT_BASE (0xfffe021c)
125#define BCM_6338_UART0_BASE (0xfffe0300)
126#define BCM_6338_GPIO_BASE (0xfffe0400)
127#define BCM_6338_SPI_BASE (0xfffe0c00)
128#define BCM_6338_UDC0_BASE (0xdeadbeef)
129#define BCM_6338_USBDMA_BASE (0xfffe2400)
130#define BCM_6338_OHCI0_BASE (0xdeadbeef)
131#define BCM_6338_OHCI_PRIV_BASE (0xfffe3000)
132#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
133#define BCM_6338_MPI_BASE (0xfffe3160)
134#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
135#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
136#define BCM_6338_DSL_BASE (0xfffe1000)
137#define BCM_6338_SAR_BASE (0xfffe2000)
138#define BCM_6338_UBUS_BASE (0xdeadbeef)
139#define BCM_6338_ENET0_BASE (0xfffe2800)
140#define BCM_6338_ENET1_BASE (0xdeadbeef)
141#define BCM_6338_ENETDMA_BASE (0xfffe2400)
142#define BCM_6338_EHCI0_BASE (0xdeadbeef)
143#define BCM_6338_SDRAM_BASE (0xfffe3100)
144#define BCM_6338_MEMC_BASE (0xdeadbeef)
145#define BCM_6338_DDR_BASE (0xdeadbeef)
146
147/*
148 * 6345 register sets base address
149 */
150#define BCM_6345_DSL_LMEM_BASE (0xfff00000)
151#define BCM_6345_PERF_BASE (0xfffe0000)
152#define BCM_6345_BB_BASE (0xfffe0100)
153#define BCM_6345_TIMER_BASE (0xfffe0200)
154#define BCM_6345_WDT_BASE (0xfffe021c)
155#define BCM_6345_UART0_BASE (0xfffe0300)
156#define BCM_6345_GPIO_BASE (0xfffe0400)
157#define BCM_6345_SPI_BASE (0xdeadbeef)
158#define BCM_6345_UDC0_BASE (0xdeadbeef)
159#define BCM_6345_USBDMA_BASE (0xfffe2800)
160#define BCM_6345_ENET0_BASE (0xfffe1800)
161#define BCM_6345_ENETDMA_BASE (0xfffe2800)
162#define BCM_6345_PCMCIA_BASE (0xfffe2028)
163#define BCM_6345_MPI_BASE (0xdeadbeef)
164#define BCM_6345_OHCI0_BASE (0xfffe2100)
165#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
166#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
167#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
168#define BCM_6345_DSL_BASE (0xdeadbeef)
169#define BCM_6345_SAR_BASE (0xdeadbeef)
170#define BCM_6345_UBUS_BASE (0xdeadbeef)
171#define BCM_6345_ENET1_BASE (0xdeadbeef)
172#define BCM_6345_EHCI0_BASE (0xdeadbeef)
173#define BCM_6345_SDRAM_BASE (0xfffe2300)
174#define BCM_6345_MEMC_BASE (0xdeadbeef)
175#define BCM_6345_DDR_BASE (0xdeadbeef)
176
177/*
178 * 6348 register sets base address
179 */
180#define BCM_6348_DSL_LMEM_BASE (0xfff00000)
181#define BCM_6348_PERF_BASE (0xfffe0000)
182#define BCM_6348_TIMER_BASE (0xfffe0200)
183#define BCM_6348_WDT_BASE (0xfffe021c)
184#define BCM_6348_UART0_BASE (0xfffe0300)
185#define BCM_6348_GPIO_BASE (0xfffe0400)
186#define BCM_6348_SPI_BASE (0xfffe0c00)
187#define BCM_6348_UDC0_BASE (0xfffe1000)
188#define BCM_6348_OHCI0_BASE (0xfffe1b00)
189#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
190#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
191#define BCM_6348_MPI_BASE (0xfffe2000)
192#define BCM_6348_PCMCIA_BASE (0xfffe2054)
193#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
194#define BCM_6348_DSL_BASE (0xfffe3000)
195#define BCM_6348_ENET0_BASE (0xfffe6000)
196#define BCM_6348_ENET1_BASE (0xfffe6800)
197#define BCM_6348_ENETDMA_BASE (0xfffe7000)
198#define BCM_6348_EHCI0_BASE (0xdeadbeef)
199#define BCM_6348_SDRAM_BASE (0xfffe2300)
200#define BCM_6348_MEMC_BASE (0xdeadbeef)
201#define BCM_6348_DDR_BASE (0xdeadbeef)
202
203/*
204 * 6358 register sets base address
205 */
206#define BCM_6358_DSL_LMEM_BASE (0xfff00000)
207#define BCM_6358_PERF_BASE (0xfffe0000)
208#define BCM_6358_TIMER_BASE (0xfffe0040)
209#define BCM_6358_WDT_BASE (0xfffe005c)
210#define BCM_6358_UART0_BASE (0xfffe0100)
211#define BCM_6358_GPIO_BASE (0xfffe0080)
212#define BCM_6358_SPI_BASE (0xdeadbeef)
213#define BCM_6358_UDC0_BASE (0xfffe0800)
214#define BCM_6358_OHCI0_BASE (0xfffe1400)
215#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
216#define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
217#define BCM_6358_MPI_BASE (0xfffe1000)
218#define BCM_6358_PCMCIA_BASE (0xfffe1054)
219#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
220#define BCM_6358_DSL_BASE (0xfffe3000)
221#define BCM_6358_ENET0_BASE (0xfffe4000)
222#define BCM_6358_ENET1_BASE (0xfffe4800)
223#define BCM_6358_ENETDMA_BASE (0xfffe5000)
224#define BCM_6358_EHCI0_BASE (0xfffe1300)
225#define BCM_6358_SDRAM_BASE (0xdeadbeef)
226#define BCM_6358_MEMC_BASE (0xfffe1200)
227#define BCM_6358_DDR_BASE (0xfffe12a0)
228
229
230extern const unsigned long *bcm63xx_regs_base;
231
232static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
233{
234#ifdef BCMCPU_RUNTIME_DETECT
235 return bcm63xx_regs_base[set];
236#else
237#ifdef CONFIG_BCM63XX_CPU_6338
238 switch (set) {
239 case RSET_DSL_LMEM:
240 return BCM_6338_DSL_LMEM_BASE;
241 case RSET_PERF:
242 return BCM_6338_PERF_BASE;
243 case RSET_TIMER:
244 return BCM_6338_TIMER_BASE;
245 case RSET_WDT:
246 return BCM_6338_WDT_BASE;
247 case RSET_UART0:
248 return BCM_6338_UART0_BASE;
249 case RSET_GPIO:
250 return BCM_6338_GPIO_BASE;
251 case RSET_SPI:
252 return BCM_6338_SPI_BASE;
253 case RSET_UDC0:
254 return BCM_6338_UDC0_BASE;
255 case RSET_OHCI0:
256 return BCM_6338_OHCI0_BASE;
257 case RSET_OHCI_PRIV:
258 return BCM_6338_OHCI_PRIV_BASE;
259 case RSET_USBH_PRIV:
260 return BCM_6338_USBH_PRIV_BASE;
261 case RSET_MPI:
262 return BCM_6338_MPI_BASE;
263 case RSET_PCMCIA:
264 return BCM_6338_PCMCIA_BASE;
265 case RSET_DSL:
266 return BCM_6338_DSL_BASE;
267 case RSET_ENET0:
268 return BCM_6338_ENET0_BASE;
269 case RSET_ENET1:
270 return BCM_6338_ENET1_BASE;
271 case RSET_ENETDMA:
272 return BCM_6338_ENETDMA_BASE;
273 case RSET_EHCI0:
274 return BCM_6338_EHCI0_BASE;
275 case RSET_SDRAM:
276 return BCM_6338_SDRAM_BASE;
277 case RSET_MEMC:
278 return BCM_6338_MEMC_BASE;
279 case RSET_DDR:
280 return BCM_6338_DDR_BASE;
281 }
282#endif
283#ifdef CONFIG_BCM63XX_CPU_6345
284 switch (set) {
285 case RSET_DSL_LMEM:
286 return BCM_6345_DSL_LMEM_BASE;
287 case RSET_PERF:
288 return BCM_6345_PERF_BASE;
289 case RSET_TIMER:
290 return BCM_6345_TIMER_BASE;
291 case RSET_WDT:
292 return BCM_6345_WDT_BASE;
293 case RSET_UART0:
294 return BCM_6345_UART0_BASE;
295 case RSET_GPIO:
296 return BCM_6345_GPIO_BASE;
297 case RSET_SPI:
298 return BCM_6345_SPI_BASE;
299 case RSET_UDC0:
300 return BCM_6345_UDC0_BASE;
301 case RSET_OHCI0:
302 return BCM_6345_OHCI0_BASE;
303 case RSET_OHCI_PRIV:
304 return BCM_6345_OHCI_PRIV_BASE;
305 case RSET_USBH_PRIV:
306 return BCM_6345_USBH_PRIV_BASE;
307 case RSET_MPI:
308 return BCM_6345_MPI_BASE;
309 case RSET_PCMCIA:
310 return BCM_6345_PCMCIA_BASE;
311 case RSET_DSL:
312 return BCM_6345_DSL_BASE;
313 case RSET_ENET0:
314 return BCM_6345_ENET0_BASE;
315 case RSET_ENET1:
316 return BCM_6345_ENET1_BASE;
317 case RSET_ENETDMA:
318 return BCM_6345_ENETDMA_BASE;
319 case RSET_EHCI0:
320 return BCM_6345_EHCI0_BASE;
321 case RSET_SDRAM:
322 return BCM_6345_SDRAM_BASE;
323 case RSET_MEMC:
324 return BCM_6345_MEMC_BASE;
325 case RSET_DDR:
326 return BCM_6345_DDR_BASE;
327 }
328#endif
329#ifdef CONFIG_BCM63XX_CPU_6348
330 switch (set) {
331 case RSET_DSL_LMEM:
332 return BCM_6348_DSL_LMEM_BASE;
333 case RSET_PERF:
334 return BCM_6348_PERF_BASE;
335 case RSET_TIMER:
336 return BCM_6348_TIMER_BASE;
337 case RSET_WDT:
338 return BCM_6348_WDT_BASE;
339 case RSET_UART0:
340 return BCM_6348_UART0_BASE;
341 case RSET_GPIO:
342 return BCM_6348_GPIO_BASE;
343 case RSET_SPI:
344 return BCM_6348_SPI_BASE;
345 case RSET_UDC0:
346 return BCM_6348_UDC0_BASE;
347 case RSET_OHCI0:
348 return BCM_6348_OHCI0_BASE;
349 case RSET_OHCI_PRIV:
350 return BCM_6348_OHCI_PRIV_BASE;
351 case RSET_USBH_PRIV:
352 return BCM_6348_USBH_PRIV_BASE;
353 case RSET_MPI:
354 return BCM_6348_MPI_BASE;
355 case RSET_PCMCIA:
356 return BCM_6348_PCMCIA_BASE;
357 case RSET_DSL:
358 return BCM_6348_DSL_BASE;
359 case RSET_ENET0:
360 return BCM_6348_ENET0_BASE;
361 case RSET_ENET1:
362 return BCM_6348_ENET1_BASE;
363 case RSET_ENETDMA:
364 return BCM_6348_ENETDMA_BASE;
365 case RSET_EHCI0:
366 return BCM_6348_EHCI0_BASE;
367 case RSET_SDRAM:
368 return BCM_6348_SDRAM_BASE;
369 case RSET_MEMC:
370 return BCM_6348_MEMC_BASE;
371 case RSET_DDR:
372 return BCM_6348_DDR_BASE;
373 }
374#endif
375#ifdef CONFIG_BCM63XX_CPU_6358
376 switch (set) {
377 case RSET_DSL_LMEM:
378 return BCM_6358_DSL_LMEM_BASE;
379 case RSET_PERF:
380 return BCM_6358_PERF_BASE;
381 case RSET_TIMER:
382 return BCM_6358_TIMER_BASE;
383 case RSET_WDT:
384 return BCM_6358_WDT_BASE;
385 case RSET_UART0:
386 return BCM_6358_UART0_BASE;
387 case RSET_GPIO:
388 return BCM_6358_GPIO_BASE;
389 case RSET_SPI:
390 return BCM_6358_SPI_BASE;
391 case RSET_UDC0:
392 return BCM_6358_UDC0_BASE;
393 case RSET_OHCI0:
394 return BCM_6358_OHCI0_BASE;
395 case RSET_OHCI_PRIV:
396 return BCM_6358_OHCI_PRIV_BASE;
397 case RSET_USBH_PRIV:
398 return BCM_6358_USBH_PRIV_BASE;
399 case RSET_MPI:
400 return BCM_6358_MPI_BASE;
401 case RSET_PCMCIA:
402 return BCM_6358_PCMCIA_BASE;
403 case RSET_ENET0:
404 return BCM_6358_ENET0_BASE;
405 case RSET_ENET1:
406 return BCM_6358_ENET1_BASE;
407 case RSET_ENETDMA:
408 return BCM_6358_ENETDMA_BASE;
409 case RSET_DSL:
410 return BCM_6358_DSL_BASE;
411 case RSET_EHCI0:
412 return BCM_6358_EHCI0_BASE;
413 case RSET_SDRAM:
414 return BCM_6358_SDRAM_BASE;
415 case RSET_MEMC:
416 return BCM_6358_MEMC_BASE;
417 case RSET_DDR:
418 return BCM_6358_DDR_BASE;
419 }
420#endif
421#endif
422 /* unreached */
423 return 0;
424}
425
426/*
427 * IRQ number changes across CPU too
428 */
429enum bcm63xx_irq {
430 IRQ_TIMER = 0,
431 IRQ_UART0,
432 IRQ_DSL,
433 IRQ_ENET0,
434 IRQ_ENET1,
435 IRQ_ENET_PHY,
436 IRQ_OHCI0,
437 IRQ_EHCI0,
438 IRQ_PCMCIA0,
439 IRQ_ENET0_RXDMA,
440 IRQ_ENET0_TXDMA,
441 IRQ_ENET1_RXDMA,
442 IRQ_ENET1_TXDMA,
443 IRQ_PCI,
444 IRQ_PCMCIA,
445};
446
447/*
448 * 6338 irqs
449 */
450#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
451#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
452#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
453#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4)
454#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
455#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
456#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
457#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
458#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
459#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10)
460#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11)
461#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
462#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
463#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
464#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
465#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
466#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17)
467
468/*
469 * 6345 irqs
470 */
471#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
472#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
473#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
474#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
475#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
476#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
477#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
478#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
479#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
480#define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5)
481#define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6)
482#define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9)
483#define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10)
484#define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13)
485#define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14)
486#define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15)
487#define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16)
488#define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17)
489#define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18)
490
491/*
492 * 6348 irqs
493 */
494#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
495#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
496#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
497#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
498#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
499#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
500#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
501#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
502#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
503#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
504#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
505#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
506#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
507
508/*
509 * 6358 irqs
510 */
511#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
512#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
513#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
514#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
515#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
516#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
517#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
518#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
519#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
520#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
521#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
522#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
523#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
524#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
525
526extern const int *bcm63xx_irqs;
527
528static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
529{
530 return bcm63xx_irqs[irq];
531}
532
533/*
534 * return installed memory size
535 */
536unsigned int bcm63xx_get_memory_size(void);
537
538#endif /* !BCM63XX_CPU_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h
new file mode 100644
index 000000000000..b1821c866e53
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h
@@ -0,0 +1,10 @@
1#ifndef BCM63XX_CS_H
2#define BCM63XX_CS_H
3
4int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size);
5int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
6 unsigned int setup, unsigned int hold);
7int bcm63xx_set_cs_param(unsigned int cs, u32 flags);
8int bcm63xx_set_cs_status(unsigned int cs, int enable);
9
10#endif /* !BCM63XX_CS_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h
new file mode 100644
index 000000000000..b587d45c3045
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h
@@ -0,0 +1,13 @@
1#ifndef __BCM63XX_DSP_H
2#define __BCM63XX_DSP_H
3
4struct bcm63xx_dsp_platform_data {
5 unsigned gpio_rst;
6 unsigned gpio_int;
7 unsigned cs;
8 unsigned ext_irq;
9};
10
11int __init bcm63xx_dsp_register(const struct bcm63xx_dsp_platform_data *pd);
12
13#endif /* __BCM63XX_DSP_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
new file mode 100644
index 000000000000..d53f611184b9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
@@ -0,0 +1,45 @@
1#ifndef BCM63XX_DEV_ENET_H_
2#define BCM63XX_DEV_ENET_H_
3
4#include <linux/if_ether.h>
5#include <linux/init.h>
6
7/*
8 * on board ethernet platform data
9 */
10struct bcm63xx_enet_platform_data {
11 char mac_addr[ETH_ALEN];
12
13 int has_phy;
14
15 /* if has_phy, then set use_internal_phy */
16 int use_internal_phy;
17
18 /* or fill phy info to use an external one */
19 int phy_id;
20 int has_phy_interrupt;
21 int phy_interrupt;
22
23 /* if has_phy, use autonegociated pause parameters or force
24 * them */
25 int pause_auto;
26 int pause_rx;
27 int pause_tx;
28
29 /* if !has_phy, set desired forced speed/duplex */
30 int force_speed_100;
31 int force_duplex_full;
32
33 /* if !has_phy, set callback to perform mii device
34 * init/remove */
35 int (*mii_config)(struct net_device *dev, int probe,
36 int (*mii_read)(struct net_device *dev,
37 int phy_id, int reg),
38 void (*mii_write)(struct net_device *dev,
39 int phy_id, int reg, int val));
40};
41
42int __init bcm63xx_enet_register(int unit,
43 const struct bcm63xx_enet_platform_data *pd);
44
45#endif /* ! BCM63XX_DEV_ENET_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h
new file mode 100644
index 000000000000..c549344b70ad
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h
@@ -0,0 +1,6 @@
1#ifndef BCM63XX_DEV_PCI_H_
2#define BCM63XX_DEV_PCI_H_
3
4extern int bcm63xx_pci_enabled;
5
6#endif /* BCM63XX_DEV_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
new file mode 100644
index 000000000000..76a0b7216af5
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -0,0 +1,22 @@
1#ifndef BCM63XX_GPIO_H
2#define BCM63XX_GPIO_H
3
4#include <linux/init.h>
5
6int __init bcm63xx_gpio_init(void);
7
8static inline unsigned long bcm63xx_gpio_count(void)
9{
10 switch (bcm63xx_get_cpu_id()) {
11 case BCM6358_CPU_ID:
12 return 40;
13 case BCM6348_CPU_ID:
14 default:
15 return 37;
16 }
17}
18
19#define GPIO_DIR_OUT 0x0
20#define GPIO_DIR_IN 0x1
21
22#endif /* !BCM63XX_GPIO_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
new file mode 100644
index 000000000000..91180fac6ed9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -0,0 +1,93 @@
1#ifndef BCM63XX_IO_H_
2#define BCM63XX_IO_H_
3
4#include "bcm63xx_cpu.h"
5
6/*
7 * Physical memory map, RAM is mapped at 0x0.
8 *
9 * Note that size MUST be a power of two.
10 */
11#define BCM_PCMCIA_COMMON_BASE_PA (0x20000000)
12#define BCM_PCMCIA_COMMON_SIZE (16 * 1024 * 1024)
13#define BCM_PCMCIA_COMMON_END_PA (BCM_PCMCIA_COMMON_BASE_PA + \
14 BCM_PCMCIA_COMMON_SIZE - 1)
15
16#define BCM_PCMCIA_ATTR_BASE_PA (0x21000000)
17#define BCM_PCMCIA_ATTR_SIZE (16 * 1024 * 1024)
18#define BCM_PCMCIA_ATTR_END_PA (BCM_PCMCIA_ATTR_BASE_PA + \
19 BCM_PCMCIA_ATTR_SIZE - 1)
20
21#define BCM_PCMCIA_IO_BASE_PA (0x22000000)
22#define BCM_PCMCIA_IO_SIZE (64 * 1024)
23#define BCM_PCMCIA_IO_END_PA (BCM_PCMCIA_IO_BASE_PA + \
24 BCM_PCMCIA_IO_SIZE - 1)
25
26#define BCM_PCI_MEM_BASE_PA (0x30000000)
27#define BCM_PCI_MEM_SIZE (128 * 1024 * 1024)
28#define BCM_PCI_MEM_END_PA (BCM_PCI_MEM_BASE_PA + \
29 BCM_PCI_MEM_SIZE - 1)
30
31#define BCM_PCI_IO_BASE_PA (0x08000000)
32#define BCM_PCI_IO_SIZE (64 * 1024)
33#define BCM_PCI_IO_END_PA (BCM_PCI_IO_BASE_PA + \
34 BCM_PCI_IO_SIZE - 1)
35#define BCM_PCI_IO_HALF_PA (BCM_PCI_IO_BASE_PA + \
36 (BCM_PCI_IO_SIZE / 2) - 1)
37
38#define BCM_CB_MEM_BASE_PA (0x38000000)
39#define BCM_CB_MEM_SIZE (128 * 1024 * 1024)
40#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \
41 BCM_CB_MEM_SIZE - 1)
42
43
44/*
45 * Internal registers are accessed through KSEG3
46 */
47#define BCM_REGS_VA(x) ((void __iomem *)(x))
48
49#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a))
50#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a))
51#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a))
52#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
53#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
54#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
55
56/*
57 * IO helpers to access register set for current CPU
58 */
59#define bcm_rset_readb(s, o) bcm_readb(bcm63xx_regset_address(s) + (o))
60#define bcm_rset_readw(s, o) bcm_readw(bcm63xx_regset_address(s) + (o))
61#define bcm_rset_readl(s, o) bcm_readl(bcm63xx_regset_address(s) + (o))
62#define bcm_rset_writeb(s, v, o) bcm_writeb((v), \
63 bcm63xx_regset_address(s) + (o))
64#define bcm_rset_writew(s, v, o) bcm_writew((v), \
65 bcm63xx_regset_address(s) + (o))
66#define bcm_rset_writel(s, v, o) bcm_writel((v), \
67 bcm63xx_regset_address(s) + (o))
68
69/*
70 * helpers for frequently used register sets
71 */
72#define bcm_perf_readl(o) bcm_rset_readl(RSET_PERF, (o))
73#define bcm_perf_writel(v, o) bcm_rset_writel(RSET_PERF, (v), (o))
74#define bcm_timer_readl(o) bcm_rset_readl(RSET_TIMER, (o))
75#define bcm_timer_writel(v, o) bcm_rset_writel(RSET_TIMER, (v), (o))
76#define bcm_wdt_readl(o) bcm_rset_readl(RSET_WDT, (o))
77#define bcm_wdt_writel(v, o) bcm_rset_writel(RSET_WDT, (v), (o))
78#define bcm_gpio_readl(o) bcm_rset_readl(RSET_GPIO, (o))
79#define bcm_gpio_writel(v, o) bcm_rset_writel(RSET_GPIO, (v), (o))
80#define bcm_uart0_readl(o) bcm_rset_readl(RSET_UART0, (o))
81#define bcm_uart0_writel(v, o) bcm_rset_writel(RSET_UART0, (v), (o))
82#define bcm_mpi_readl(o) bcm_rset_readl(RSET_MPI, (o))
83#define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o))
84#define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o))
85#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
86#define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o))
87#define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o))
88#define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o))
89#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o))
90#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o))
91#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
92
93#endif /* ! BCM63XX_IO_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
new file mode 100644
index 000000000000..5f95577c8213
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
@@ -0,0 +1,15 @@
1#ifndef BCM63XX_IRQ_H_
2#define BCM63XX_IRQ_H_
3
4#include <bcm63xx_cpu.h>
5
6#define IRQ_MIPS_BASE 0
7#define IRQ_INTERNAL_BASE 8
8
9#define IRQ_EXT_BASE (IRQ_MIPS_BASE + 3)
10#define IRQ_EXT_0 (IRQ_EXT_BASE + 0)
11#define IRQ_EXT_1 (IRQ_EXT_BASE + 1)
12#define IRQ_EXT_2 (IRQ_EXT_BASE + 2)
13#define IRQ_EXT_3 (IRQ_EXT_BASE + 3)
14
15#endif /* ! BCM63XX_IRQ_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
new file mode 100644
index 000000000000..ed4ccec87dd4
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -0,0 +1,773 @@
1#ifndef BCM63XX_REGS_H_
2#define BCM63XX_REGS_H_
3
4/*************************************************************************
5 * _REG relative to RSET_PERF
6 *************************************************************************/
7
8/* Chip Identifier / Revision register */
9#define PERF_REV_REG 0x0
10#define REV_CHIPID_SHIFT 16
11#define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
12#define REV_REVID_SHIFT 0
13#define REV_REVID_MASK (0xffff << REV_REVID_SHIFT)
14
15/* Clock Control register */
16#define PERF_CKCTL_REG 0x4
17
18#define CKCTL_6338_ADSLPHY_EN (1 << 0)
19#define CKCTL_6338_MPI_EN (1 << 1)
20#define CKCTL_6338_DRAM_EN (1 << 2)
21#define CKCTL_6338_ENET_EN (1 << 4)
22#define CKCTL_6338_USBS_EN (1 << 4)
23#define CKCTL_6338_SAR_EN (1 << 5)
24#define CKCTL_6338_SPI_EN (1 << 9)
25
26#define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \
27 CKCTL_6338_MPI_EN | \
28 CKCTL_6338_ENET_EN | \
29 CKCTL_6338_SAR_EN | \
30 CKCTL_6338_SPI_EN)
31
32#define CKCTL_6345_CPU_EN (1 << 0)
33#define CKCTL_6345_BUS_EN (1 << 1)
34#define CKCTL_6345_EBI_EN (1 << 2)
35#define CKCTL_6345_UART_EN (1 << 3)
36#define CKCTL_6345_ADSLPHY_EN (1 << 4)
37#define CKCTL_6345_ENET_EN (1 << 7)
38#define CKCTL_6345_USBH_EN (1 << 8)
39
40#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
41 CKCTL_6345_USBH_EN | \
42 CKCTL_6345_ADSLPHY_EN)
43
44#define CKCTL_6348_ADSLPHY_EN (1 << 0)
45#define CKCTL_6348_MPI_EN (1 << 1)
46#define CKCTL_6348_SDRAM_EN (1 << 2)
47#define CKCTL_6348_M2M_EN (1 << 3)
48#define CKCTL_6348_ENET_EN (1 << 4)
49#define CKCTL_6348_SAR_EN (1 << 5)
50#define CKCTL_6348_USBS_EN (1 << 6)
51#define CKCTL_6348_USBH_EN (1 << 8)
52#define CKCTL_6348_SPI_EN (1 << 9)
53
54#define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \
55 CKCTL_6348_M2M_EN | \
56 CKCTL_6348_ENET_EN | \
57 CKCTL_6348_SAR_EN | \
58 CKCTL_6348_USBS_EN | \
59 CKCTL_6348_USBH_EN | \
60 CKCTL_6348_SPI_EN)
61
62#define CKCTL_6358_ENET_EN (1 << 4)
63#define CKCTL_6358_ADSLPHY_EN (1 << 5)
64#define CKCTL_6358_PCM_EN (1 << 8)
65#define CKCTL_6358_SPI_EN (1 << 9)
66#define CKCTL_6358_USBS_EN (1 << 10)
67#define CKCTL_6358_SAR_EN (1 << 11)
68#define CKCTL_6358_EMUSB_EN (1 << 17)
69#define CKCTL_6358_ENET0_EN (1 << 18)
70#define CKCTL_6358_ENET1_EN (1 << 19)
71#define CKCTL_6358_USBSU_EN (1 << 20)
72#define CKCTL_6358_EPHY_EN (1 << 21)
73
74#define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \
75 CKCTL_6358_ADSLPHY_EN | \
76 CKCTL_6358_PCM_EN | \
77 CKCTL_6358_SPI_EN | \
78 CKCTL_6358_USBS_EN | \
79 CKCTL_6358_SAR_EN | \
80 CKCTL_6358_EMUSB_EN | \
81 CKCTL_6358_ENET0_EN | \
82 CKCTL_6358_ENET1_EN | \
83 CKCTL_6358_USBSU_EN | \
84 CKCTL_6358_EPHY_EN)
85
86/* System PLL Control register */
87#define PERF_SYS_PLL_CTL_REG 0x8
88#define SYS_PLL_SOFT_RESET 0x1
89
90/* Interrupt Mask register */
91#define PERF_IRQMASK_REG 0xc
92#define PERF_IRQSTAT_REG 0x10
93
94/* Interrupt Status register */
95#define PERF_IRQSTAT_REG 0x10
96
97/* External Interrupt Configuration register */
98#define PERF_EXTIRQ_CFG_REG 0x14
99#define EXTIRQ_CFG_SENSE(x) (1 << (x))
100#define EXTIRQ_CFG_STAT(x) (1 << (x + 5))
101#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10))
102#define EXTIRQ_CFG_MASK(x) (1 << (x + 15))
103#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20))
104#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25))
105
106#define EXTIRQ_CFG_CLEAR_ALL (0xf << 10)
107#define EXTIRQ_CFG_MASK_ALL (0xf << 15)
108
109/* Soft Reset register */
110#define PERF_SOFTRESET_REG 0x28
111
112#define SOFTRESET_6338_SPI_MASK (1 << 0)
113#define SOFTRESET_6338_ENET_MASK (1 << 2)
114#define SOFTRESET_6338_USBH_MASK (1 << 3)
115#define SOFTRESET_6338_USBS_MASK (1 << 4)
116#define SOFTRESET_6338_ADSL_MASK (1 << 5)
117#define SOFTRESET_6338_DMAMEM_MASK (1 << 6)
118#define SOFTRESET_6338_SAR_MASK (1 << 7)
119#define SOFTRESET_6338_ACLC_MASK (1 << 8)
120#define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
121#define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \
122 SOFTRESET_6338_ENET_MASK | \
123 SOFTRESET_6338_USBH_MASK | \
124 SOFTRESET_6338_USBS_MASK | \
125 SOFTRESET_6338_ADSL_MASK | \
126 SOFTRESET_6338_DMAMEM_MASK | \
127 SOFTRESET_6338_SAR_MASK | \
128 SOFTRESET_6338_ACLC_MASK | \
129 SOFTRESET_6338_ADSLMIPSPLL_MASK)
130
131#define SOFTRESET_6348_SPI_MASK (1 << 0)
132#define SOFTRESET_6348_ENET_MASK (1 << 2)
133#define SOFTRESET_6348_USBH_MASK (1 << 3)
134#define SOFTRESET_6348_USBS_MASK (1 << 4)
135#define SOFTRESET_6348_ADSL_MASK (1 << 5)
136#define SOFTRESET_6348_DMAMEM_MASK (1 << 6)
137#define SOFTRESET_6348_SAR_MASK (1 << 7)
138#define SOFTRESET_6348_ACLC_MASK (1 << 8)
139#define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
140
141#define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \
142 SOFTRESET_6348_ENET_MASK | \
143 SOFTRESET_6348_USBH_MASK | \
144 SOFTRESET_6348_USBS_MASK | \
145 SOFTRESET_6348_ADSL_MASK | \
146 SOFTRESET_6348_DMAMEM_MASK | \
147 SOFTRESET_6348_SAR_MASK | \
148 SOFTRESET_6348_ACLC_MASK | \
149 SOFTRESET_6348_ADSLMIPSPLL_MASK)
150
151/* MIPS PLL control register */
152#define PERF_MIPSPLLCTL_REG 0x34
153#define MIPSPLLCTL_N1_SHIFT 20
154#define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT)
155#define MIPSPLLCTL_N2_SHIFT 15
156#define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT)
157#define MIPSPLLCTL_M1REF_SHIFT 12
158#define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT)
159#define MIPSPLLCTL_M2REF_SHIFT 9
160#define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT)
161#define MIPSPLLCTL_M1CPU_SHIFT 6
162#define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
163#define MIPSPLLCTL_M1BUS_SHIFT 3
164#define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
165#define MIPSPLLCTL_M2BUS_SHIFT 0
166#define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
167
168/* ADSL PHY PLL Control register */
169#define PERF_ADSLPLLCTL_REG 0x38
170#define ADSLPLLCTL_N1_SHIFT 20
171#define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT)
172#define ADSLPLLCTL_N2_SHIFT 15
173#define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT)
174#define ADSLPLLCTL_M1REF_SHIFT 12
175#define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT)
176#define ADSLPLLCTL_M2REF_SHIFT 9
177#define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT)
178#define ADSLPLLCTL_M1CPU_SHIFT 6
179#define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
180#define ADSLPLLCTL_M1BUS_SHIFT 3
181#define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
182#define ADSLPLLCTL_M2BUS_SHIFT 0
183#define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
184
185#define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus) \
186 (((n1) << ADSLPLLCTL_N1_SHIFT) | \
187 ((n2) << ADSLPLLCTL_N2_SHIFT) | \
188 ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \
189 ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \
190 ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \
191 ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \
192 ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
193
194
195/*************************************************************************
196 * _REG relative to RSET_TIMER
197 *************************************************************************/
198
199#define BCM63XX_TIMER_COUNT 4
200#define TIMER_T0_ID 0
201#define TIMER_T1_ID 1
202#define TIMER_T2_ID 2
203#define TIMER_WDT_ID 3
204
205/* Timer irqstat register */
206#define TIMER_IRQSTAT_REG 0
207#define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x))
208#define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0)
209#define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1)
210#define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2)
211#define TIMER_IRQSTAT_WDT_CAUSE (1 << 3)
212#define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8))
213#define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8)
214#define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
215#define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
216
217/* Timer control register */
218#define TIMER_CTLx_REG(x) (0x4 + (x * 4))
219#define TIMER_CTL0_REG 0x4
220#define TIMER_CTL1_REG 0x8
221#define TIMER_CTL2_REG 0xC
222#define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff)
223#define TIMER_CTL_MONOTONIC_MASK (1 << 30)
224#define TIMER_CTL_ENABLE_MASK (1 << 31)
225
226
227/*************************************************************************
228 * _REG relative to RSET_WDT
229 *************************************************************************/
230
231/* Watchdog default count register */
232#define WDT_DEFVAL_REG 0x0
233
234/* Watchdog control register */
235#define WDT_CTL_REG 0x4
236
237/* Watchdog control register constants */
238#define WDT_START_1 (0xff00)
239#define WDT_START_2 (0x00ff)
240#define WDT_STOP_1 (0xee00)
241#define WDT_STOP_2 (0x00ee)
242
243/* Watchdog reset length register */
244#define WDT_RSTLEN_REG 0x8
245
246
247/*************************************************************************
248 * _REG relative to RSET_UARTx
249 *************************************************************************/
250
251/* UART Control Register */
252#define UART_CTL_REG 0x0
253#define UART_CTL_RXTMOUTCNT_SHIFT 0
254#define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
255#define UART_CTL_RSTTXDN_SHIFT 5
256#define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
257#define UART_CTL_RSTRXFIFO_SHIFT 6
258#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
259#define UART_CTL_RSTTXFIFO_SHIFT 7
260#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
261#define UART_CTL_STOPBITS_SHIFT 8
262#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
263#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
264#define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
265#define UART_CTL_BITSPERSYM_SHIFT 12
266#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
267#define UART_CTL_XMITBRK_SHIFT 14
268#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
269#define UART_CTL_RSVD_SHIFT 15
270#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
271#define UART_CTL_RXPAREVEN_SHIFT 16
272#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
273#define UART_CTL_RXPAREN_SHIFT 17
274#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
275#define UART_CTL_TXPAREVEN_SHIFT 18
276#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
277#define UART_CTL_TXPAREN_SHIFT 18
278#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
279#define UART_CTL_LOOPBACK_SHIFT 20
280#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
281#define UART_CTL_RXEN_SHIFT 21
282#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
283#define UART_CTL_TXEN_SHIFT 22
284#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
285#define UART_CTL_BRGEN_SHIFT 23
286#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
287
288/* UART Baudword register */
289#define UART_BAUD_REG 0x4
290
291/* UART Misc Control register */
292#define UART_MCTL_REG 0x8
293#define UART_MCTL_DTR_SHIFT 0
294#define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
295#define UART_MCTL_RTS_SHIFT 1
296#define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
297#define UART_MCTL_RXFIFOTHRESH_SHIFT 8
298#define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
299#define UART_MCTL_TXFIFOTHRESH_SHIFT 12
300#define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
301#define UART_MCTL_RXFIFOFILL_SHIFT 16
302#define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
303#define UART_MCTL_TXFIFOFILL_SHIFT 24
304#define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
305
306/* UART External Input Configuration register */
307#define UART_EXTINP_REG 0xc
308#define UART_EXTINP_RI_SHIFT 0
309#define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
310#define UART_EXTINP_CTS_SHIFT 1
311#define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
312#define UART_EXTINP_DCD_SHIFT 2
313#define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
314#define UART_EXTINP_DSR_SHIFT 3
315#define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
316#define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
317#define UART_EXTINP_IRMASK(x) (1 << (x + 8))
318#define UART_EXTINP_IR_RI 0
319#define UART_EXTINP_IR_CTS 1
320#define UART_EXTINP_IR_DCD 2
321#define UART_EXTINP_IR_DSR 3
322#define UART_EXTINP_RI_NOSENSE_SHIFT 16
323#define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
324#define UART_EXTINP_CTS_NOSENSE_SHIFT 17
325#define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
326#define UART_EXTINP_DCD_NOSENSE_SHIFT 18
327#define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
328#define UART_EXTINP_DSR_NOSENSE_SHIFT 19
329#define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
330
331/* UART Interrupt register */
332#define UART_IR_REG 0x10
333#define UART_IR_MASK(x) (1 << (x + 16))
334#define UART_IR_STAT(x) (1 << (x))
335#define UART_IR_EXTIP 0
336#define UART_IR_TXUNDER 1
337#define UART_IR_TXOVER 2
338#define UART_IR_TXTRESH 3
339#define UART_IR_TXRDLATCH 4
340#define UART_IR_TXEMPTY 5
341#define UART_IR_RXUNDER 6
342#define UART_IR_RXOVER 7
343#define UART_IR_RXTIMEOUT 8
344#define UART_IR_RXFULL 9
345#define UART_IR_RXTHRESH 10
346#define UART_IR_RXNOTEMPTY 11
347#define UART_IR_RXFRAMEERR 12
348#define UART_IR_RXPARERR 13
349#define UART_IR_RXBRK 14
350#define UART_IR_TXDONE 15
351
352/* UART Fifo register */
353#define UART_FIFO_REG 0x14
354#define UART_FIFO_VALID_SHIFT 0
355#define UART_FIFO_VALID_MASK 0xff
356#define UART_FIFO_FRAMEERR_SHIFT 8
357#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
358#define UART_FIFO_PARERR_SHIFT 9
359#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
360#define UART_FIFO_BRKDET_SHIFT 10
361#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
362#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
363 UART_FIFO_PARERR_MASK | \
364 UART_FIFO_BRKDET_MASK)
365
366
367/*************************************************************************
368 * _REG relative to RSET_GPIO
369 *************************************************************************/
370
371/* GPIO registers */
372#define GPIO_CTL_HI_REG 0x0
373#define GPIO_CTL_LO_REG 0x4
374#define GPIO_DATA_HI_REG 0x8
375#define GPIO_DATA_LO_REG 0xC
376
377/* GPIO mux registers and constants */
378#define GPIO_MODE_REG 0x18
379
380#define GPIO_MODE_6348_G4_DIAG 0x00090000
381#define GPIO_MODE_6348_G4_UTOPIA 0x00080000
382#define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000
383#define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000
384#define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000
385#define GPIO_MODE_6348_G3_DIAG 0x00009000
386#define GPIO_MODE_6348_G3_UTOPIA 0x00008000
387#define GPIO_MODE_6348_G3_EXT_MII 0x00007000
388#define GPIO_MODE_6348_G2_DIAG 0x00000900
389#define GPIO_MODE_6348_G2_PCI 0x00000500
390#define GPIO_MODE_6348_G1_DIAG 0x00000090
391#define GPIO_MODE_6348_G1_UTOPIA 0x00000080
392#define GPIO_MODE_6348_G1_SPI_UART 0x00000060
393#define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060
394#define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040
395#define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020
396#define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010
397#define GPIO_MODE_6348_G0_DIAG 0x00000009
398#define GPIO_MODE_6348_G0_EXT_MII 0x00000007
399
400#define GPIO_MODE_6358_EXTRACS (1 << 5)
401#define GPIO_MODE_6358_UART1 (1 << 6)
402#define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
403#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
404#define GPIO_MODE_6358_UTOPIA (1 << 12)
405
406
407/*************************************************************************
408 * _REG relative to RSET_ENET
409 *************************************************************************/
410
411/* Receiver Configuration register */
412#define ENET_RXCFG_REG 0x0
413#define ENET_RXCFG_ALLMCAST_SHIFT 1
414#define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT)
415#define ENET_RXCFG_PROMISC_SHIFT 3
416#define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT)
417#define ENET_RXCFG_LOOPBACK_SHIFT 4
418#define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT)
419#define ENET_RXCFG_ENFLOW_SHIFT 5
420#define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT)
421
422/* Receive Maximum Length register */
423#define ENET_RXMAXLEN_REG 0x4
424#define ENET_RXMAXLEN_SHIFT 0
425#define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT)
426
427/* Transmit Maximum Length register */
428#define ENET_TXMAXLEN_REG 0x8
429#define ENET_TXMAXLEN_SHIFT 0
430#define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT)
431
432/* MII Status/Control register */
433#define ENET_MIISC_REG 0x10
434#define ENET_MIISC_MDCFREQDIV_SHIFT 0
435#define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
436#define ENET_MIISC_PREAMBLEEN_SHIFT 7
437#define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
438
439/* MII Data register */
440#define ENET_MIIDATA_REG 0x14
441#define ENET_MIIDATA_DATA_SHIFT 0
442#define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT)
443#define ENET_MIIDATA_TA_SHIFT 16
444#define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT)
445#define ENET_MIIDATA_REG_SHIFT 18
446#define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT)
447#define ENET_MIIDATA_PHYID_SHIFT 23
448#define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT)
449#define ENET_MIIDATA_OP_READ_MASK (0x6 << 28)
450#define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28)
451
452/* Ethernet Interrupt Mask register */
453#define ENET_IRMASK_REG 0x18
454
455/* Ethernet Interrupt register */
456#define ENET_IR_REG 0x1c
457#define ENET_IR_MII (1 << 0)
458#define ENET_IR_MIB (1 << 1)
459#define ENET_IR_FLOWC (1 << 2)
460
461/* Ethernet Control register */
462#define ENET_CTL_REG 0x2c
463#define ENET_CTL_ENABLE_SHIFT 0
464#define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT)
465#define ENET_CTL_DISABLE_SHIFT 1
466#define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT)
467#define ENET_CTL_SRESET_SHIFT 2
468#define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT)
469#define ENET_CTL_EPHYSEL_SHIFT 3
470#define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT)
471
472/* Transmit Control register */
473#define ENET_TXCTL_REG 0x30
474#define ENET_TXCTL_FD_SHIFT 0
475#define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT)
476
477/* Transmit Watermask register */
478#define ENET_TXWMARK_REG 0x34
479#define ENET_TXWMARK_WM_SHIFT 0
480#define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT)
481
482/* MIB Control register */
483#define ENET_MIBCTL_REG 0x38
484#define ENET_MIBCTL_RDCLEAR_SHIFT 0
485#define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
486
487/* Perfect Match Data Low register */
488#define ENET_PML_REG(x) (0x58 + (x) * 8)
489#define ENET_PMH_REG(x) (0x5c + (x) * 8)
490#define ENET_PMH_DATAVALID_SHIFT 16
491#define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT)
492
493/* MIB register */
494#define ENET_MIB_REG(x) (0x200 + (x) * 4)
495#define ENET_MIB_REG_COUNT 55
496
497
498/*************************************************************************
499 * _REG relative to RSET_ENETDMA
500 *************************************************************************/
501
502/* Controller Configuration Register */
503#define ENETDMA_CFG_REG (0x0)
504#define ENETDMA_CFG_EN_SHIFT 0
505#define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT)
506#define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
507
508/* Flow Control Descriptor Low Threshold register */
509#define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6)
510
511/* Flow Control Descriptor High Threshold register */
512#define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6)
513
514/* Flow Control Descriptor Buffer Alloca Threshold register */
515#define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6)
516#define ENETDMA_BUFALLOC_FORCE_SHIFT 31
517#define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
518
519/* Channel Configuration register */
520#define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
521#define ENETDMA_CHANCFG_EN_SHIFT 0
522#define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
523#define ENETDMA_CHANCFG_PKTHALT_SHIFT 1
524#define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
525
526/* Interrupt Control/Status register */
527#define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10)
528#define ENETDMA_IR_BUFDONE_MASK (1 << 0)
529#define ENETDMA_IR_PKTDONE_MASK (1 << 1)
530#define ENETDMA_IR_NOTOWNER_MASK (1 << 2)
531
532/* Interrupt Mask register */
533#define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10)
534
535/* Maximum Burst Length */
536#define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10)
537
538/* Ring Start Address register */
539#define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10)
540
541/* State Ram Word 2 */
542#define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10)
543
544/* State Ram Word 3 */
545#define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10)
546
547/* State Ram Word 4 */
548#define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
549
550
551/*************************************************************************
552 * _REG relative to RSET_OHCI_PRIV
553 *************************************************************************/
554
555#define OHCI_PRIV_REG 0x0
556#define OHCI_PRIV_PORT1_HOST_SHIFT 0
557#define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
558#define OHCI_PRIV_REG_SWAP_SHIFT 3
559#define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT)
560
561
562/*************************************************************************
563 * _REG relative to RSET_USBH_PRIV
564 *************************************************************************/
565
566#define USBH_PRIV_SWAP_REG 0x0
567#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
568#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
569#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
570#define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
571#define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1
572#define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
573#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
574#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
575
576#define USBH_PRIV_TEST_REG 0x24
577
578
579/*************************************************************************
580 * _REG relative to RSET_MPI
581 *************************************************************************/
582
583/* well known (hard wired) chip select */
584#define MPI_CS_PCMCIA_COMMON 4
585#define MPI_CS_PCMCIA_ATTR 5
586#define MPI_CS_PCMCIA_IO 6
587
588/* Chip select base register */
589#define MPI_CSBASE_REG(x) (0x0 + (x) * 8)
590#define MPI_CSBASE_BASE_SHIFT 13
591#define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT)
592#define MPI_CSBASE_SIZE_SHIFT 0
593#define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT)
594
595#define MPI_CSBASE_SIZE_8K 0
596#define MPI_CSBASE_SIZE_16K 1
597#define MPI_CSBASE_SIZE_32K 2
598#define MPI_CSBASE_SIZE_64K 3
599#define MPI_CSBASE_SIZE_128K 4
600#define MPI_CSBASE_SIZE_256K 5
601#define MPI_CSBASE_SIZE_512K 6
602#define MPI_CSBASE_SIZE_1M 7
603#define MPI_CSBASE_SIZE_2M 8
604#define MPI_CSBASE_SIZE_4M 9
605#define MPI_CSBASE_SIZE_8M 10
606#define MPI_CSBASE_SIZE_16M 11
607#define MPI_CSBASE_SIZE_32M 12
608#define MPI_CSBASE_SIZE_64M 13
609#define MPI_CSBASE_SIZE_128M 14
610#define MPI_CSBASE_SIZE_256M 15
611
612/* Chip select control register */
613#define MPI_CSCTL_REG(x) (0x4 + (x) * 8)
614#define MPI_CSCTL_ENABLE_MASK (1 << 0)
615#define MPI_CSCTL_WAIT_SHIFT 1
616#define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT)
617#define MPI_CSCTL_DATA16_MASK (1 << 4)
618#define MPI_CSCTL_SYNCMODE_MASK (1 << 7)
619#define MPI_CSCTL_TSIZE_MASK (1 << 8)
620#define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10)
621#define MPI_CSCTL_SETUP_SHIFT 16
622#define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT)
623#define MPI_CSCTL_HOLD_SHIFT 20
624#define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT)
625
626/* PCI registers */
627#define MPI_SP0_RANGE_REG 0x100
628#define MPI_SP0_REMAP_REG 0x104
629#define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
630#define MPI_SP1_RANGE_REG 0x10C
631#define MPI_SP1_REMAP_REG 0x110
632#define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
633
634#define MPI_L2PCFG_REG 0x11C
635#define MPI_L2PCFG_CFG_TYPE_SHIFT 0
636#define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
637#define MPI_L2PCFG_REG_SHIFT 2
638#define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
639#define MPI_L2PCFG_FUNC_SHIFT 8
640#define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
641#define MPI_L2PCFG_DEVNUM_SHIFT 11
642#define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
643#define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
644#define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
645
646#define MPI_L2PMEMRANGE1_REG 0x120
647#define MPI_L2PMEMBASE1_REG 0x124
648#define MPI_L2PMEMREMAP1_REG 0x128
649#define MPI_L2PMEMRANGE2_REG 0x12C
650#define MPI_L2PMEMBASE2_REG 0x130
651#define MPI_L2PMEMREMAP2_REG 0x134
652#define MPI_L2PIORANGE_REG 0x138
653#define MPI_L2PIOBASE_REG 0x13C
654#define MPI_L2PIOREMAP_REG 0x140
655#define MPI_L2P_BASE_MASK (0xffff8000)
656#define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
657#define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
658
659#define MPI_PCIMODESEL_REG 0x144
660#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
661#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
662#define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
663#define MPI_PCIMODESEL_PREFETCH_SHIFT 4
664#define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
665
666#define MPI_LOCBUSCTL_REG 0x14C
667#define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
668#define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
669
670#define MPI_LOCINT_REG 0x150
671#define MPI_LOCINT_MASK(x) (1 << (x + 16))
672#define MPI_LOCINT_STAT(x) (1 << (x))
673#define MPI_LOCINT_DIR_FAILED 6
674#define MPI_LOCINT_EXT_PCI_INT 7
675#define MPI_LOCINT_SERR 8
676#define MPI_LOCINT_CSERR 9
677
678#define MPI_PCICFGCTL_REG 0x178
679#define MPI_PCICFGCTL_CFGADDR_SHIFT 2
680#define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
681#define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
682
683#define MPI_PCICFGDATA_REG 0x17C
684
685/* PCI host bridge custom register */
686#define BCMPCI_REG_TIMERS 0x40
687#define REG_TIMER_TRDY_SHIFT 0
688#define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
689#define REG_TIMER_RETRY_SHIFT 8
690#define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
691
692
693/*************************************************************************
694 * _REG relative to RSET_PCMCIA
695 *************************************************************************/
696
697#define PCMCIA_C1_REG 0x0
698#define PCMCIA_C1_CD1_MASK (1 << 0)
699#define PCMCIA_C1_CD2_MASK (1 << 1)
700#define PCMCIA_C1_VS1_MASK (1 << 2)
701#define PCMCIA_C1_VS2_MASK (1 << 3)
702#define PCMCIA_C1_VS1OE_MASK (1 << 6)
703#define PCMCIA_C1_VS2OE_MASK (1 << 7)
704#define PCMCIA_C1_CBIDSEL_SHIFT (8)
705#define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
706#define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
707#define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
708#define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
709#define PCMCIA_C1_RESET_MASK (1 << 18)
710
711#define PCMCIA_C2_REG 0x8
712#define PCMCIA_C2_DATA16_MASK (1 << 0)
713#define PCMCIA_C2_BYTESWAP_MASK (1 << 1)
714#define PCMCIA_C2_RWCOUNT_SHIFT 2
715#define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
716#define PCMCIA_C2_INACTIVE_SHIFT 8
717#define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
718#define PCMCIA_C2_SETUP_SHIFT 16
719#define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT)
720#define PCMCIA_C2_HOLD_SHIFT 24
721#define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT)
722
723
724/*************************************************************************
725 * _REG relative to RSET_SDRAM
726 *************************************************************************/
727
728#define SDRAM_CFG_REG 0x0
729#define SDRAM_CFG_ROW_SHIFT 4
730#define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
731#define SDRAM_CFG_COL_SHIFT 6
732#define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
733#define SDRAM_CFG_32B_SHIFT 10
734#define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
735#define SDRAM_CFG_BANK_SHIFT 13
736#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
737
738#define SDRAM_PRIO_REG 0x2C
739#define SDRAM_PRIO_MIPS_SHIFT 29
740#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
741#define SDRAM_PRIO_ADSL_SHIFT 30
742#define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT)
743#define SDRAM_PRIO_EN_SHIFT 31
744#define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT)
745
746
747/*************************************************************************
748 * _REG relative to RSET_MEMC
749 *************************************************************************/
750
751#define MEMC_CFG_REG 0x4
752#define MEMC_CFG_32B_SHIFT 1
753#define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
754#define MEMC_CFG_COL_SHIFT 3
755#define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
756#define MEMC_CFG_ROW_SHIFT 6
757#define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
758
759
760/*************************************************************************
761 * _REG relative to RSET_DDR
762 *************************************************************************/
763
764#define DDR_DMIPSPLLCFG_REG 0x18
765#define DMIPSPLLCFG_M1_SHIFT 0
766#define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
767#define DMIPSPLLCFG_N1_SHIFT 23
768#define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT)
769#define DMIPSPLLCFG_N2_SHIFT 29
770#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
771
772#endif /* BCM63XX_REGS_H_ */
773
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h
new file mode 100644
index 000000000000..c0fce833c9ed
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h
@@ -0,0 +1,11 @@
1#ifndef BCM63XX_TIMER_H_
2#define BCM63XX_TIMER_H_
3
4int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data);
5void bcm63xx_timer_unregister(int id);
6int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us);
7int bcm63xx_timer_enable(int id);
8int bcm63xx_timer_disable(int id);
9unsigned int bcm63xx_timer_countdown(unsigned int countdown_us);
10
11#endif /* !BCM63XX_TIMER_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
new file mode 100644
index 000000000000..6479090a4106
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -0,0 +1,60 @@
1#ifndef BOARD_BCM963XX_H_
2#define BOARD_BCM963XX_H_
3
4#include <linux/types.h>
5#include <linux/gpio.h>
6#include <linux/leds.h>
7#include <bcm63xx_dev_enet.h>
8#include <bcm63xx_dev_dsp.h>
9
10/*
11 * flash mapping
12 */
13#define BCM963XX_CFE_VERSION_OFFSET 0x570
14#define BCM963XX_NVRAM_OFFSET 0x580
15
16/*
17 * nvram structure
18 */
19struct bcm963xx_nvram {
20 u32 version;
21 u8 reserved1[256];
22 u8 name[16];
23 u32 main_tp_number;
24 u32 psi_size;
25 u32 mac_addr_count;
26 u8 mac_addr_base[6];
27 u8 reserved2[2];
28 u32 checksum_old;
29 u8 reserved3[720];
30 u32 checksum_high;
31};
32
33/*
34 * board definition
35 */
36struct board_info {
37 u8 name[16];
38 unsigned int expected_cpu_id;
39
40 /* enabled feature/device */
41 unsigned int has_enet0:1;
42 unsigned int has_enet1:1;
43 unsigned int has_pci:1;
44 unsigned int has_pccard:1;
45 unsigned int has_ohci0:1;
46 unsigned int has_ehci0:1;
47 unsigned int has_dsp:1;
48
49 /* ethernet config */
50 struct bcm63xx_enet_platform_data enet0;
51 struct bcm63xx_enet_platform_data enet1;
52
53 /* DSP config */
54 struct bcm63xx_dsp_platform_data dsp;
55
56 /* GPIO LEDs */
57 struct gpio_led leds[5];
58};
59
60#endif /* ! BOARD_BCM963XX_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
new file mode 100644
index 000000000000..71742bac940d
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
@@ -0,0 +1,51 @@
1#ifndef __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
2#define __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
3
4#include <bcm63xx_cpu.h>
5
6#define cpu_has_tlb 1
7#define cpu_has_4kex 1
8#define cpu_has_4k_cache 1
9#define cpu_has_fpu 0
10#define cpu_has_32fpr 0
11#define cpu_has_counter 1
12#define cpu_has_watch 0
13#define cpu_has_divec 1
14#define cpu_has_vce 0
15#define cpu_has_cache_cdex_p 0
16#define cpu_has_cache_cdex_s 0
17#define cpu_has_prefetch 1
18#define cpu_has_mcheck 1
19#define cpu_has_ejtag 1
20#define cpu_has_llsc 1
21#define cpu_has_mips16 0
22#define cpu_has_mdmx 0
23#define cpu_has_mips3d 0
24#define cpu_has_smartmips 0
25#define cpu_has_vtag_icache 0
26
27#if !defined(BCMCPU_RUNTIME_DETECT) && (defined(CONFIG_BCMCPU_IS_6348) || defined(CONFIG_CPU_IS_6338) || defined(CONFIG_CPU_IS_BCM6345))
28#define cpu_has_dc_aliases 0
29#endif
30
31#define cpu_has_ic_fills_f_dc 0
32#define cpu_has_pindexed_dcache 0
33
34#define cpu_has_mips32r1 1
35#define cpu_has_mips32r2 0
36#define cpu_has_mips64r1 0
37#define cpu_has_mips64r2 0
38
39#define cpu_has_dsp 0
40#define cpu_has_mipsmt 0
41#define cpu_has_userlocal 0
42
43#define cpu_has_nofpuex 0
44#define cpu_has_64bits 0
45#define cpu_has_64bit_zero_reg 0
46
47#define cpu_dcache_line_size() 16
48#define cpu_icache_line_size() 16
49#define cpu_scache_line_size() 0
50
51#endif /* __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/gpio.h b/arch/mips/include/asm/mach-bcm63xx/gpio.h
new file mode 100644
index 000000000000..7cda8c0a3979
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/gpio.h
@@ -0,0 +1,15 @@
1#ifndef __ASM_MIPS_MACH_BCM63XX_GPIO_H
2#define __ASM_MIPS_MACH_BCM63XX_GPIO_H
3
4#include <bcm63xx_gpio.h>
5
6#define gpio_to_irq(gpio) NULL
7
8#define gpio_get_value __gpio_get_value
9#define gpio_set_value __gpio_set_value
10
11#define gpio_cansleep __gpio_cansleep
12
13#include <asm-generic/gpio.h>
14
15#endif /* __ASM_MIPS_MACH_BCM63XX_GPIO_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/war.h b/arch/mips/include/asm/mach-bcm63xx/war.h
new file mode 100644
index 000000000000..8e3f3fdf3209
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_BCM63XX_WAR_H
9#define __ASM_MIPS_MACH_BCM63XX_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_BCM63XX_WAR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-15 05:25:50 -0400