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authorMaxime Bizon <mbizon@freebox.fr>2011-11-04 14:09:34 -0400
committerRalf Baechle <ralf@linux-mips.org>2011-12-07 17:03:04 -0500
commit6224892c819e96898534c107c72b80a1a8e75abf (patch)
tree4f9f2bc957b221f7dd6f6daea7d993c78813b9ad /arch/mips/include/asm/mach-bcm63xx
parent71a43927b3bfe1a42cbf7bb174b170f06fa00a1a (diff)
MIPS: BCM63XX: Add external irq support for non 6348 CPUs.
Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2899/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-bcm63xx')
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h31
1 files changed, 22 insertions, 9 deletions
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 25676cdeb30f..2b3a2d6bdb03 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -100,16 +100,29 @@
100#define PERF_IRQSTAT_6358_REG 0x10 100#define PERF_IRQSTAT_6358_REG 0x10
101 101
102/* External Interrupt Configuration register */ 102/* External Interrupt Configuration register */
103#define PERF_EXTIRQ_CFG_REG 0x14 103#define PERF_EXTIRQ_CFG_REG_6338 0x14
104#define PERF_EXTIRQ_CFG_REG_6348 0x14
105#define PERF_EXTIRQ_CFG_REG_6358 0x14
106
107/* for 6348 only */
108#define EXTIRQ_CFG_SENSE_6348(x) (1 << (x))
109#define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5))
110#define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10))
111#define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15))
112#define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20))
113#define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25))
114#define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10)
115#define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15)
116
117/* for all others */
104#define EXTIRQ_CFG_SENSE(x) (1 << (x)) 118#define EXTIRQ_CFG_SENSE(x) (1 << (x))
105#define EXTIRQ_CFG_STAT(x) (1 << (x + 5)) 119#define EXTIRQ_CFG_STAT(x) (1 << (x + 4))
106#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10)) 120#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8))
107#define EXTIRQ_CFG_MASK(x) (1 << (x + 15)) 121#define EXTIRQ_CFG_MASK(x) (1 << (x + 12))
108#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20)) 122#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16))
109#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25)) 123#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20))
110 124#define EXTIRQ_CFG_CLEAR_ALL (0xf << 8)
111#define EXTIRQ_CFG_CLEAR_ALL (0xf << 10) 125#define EXTIRQ_CFG_MASK_ALL (0xf << 12)
112#define EXTIRQ_CFG_MASK_ALL (0xf << 15)
113 126
114/* Soft Reset register */ 127/* Soft Reset register */
115#define PERF_SOFTRESET_REG 0x28 128#define PERF_SOFTRESET_REG 0x28