MIPS: BCM63xx: Append irq line to irq_{stat,mask}*

The SMP capable irq controllers have two interrupt output pins which are
controlled through separate registers, so make the variables arrays.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: John Crispin <blogic@openwrt.org>
Cc: Maxime Bizon <mbizon@freebox.fr>
Cc: Florian Fainelli <florian@openwrt.org>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Gregory Fong <gregory.0xf0@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7318/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 8 insertions, 8 deletions

diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index ab427f8814e6..4794067cb5a7 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -215,23 +215,23 @@
 
 /* Interrupt Mask register */
 #define PERF_IRQMASK_3368_REG           0xc
-#define PERF_IRQMASK_6328_REG           0x20
+#define PERF_IRQMASK_6328_REG(x)        (0x20 + (x) * 0x10)
 #define PERF_IRQMASK_6338_REG           0xc
 #define PERF_IRQMASK_6345_REG           0xc
 #define PERF_IRQMASK_6348_REG           0xc
-#define PERF_IRQMASK_6358_REG           0xc
-#define PERF_IRQMASK_6362_REG           0x20
-#define PERF_IRQMASK_6368_REG           0x20
+#define PERF_IRQMASK_6358_REG(x)        (0xc + (x) * 0x2c)
+#define PERF_IRQMASK_6362_REG(x)        (0x20 + (x) * 0x10)
+#define PERF_IRQMASK_6368_REG(x)        (0x20 + (x) * 0x10)
 
 /* Interrupt Status register */
 #define PERF_IRQSTAT_3368_REG           0x10
-#define PERF_IRQSTAT_6328_REG           0x28
+#define PERF_IRQSTAT_6328_REG(x)        (0x28 + (x) * 0x10)
 #define PERF_IRQSTAT_6338_REG           0x10
 #define PERF_IRQSTAT_6345_REG           0x10
 #define PERF_IRQSTAT_6348_REG           0x10
-#define PERF_IRQSTAT_6358_REG           0x10
-#define PERF_IRQSTAT_6362_REG           0x28
-#define PERF_IRQSTAT_6368_REG           0x28
+#define PERF_IRQSTAT_6358_REG(x)        (0x10 + (x) * 0x2c)
+#define PERF_IRQSTAT_6362_REG(x)        (0x28 + (x) * 0x10)
+#define PERF_IRQSTAT_6368_REG(x)        (0x28 + (x) * 0x10)
 
 /* External Interrupt Configuration register */
 #define PERF_EXTIRQ_CFG_REG_3368        0x14