Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (37 commits)
  MIPS: O32: Provide definition of registers ta0 .. ta3.
  MIPS: perf: Add Octeon support for hardware perf.
  MIPS: perf: Add support for 64-bit perf counters.
  MIPS: perf: Reorganize contents of perf support files.
  MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c
  MIPS: Add accessor macros for 64-bit performance counter registers.
  MIPS: Add probes for more Octeon II CPUs.
  MIPS: Add more CPU identifiers for Octeon II CPUs.
  MIPS: XLR, XLS: Add comment for smp setup
  MIPS: JZ4740: GPIO: Check correct IRQ in demux handler
  MIPS: JZ4740: GPIO: Simplify IRQ demuxer
  MIPS: JZ4740: Use generic irq chip
  MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines
  MIPS: Alchemy: kill au1xxx.h header
  MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines
  MIPS, IDE: Alchem, au1xxx-ide: Remove pb1200/db1200 header dep
  MIPS: Alchemy: Redo PCI as platform driver
  MIPS: Alchemy: more base address cleanup
  MIPS: Alchemy: rewrite USB platform setup.
  MIPS: Alchemy: abstract USB block control register access
  ...

Fix up trivial conflicts in:
	arch/mips/alchemy/devboards/db1x00/platform.c
	drivers/ide/Kconfig
	drivers/mmc/host/au1xmmc.c
	drivers/video/Kconfig
	sound/mips/Kconfig

1 files changed, 56 insertions, 60 deletions

diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 2fdacfe85e23..323ce2d145f2 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -126,66 +126,62 @@ typedef volatile struct au1xxx_ddma_desc {
 #define SW_STATUS_INUSE         (1 << 0)
 
 /* Command 0 device IDs. */
-#ifdef CONFIG_SOC_AU1550
-#define DSCR_CMD0_UART0_TX      0
-#define DSCR_CMD0_UART0_RX      1
-#define DSCR_CMD0_UART3_TX      2
-#define DSCR_CMD0_UART3_RX      3
-#define DSCR_CMD0_DMA_REQ0      4
-#define DSCR_CMD0_DMA_REQ1      5
-#define DSCR_CMD0_DMA_REQ2      6
-#define DSCR_CMD0_DMA_REQ3      7
-#define DSCR_CMD0_USBDEV_RX0    8
-#define DSCR_CMD0_USBDEV_TX0    9
-#define DSCR_CMD0_USBDEV_TX1    10
-#define DSCR_CMD0_USBDEV_TX2    11
-#define DSCR_CMD0_USBDEV_RX3    12
-#define DSCR_CMD0_USBDEV_RX4    13
-#define DSCR_CMD0_PSC0_TX       14
-#define DSCR_CMD0_PSC0_RX       15
-#define DSCR_CMD0_PSC1_TX       16
-#define DSCR_CMD0_PSC1_RX       17
-#define DSCR_CMD0_PSC2_TX       18
-#define DSCR_CMD0_PSC2_RX       19
-#define DSCR_CMD0_PSC3_TX       20
-#define DSCR_CMD0_PSC3_RX       21
-#define DSCR_CMD0_PCI_WRITE     22
-#define DSCR_CMD0_NAND_FLASH    23
-#define DSCR_CMD0_MAC0_RX       24
-#define DSCR_CMD0_MAC0_TX       25
-#define DSCR_CMD0_MAC1_RX       26
-#define DSCR_CMD0_MAC1_TX       27
-#endif /* CONFIG_SOC_AU1550 */
-
-#ifdef CONFIG_SOC_AU1200
-#define DSCR_CMD0_UART0_TX      0
-#define DSCR_CMD0_UART0_RX      1
-#define DSCR_CMD0_UART1_TX      2
-#define DSCR_CMD0_UART1_RX      3
-#define DSCR_CMD0_DMA_REQ0      4
-#define DSCR_CMD0_DMA_REQ1      5
-#define DSCR_CMD0_MAE_BE        6
-#define DSCR_CMD0_MAE_FE        7
-#define DSCR_CMD0_SDMS_TX0      8
-#define DSCR_CMD0_SDMS_RX0      9
-#define DSCR_CMD0_SDMS_TX1      10
-#define DSCR_CMD0_SDMS_RX1      11
-#define DSCR_CMD0_AES_TX        13
-#define DSCR_CMD0_AES_RX        12
-#define DSCR_CMD0_PSC0_TX       14
-#define DSCR_CMD0_PSC0_RX       15
-#define DSCR_CMD0_PSC1_TX       16
-#define DSCR_CMD0_PSC1_RX       17
-#define DSCR_CMD0_CIM_RXA       18
-#define DSCR_CMD0_CIM_RXB       19
-#define DSCR_CMD0_CIM_RXC       20
-#define DSCR_CMD0_MAE_BOTH      21
-#define DSCR_CMD0_LCD           22
-#define DSCR_CMD0_NAND_FLASH    23
-#define DSCR_CMD0_PSC0_SYNC     24
-#define DSCR_CMD0_PSC1_SYNC     25
-#define DSCR_CMD0_CIM_SYNC      26
-#endif /* CONFIG_SOC_AU1200 */
+#define AU1550_DSCR_CMD0_UART0_TX       0
+#define AU1550_DSCR_CMD0_UART0_RX       1
+#define AU1550_DSCR_CMD0_UART3_TX       2
+#define AU1550_DSCR_CMD0_UART3_RX       3
+#define AU1550_DSCR_CMD0_DMA_REQ0       4
+#define AU1550_DSCR_CMD0_DMA_REQ1       5
+#define AU1550_DSCR_CMD0_DMA_REQ2       6
+#define AU1550_DSCR_CMD0_DMA_REQ3       7
+#define AU1550_DSCR_CMD0_USBDEV_RX0     8
+#define AU1550_DSCR_CMD0_USBDEV_TX0     9
+#define AU1550_DSCR_CMD0_USBDEV_TX1     10
+#define AU1550_DSCR_CMD0_USBDEV_TX2     11
+#define AU1550_DSCR_CMD0_USBDEV_RX3     12
+#define AU1550_DSCR_CMD0_USBDEV_RX4     13
+#define AU1550_DSCR_CMD0_PSC0_TX        14
+#define AU1550_DSCR_CMD0_PSC0_RX        15
+#define AU1550_DSCR_CMD0_PSC1_TX        16
+#define AU1550_DSCR_CMD0_PSC1_RX        17
+#define AU1550_DSCR_CMD0_PSC2_TX        18
+#define AU1550_DSCR_CMD0_PSC2_RX        19
+#define AU1550_DSCR_CMD0_PSC3_TX        20
+#define AU1550_DSCR_CMD0_PSC3_RX        21
+#define AU1550_DSCR_CMD0_PCI_WRITE      22
+#define AU1550_DSCR_CMD0_NAND_FLASH     23
+#define AU1550_DSCR_CMD0_MAC0_RX        24
+#define AU1550_DSCR_CMD0_MAC0_TX        25
+#define AU1550_DSCR_CMD0_MAC1_RX        26
+#define AU1550_DSCR_CMD0_MAC1_TX        27
+
+#define AU1200_DSCR_CMD0_UART0_TX       0
+#define AU1200_DSCR_CMD0_UART0_RX       1
+#define AU1200_DSCR_CMD0_UART1_TX       2
+#define AU1200_DSCR_CMD0_UART1_RX       3
+#define AU1200_DSCR_CMD0_DMA_REQ0       4
+#define AU1200_DSCR_CMD0_DMA_REQ1       5
+#define AU1200_DSCR_CMD0_MAE_BE         6
+#define AU1200_DSCR_CMD0_MAE_FE         7
+#define AU1200_DSCR_CMD0_SDMS_TX0       8
+#define AU1200_DSCR_CMD0_SDMS_RX0       9
+#define AU1200_DSCR_CMD0_SDMS_TX1       10
+#define AU1200_DSCR_CMD0_SDMS_RX1       11
+#define AU1200_DSCR_CMD0_AES_TX         13
+#define AU1200_DSCR_CMD0_AES_RX         12
+#define AU1200_DSCR_CMD0_PSC0_TX        14
+#define AU1200_DSCR_CMD0_PSC0_RX        15
+#define AU1200_DSCR_CMD0_PSC1_TX        16
+#define AU1200_DSCR_CMD0_PSC1_RX        17
+#define AU1200_DSCR_CMD0_CIM_RXA        18
+#define AU1200_DSCR_CMD0_CIM_RXB        19
+#define AU1200_DSCR_CMD0_CIM_RXC        20
+#define AU1200_DSCR_CMD0_MAE_BOTH       21
+#define AU1200_DSCR_CMD0_LCD            22
+#define AU1200_DSCR_CMD0_NAND_FLASH     23
+#define AU1200_DSCR_CMD0_PSC0_SYNC      24
+#define AU1200_DSCR_CMD0_PSC1_SYNC      25
+#define AU1200_DSCR_CMD0_CIM_SYNC       26
 
 #define DSCR_CMD0_THROTTLE      30
 #define DSCR_CMD0_ALWAYS        31