diff options
author | Gabor Juhos <juhosg@openwrt.org> | 2013-02-04 05:56:53 -0500 |
---|---|---|
committer | John Crispin <blogic@openwrt.org> | 2013-02-16 19:25:35 -0500 |
commit | ad4ce92e919f7ad5561a2060deb58899de58b40c (patch) | |
tree | afdb8e34ae87d800095b901b21b822b31b7578da /arch/mips/include/asm/mach-ath79 | |
parent | fb167e891d5cc6386840dd092af2d461b38eb802 (diff) |
MIPS: ath79: move global PCI defines into a common header
The constants will be used by a subsequent patch.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4907/
Signed-off-by: John Crispin <blogic@openwrt.org>
Diffstat (limited to 'arch/mips/include/asm/mach-ath79')
-rw-r--r-- | arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 7d44b5d5f609..7c87bfe6e4ff 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h | |||
@@ -41,11 +41,35 @@ | |||
41 | #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) | 41 | #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) |
42 | #define AR71XX_RESET_SIZE 0x100 | 42 | #define AR71XX_RESET_SIZE 0x100 |
43 | 43 | ||
44 | #define AR71XX_PCI_MEM_BASE 0x10000000 | ||
45 | #define AR71XX_PCI_MEM_SIZE 0x07000000 | ||
46 | |||
47 | #define AR71XX_PCI_WIN0_OFFS 0x10000000 | ||
48 | #define AR71XX_PCI_WIN1_OFFS 0x11000000 | ||
49 | #define AR71XX_PCI_WIN2_OFFS 0x12000000 | ||
50 | #define AR71XX_PCI_WIN3_OFFS 0x13000000 | ||
51 | #define AR71XX_PCI_WIN4_OFFS 0x14000000 | ||
52 | #define AR71XX_PCI_WIN5_OFFS 0x15000000 | ||
53 | #define AR71XX_PCI_WIN6_OFFS 0x16000000 | ||
54 | #define AR71XX_PCI_WIN7_OFFS 0x07000000 | ||
55 | |||
56 | #define AR71XX_PCI_CFG_BASE \ | ||
57 | (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) | ||
58 | #define AR71XX_PCI_CFG_SIZE 0x100 | ||
59 | |||
44 | #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) | 60 | #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) |
45 | #define AR7240_USB_CTRL_SIZE 0x100 | 61 | #define AR7240_USB_CTRL_SIZE 0x100 |
46 | #define AR7240_OHCI_BASE 0x1b000000 | 62 | #define AR7240_OHCI_BASE 0x1b000000 |
47 | #define AR7240_OHCI_SIZE 0x1000 | 63 | #define AR7240_OHCI_SIZE 0x1000 |
48 | 64 | ||
65 | #define AR724X_PCI_MEM_BASE 0x10000000 | ||
66 | #define AR724X_PCI_MEM_SIZE 0x04000000 | ||
67 | |||
68 | #define AR724X_PCI_CFG_BASE 0x14000000 | ||
69 | #define AR724X_PCI_CFG_SIZE 0x1000 | ||
70 | #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) | ||
71 | #define AR724X_PCI_CTRL_SIZE 0x100 | ||
72 | |||
49 | #define AR724X_EHCI_BASE 0x1b000000 | 73 | #define AR724X_EHCI_BASE 0x1b000000 |
50 | #define AR724X_EHCI_SIZE 0x1000 | 74 | #define AR724X_EHCI_SIZE 0x1000 |
51 | 75 | ||