MIPS: ath79: add IRQ handling code for the QCA955X SoCs

The IRQ routing in the QCA955x SoCs is slightly
different from the routing implemented in the
already supported SoCs.

Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4955/
Signed-off-by: John Crispin <blogic@openwrt.org>

2 files changed, 37 insertions, 1 deletions

diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index 7b00e12afc1c..8782d8b097a3 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -300,6 +300,7 @@
 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS   0xac
 
 #define QCA955X_RESET_REG_BOOTSTRAP             0xb0
+#define QCA955X_RESET_REG_EXT_INT_STATUS        0xac
 
 #define MISC_INT_ETHSW                  BIT(12)
 #define MISC_INT_TIMER4                 BIT(10)
@@ -398,6 +399,37 @@
          AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
          AR934X_PCIE_WMAC_INT_PCIE_RC3)
 
+#define QCA955X_EXT_INT_WMAC_MISC               BIT(0)
+#define QCA955X_EXT_INT_WMAC_TX                 BIT(1)
+#define QCA955X_EXT_INT_WMAC_RXLP               BIT(2)
+#define QCA955X_EXT_INT_WMAC_RXHP               BIT(3)
+#define QCA955X_EXT_INT_PCIE_RC1                BIT(4)
+#define QCA955X_EXT_INT_PCIE_RC1_INT0           BIT(5)
+#define QCA955X_EXT_INT_PCIE_RC1_INT1           BIT(6)
+#define QCA955X_EXT_INT_PCIE_RC1_INT2           BIT(7)
+#define QCA955X_EXT_INT_PCIE_RC1_INT3           BIT(8)
+#define QCA955X_EXT_INT_PCIE_RC2                BIT(12)
+#define QCA955X_EXT_INT_PCIE_RC2_INT0           BIT(13)
+#define QCA955X_EXT_INT_PCIE_RC2_INT1           BIT(14)
+#define QCA955X_EXT_INT_PCIE_RC2_INT2           BIT(15)
+#define QCA955X_EXT_INT_PCIE_RC2_INT3           BIT(16)
+#define QCA955X_EXT_INT_USB1                    BIT(24)
+#define QCA955X_EXT_INT_USB2                    BIT(28)
+
+#define QCA955X_EXT_INT_WMAC_ALL \
+        (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
+         QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
+
+#define QCA955X_EXT_INT_PCIE_RC1_ALL \
+        (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
+         QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
+         QCA955X_EXT_INT_PCIE_RC1_INT3)
+
+#define QCA955X_EXT_INT_PCIE_RC2_ALL \
+        (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
+         QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
+         QCA955X_EXT_INT_PCIE_RC2_INT3)
+
 #define REV_ID_MAJOR_MASK               0xfff0
 #define REV_ID_MAJOR_AR71XX             0x00a0
 #define REV_ID_MAJOR_AR913X             0x00b0
diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
index 23e2bba42482..5c9ca76a7ebf 100644
--- a/arch/mips/include/asm/mach-ath79/irq.h
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -10,7 +10,7 @@
 #define __ASM_MACH_ATH79_IRQ_H
 
 #define MIPS_CPU_IRQ_BASE       0
-#define NR_IRQS                 48
+#define NR_IRQS                 51
 
 #define ATH79_CPU_IRQ(_x)       (MIPS_CPU_IRQ_BASE + (_x))
 
@@ -26,6 +26,10 @@
 #define ATH79_IP2_IRQ_COUNT     2
 #define ATH79_IP2_IRQ(_x)       (ATH79_IP2_IRQ_BASE + (_x))
 
+#define ATH79_IP3_IRQ_BASE      (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT)
+#define ATH79_IP3_IRQ_COUNT     3
+#define ATH79_IP3_IRQ(_x)       (ATH79_IP3_IRQ_BASE + (_x))
+
 #include_next <irq.h>
 
 #endif /* __ASM_MACH_ATH79_IRQ_H */