diff options
author | Gabor Juhos <juhosg@openwrt.org> | 2011-06-20 15:26:04 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2011-12-07 17:02:45 -0500 |
commit | 04225e1d227c8e68d685936ecf42ac175fec0e54 (patch) | |
tree | e7ecd726ca40a58c1d11bc6753dd7e4c8c72c107 /arch/mips/include/asm/mach-ath79 | |
parent | 0bd3acdf7d559c8289de73c4c711fd2381e6c7ad (diff) |
MIPS: ath79: add AR933X specific clock init
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: Kathy Giori <kgiori@qca.qualcomm.com>
Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
Patchwork: https://patchwork.linux-mips.org/patch/2522/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-ath79')
-rw-r--r-- | arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 22 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-ath79/ath79.h | 6 |
2 files changed, 28 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index 90223f206610..418b7392e8c3 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h | |||
@@ -123,6 +123,24 @@ | |||
123 | #define AR913X_AHB_DIV_SHIFT 19 | 123 | #define AR913X_AHB_DIV_SHIFT 19 |
124 | #define AR913X_AHB_DIV_MASK 0x1 | 124 | #define AR913X_AHB_DIV_MASK 0x1 |
125 | 125 | ||
126 | #define AR933X_PLL_CPU_CONFIG_REG 0x00 | ||
127 | #define AR933X_PLL_CLOCK_CTRL_REG 0x08 | ||
128 | |||
129 | #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 | ||
130 | #define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f | ||
131 | #define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 | ||
132 | #define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f | ||
133 | #define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 | ||
134 | #define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 | ||
135 | |||
136 | #define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) | ||
137 | #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 | ||
138 | #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 | ||
139 | #define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 | ||
140 | #define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 | ||
141 | #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 | ||
142 | #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 | ||
143 | |||
126 | /* | 144 | /* |
127 | * USB_CONFIG block | 145 | * USB_CONFIG block |
128 | */ | 146 | */ |
@@ -155,6 +173,8 @@ | |||
155 | 173 | ||
156 | #define AR724X_RESET_REG_RESET_MODULE 0x1c | 174 | #define AR724X_RESET_REG_RESET_MODULE 0x1c |
157 | 175 | ||
176 | #define AR933X_RESET_REG_BOOTSTRAP 0xac | ||
177 | |||
158 | #define MISC_INT_ETHSW BIT(12) | 178 | #define MISC_INT_ETHSW BIT(12) |
159 | #define MISC_INT_TIMER4 BIT(10) | 179 | #define MISC_INT_TIMER4 BIT(10) |
160 | #define MISC_INT_TIMER3 BIT(9) | 180 | #define MISC_INT_TIMER3 BIT(9) |
@@ -204,6 +224,8 @@ | |||
204 | #define AR913X_RESET_USB_HOST BIT(5) | 224 | #define AR913X_RESET_USB_HOST BIT(5) |
205 | #define AR913X_RESET_USB_PHY BIT(4) | 225 | #define AR913X_RESET_USB_PHY BIT(4) |
206 | 226 | ||
227 | #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) | ||
228 | |||
207 | #define REV_ID_MAJOR_MASK 0xfff0 | 229 | #define REV_ID_MAJOR_MASK 0xfff0 |
208 | #define REV_ID_MAJOR_AR71XX 0x00a0 | 230 | #define REV_ID_MAJOR_AR71XX 0x00a0 |
209 | #define REV_ID_MAJOR_AR913X 0x00b0 | 231 | #define REV_ID_MAJOR_AR913X 0x00b0 |
diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h index 2dfc94c0444b..407c9354f747 100644 --- a/arch/mips/include/asm/mach-ath79/ath79.h +++ b/arch/mips/include/asm/mach-ath79/ath79.h | |||
@@ -68,6 +68,12 @@ static inline int soc_is_ar913x(void) | |||
68 | ath79_soc == ATH79_SOC_AR9132); | 68 | ath79_soc == ATH79_SOC_AR9132); |
69 | } | 69 | } |
70 | 70 | ||
71 | static inline int soc_is_ar933x(void) | ||
72 | { | ||
73 | return (ath79_soc == ATH79_SOC_AR9330 || | ||
74 | ath79_soc == ATH79_SOC_AR9331); | ||
75 | } | ||
76 | |||
71 | extern void __iomem *ath79_ddr_base; | 77 | extern void __iomem *ath79_ddr_base; |
72 | extern void __iomem *ath79_pll_base; | 78 | extern void __iomem *ath79_pll_base; |
73 | extern void __iomem *ath79_reset_base; | 79 | extern void __iomem *ath79_reset_base; |