MIPS: ath79: add IRQ handling code for AR934X

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Cc: linux-mips@linux-mips.org
Cc: mcgrof@infradead.org
Patchwork: https://patchwork.linux-mips.org/patch/3510/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 25 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index 1a9234b5150b..d6af4eb5d2c0 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -92,6 +92,12 @@
 #define AR933X_DDR_REG_FLUSH_USB        0x84
 #define AR933X_DDR_REG_FLUSH_WMAC       0x88
 
+#define AR934X_DDR_REG_FLUSH_GE0        0x9c
+#define AR934X_DDR_REG_FLUSH_GE1        0xa0
+#define AR934X_DDR_REG_FLUSH_USB        0xa4
+#define AR934X_DDR_REG_FLUSH_PCIE       0xa8
+#define AR934X_DDR_REG_FLUSH_WMAC       0xac
+
 /*
  * PLL block
  */
@@ -222,6 +228,7 @@
 #define AR933X_RESET_REG_BOOTSTRAP              0xac
 
 #define AR934X_RESET_REG_BOOTSTRAP              0xb0
+#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS   0xac
 
 #define MISC_INT_ETHSW                  BIT(12)
 #define MISC_INT_TIMER4                 BIT(10)
@@ -295,6 +302,24 @@
 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
 #define AR934X_BOOTSTRAP_DDR1           BIT(0)
 
+#define AR934X_PCIE_WMAC_INT_WMAC_MISC          BIT(0)
+#define AR934X_PCIE_WMAC_INT_WMAC_TX            BIT(1)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXLP          BIT(2)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXHP          BIT(3)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC            BIT(4)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC0           BIT(5)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC1           BIT(6)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC2           BIT(7)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC3           BIT(8)
+#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
+        (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
+         AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
+        (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
+         AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+         AR934X_PCIE_WMAC_INT_PCIE_RC3)
+
 #define REV_ID_MAJOR_MASK               0xfff0
 #define REV_ID_MAJOR_AR71XX             0x00a0
 #define REV_ID_MAJOR_AR913X             0x00b0