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authorLinus Torvalds <torvalds@linux-foundation.org>2014-04-02 16:40:50 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-04-02 16:40:50 -0400
commitbdfc7cbdeef8cadba0e5793079ac0130b8e2220c (patch)
tree82af0cae4898e259edcc6cbdad639087dc1189a8 /arch/mips/include/asm/futex.h
parent62d1a3ba5adc5653d43f6cd3a90758bb6ad5d5bd (diff)
parentade63aada79c61bcd5f51cbd310f237399892268 (diff)
Merge branch 'mips-for-linux-next' of git://git.linux-mips.org/pub/scm/ralf/upstream-sfr
Pull MIPS updates from Ralf Baechle: - Support for Imgtec's Aptiv family of MIPS cores. - Improved detection of BCM47xx configurations. - Fix hiberation for certain configurations. - Add support for the Chinese Loongson 3 CPU, a MIPS64 R2 core and systems. - Detection and support for the MIPS P5600 core. - A few more random fixes that didn't make 3.14. - Support for the EVA Extended Virtual Addressing - Switch Alchemy to the platform PATA driver - Complete unification of Alchemy support - Allow availability of I/O cache coherency to be runtime detected - Improvments to multiprocessing support for Imgtec platforms - A few microoptimizations - Cleanups of FPU support - Paul Gortmaker's fixes for the init stuff - Support for seccomp * 'mips-for-linux-next' of git://git.linux-mips.org/pub/scm/ralf/upstream-sfr: (165 commits) MIPS: CPC: Use __raw_ memory access functions MIPS: CM: use __raw_ memory access functions MIPS: Fix warning when including smp-ops.h with CONFIG_SMP=n MIPS: Malta: GIC IPIs may be used without MT MIPS: smp-mt: Use common GIC IPI implementation MIPS: smp-cmp: Remove incorrect core number probe MIPS: Fix gigaton of warning building with microMIPS. MIPS: Fix core number detection for MT cores MIPS: MT: core_nvpes function to retrieve VPE count MIPS: Provide empty mips_mt_set_cpuoptions when CONFIG_MIPS_MT=n MIPS: Lasat: Replace del_timer by del_timer_sync MIPS: Malta: Setup PM I/O region on boot MIPS: Loongson: Add a Loongson-3 default config file MIPS: Loongson 3: Add CPU hotplug support MIPS: Loongson 3: Add Loongson-3 SMP support MIPS: Loongson: Add Loongson-3 Kconfig options MIPS: Loongson: Add swiotlb to support All-Memory DMA MIPS: Loongson 3: Add serial port support MIPS: Loongson 3: Add IRQ init and dispatch support MIPS: Loongson 3: Add HT-linked PCI support ...
Diffstat (limited to 'arch/mips/include/asm/futex.h')
-rw-r--r--arch/mips/include/asm/futex.h25
1 files changed, 13 insertions, 12 deletions
diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h
index 6ea15815d3ee..194cda0396a3 100644
--- a/arch/mips/include/asm/futex.h
+++ b/arch/mips/include/asm/futex.h
@@ -12,6 +12,7 @@
12 12
13#include <linux/futex.h> 13#include <linux/futex.h>
14#include <linux/uaccess.h> 14#include <linux/uaccess.h>
15#include <asm/asm-eva.h>
15#include <asm/barrier.h> 16#include <asm/barrier.h>
16#include <asm/errno.h> 17#include <asm/errno.h>
17#include <asm/war.h> 18#include <asm/war.h>
@@ -22,11 +23,11 @@
22 __asm__ __volatile__( \ 23 __asm__ __volatile__( \
23 " .set push \n" \ 24 " .set push \n" \
24 " .set noat \n" \ 25 " .set noat \n" \
25 " .set mips3 \n" \ 26 " .set arch=r4000 \n" \
26 "1: ll %1, %4 # __futex_atomic_op \n" \ 27 "1: ll %1, %4 # __futex_atomic_op \n" \
27 " .set mips0 \n" \ 28 " .set mips0 \n" \
28 " " insn " \n" \ 29 " " insn " \n" \
29 " .set mips3 \n" \ 30 " .set arch=r4000 \n" \
30 "2: sc $1, %2 \n" \ 31 "2: sc $1, %2 \n" \
31 " beqzl $1, 1b \n" \ 32 " beqzl $1, 1b \n" \
32 __WEAK_LLSC_MB \ 33 __WEAK_LLSC_MB \
@@ -48,12 +49,12 @@
48 __asm__ __volatile__( \ 49 __asm__ __volatile__( \
49 " .set push \n" \ 50 " .set push \n" \
50 " .set noat \n" \ 51 " .set noat \n" \
51 " .set mips3 \n" \ 52 " .set arch=r4000 \n" \
52 "1: ll %1, %4 # __futex_atomic_op \n" \ 53 "1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \
53 " .set mips0 \n" \ 54 " .set mips0 \n" \
54 " " insn " \n" \ 55 " " insn " \n" \
55 " .set mips3 \n" \ 56 " .set arch=r4000 \n" \
56 "2: sc $1, %2 \n" \ 57 "2: "user_sc("$1", "%2")" \n" \
57 " beqz $1, 1b \n" \ 58 " beqz $1, 1b \n" \
58 __WEAK_LLSC_MB \ 59 __WEAK_LLSC_MB \
59 "3: \n" \ 60 "3: \n" \
@@ -146,12 +147,12 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
146 "# futex_atomic_cmpxchg_inatomic \n" 147 "# futex_atomic_cmpxchg_inatomic \n"
147 " .set push \n" 148 " .set push \n"
148 " .set noat \n" 149 " .set noat \n"
149 " .set mips3 \n" 150 " .set arch=r4000 \n"
150 "1: ll %1, %3 \n" 151 "1: ll %1, %3 \n"
151 " bne %1, %z4, 3f \n" 152 " bne %1, %z4, 3f \n"
152 " .set mips0 \n" 153 " .set mips0 \n"
153 " move $1, %z5 \n" 154 " move $1, %z5 \n"
154 " .set mips3 \n" 155 " .set arch=r4000 \n"
155 "2: sc $1, %2 \n" 156 "2: sc $1, %2 \n"
156 " beqzl $1, 1b \n" 157 " beqzl $1, 1b \n"
157 __WEAK_LLSC_MB 158 __WEAK_LLSC_MB
@@ -173,13 +174,13 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
173 "# futex_atomic_cmpxchg_inatomic \n" 174 "# futex_atomic_cmpxchg_inatomic \n"
174 " .set push \n" 175 " .set push \n"
175 " .set noat \n" 176 " .set noat \n"
176 " .set mips3 \n" 177 " .set arch=r4000 \n"
177 "1: ll %1, %3 \n" 178 "1: "user_ll("%1", "%3")" \n"
178 " bne %1, %z4, 3f \n" 179 " bne %1, %z4, 3f \n"
179 " .set mips0 \n" 180 " .set mips0 \n"
180 " move $1, %z5 \n" 181 " move $1, %z5 \n"
181 " .set mips3 \n" 182 " .set arch=r4000 \n"
182 "2: sc $1, %2 \n" 183 "2: "user_sc("$1", "%2")" \n"
183 " beqz $1, 1b \n" 184 " beqz $1, 1b \n"
184 __WEAK_LLSC_MB 185 __WEAK_LLSC_MB
185 "3: \n" 186 "3: \n"