diff options
author | Huacai Chen <chenhc@lemote.com> | 2014-03-21 06:43:59 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-31 12:17:12 -0400 |
commit | 152ebb44eff3c2dae0fb7d5b19c3f65e7c8d3493 (patch) | |
tree | 3b88dc5ef2a1af4b22a55433d4bbbd7f10db9eb3 /arch/mips/include/asm/cpu.h | |
parent | d6d3c9afaab47418ab2d7f874fb8aeac1f067104 (diff) |
MIPS: Loongson: Add basic Loongson-3 definition
Loongson-3 is a multi-core MIPS family CPU, it support MIPS64R2 fully.
Loongson-3 has the same IMP field (0x6300) as Loongson-2.
Loongson-3 has a hardware-maintained cache, system software doesn't
need to maintain coherency.
Loongson-3A is the first revision of Loongson-3, and it is the quad-
core version of Loongson-2G. Loongson-3A has a simplified version named
Loongson-2Gq, the main difference between Loongson-3A/2Gq is 3A has two
HyperTransport controller but 2Gq has only one. HT0 is used for cross-
chip interconnection and HT1 is used to link PCI bus. Therefore, 2Gq
cannot support NUMA but 3A can. For software, Loongson-2Gq is simply
identified as Loongson-3A.
Exsisting Loongson family CPUs:
Loongson-1: Loongson-1A, Loongson-1B, they are 32-bit MIPS CPUs.
Loongson-2: Loongson-2E, Loongson-2F, Loongson-2G, they are 64-bit
single-core MIPS CPUs.
Loongson-3: Loongson-3A(including so-called Loongson-2Gq), they are
64-bit multi-core MIPS CPUs.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6629/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/cpu.h')
-rw-r--r-- | arch/mips/include/asm/cpu.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 01d757c83201..530eb8b3a68e 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h | |||
@@ -231,6 +231,7 @@ | |||
231 | #define PRID_REV_LOONGSON1B 0x0020 | 231 | #define PRID_REV_LOONGSON1B 0x0020 |
232 | #define PRID_REV_LOONGSON2E 0x0002 | 232 | #define PRID_REV_LOONGSON2E 0x0002 |
233 | #define PRID_REV_LOONGSON2F 0x0003 | 233 | #define PRID_REV_LOONGSON2F 0x0003 |
234 | #define PRID_REV_LOONGSON3A 0x0005 | ||
234 | 235 | ||
235 | /* | 236 | /* |
236 | * Older processors used to encode processor version and revision in two | 237 | * Older processors used to encode processor version and revision in two |
@@ -304,8 +305,8 @@ enum cpu_type_enum { | |||
304 | * MIPS64 class processors | 305 | * MIPS64 class processors |
305 | */ | 306 | */ |
306 | CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, | 307 | CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, |
307 | CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, | 308 | CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, |
308 | CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, | 309 | CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, |
309 | 310 | ||
310 | CPU_LAST | 311 | CPU_LAST |
311 | }; | 312 | }; |