diff options
| author | Markos Chandras <markos.chandras@imgtec.com> | 2014-11-20 08:31:48 -0500 |
|---|---|---|
| committer | Markos Chandras <markos.chandras@imgtec.com> | 2015-02-17 10:37:22 -0500 |
| commit | fa998ebbc02d11aa33a621e6f41cb15ce87e6b9e (patch) | |
| tree | 2585abfaa29dc870137f9c7d26115558ecf7c1e2 /arch/mips/include/asm/cmpxchg.h | |
| parent | 123e4b3bbc0afd3cb596ecbe165533b368529a8e (diff) | |
MIPS: asm: cmpxchg: Update ISA constraints for MIPS R6 support
MIPS R6 changed the opcodes for LL/SC instructions so we need to set
the correct ISA.
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'arch/mips/include/asm/cmpxchg.h')
| -rw-r--r-- | arch/mips/include/asm/cmpxchg.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h index 68baa0cf521a..d0a2a68ca600 100644 --- a/arch/mips/include/asm/cmpxchg.h +++ b/arch/mips/include/asm/cmpxchg.h | |||
| @@ -39,11 +39,11 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) | |||
| 39 | 39 | ||
| 40 | do { | 40 | do { |
| 41 | __asm__ __volatile__( | 41 | __asm__ __volatile__( |
| 42 | " .set arch=r4000 \n" | 42 | " .set "MIPS_ISA_ARCH_LEVEL" \n" |
| 43 | " ll %0, %3 # xchg_u32 \n" | 43 | " ll %0, %3 # xchg_u32 \n" |
| 44 | " .set mips0 \n" | 44 | " .set mips0 \n" |
| 45 | " move %2, %z4 \n" | 45 | " move %2, %z4 \n" |
| 46 | " .set arch=r4000 \n" | 46 | " .set "MIPS_ISA_ARCH_LEVEL" \n" |
| 47 | " sc %2, %1 \n" | 47 | " sc %2, %1 \n" |
| 48 | " .set mips0 \n" | 48 | " .set mips0 \n" |
| 49 | : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m), | 49 | : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m), |
| @@ -90,7 +90,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) | |||
| 90 | 90 | ||
| 91 | do { | 91 | do { |
| 92 | __asm__ __volatile__( | 92 | __asm__ __volatile__( |
| 93 | " .set arch=r4000 \n" | 93 | " .set "MIPS_ISA_ARCH_LEVEL" \n" |
| 94 | " lld %0, %3 # xchg_u64 \n" | 94 | " lld %0, %3 # xchg_u64 \n" |
| 95 | " move %2, %z4 \n" | 95 | " move %2, %z4 \n" |
| 96 | " scd %2, %1 \n" | 96 | " scd %2, %1 \n" |
| @@ -165,12 +165,12 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz | |||
| 165 | __asm__ __volatile__( \ | 165 | __asm__ __volatile__( \ |
| 166 | " .set push \n" \ | 166 | " .set push \n" \ |
| 167 | " .set noat \n" \ | 167 | " .set noat \n" \ |
| 168 | " .set arch=r4000 \n" \ | 168 | " .set "MIPS_ISA_ARCH_LEVEL" \n" \ |
| 169 | "1: " ld " %0, %2 # __cmpxchg_asm \n" \ | 169 | "1: " ld " %0, %2 # __cmpxchg_asm \n" \ |
| 170 | " bne %0, %z3, 2f \n" \ | 170 | " bne %0, %z3, 2f \n" \ |
| 171 | " .set mips0 \n" \ | 171 | " .set mips0 \n" \ |
| 172 | " move $1, %z4 \n" \ | 172 | " move $1, %z4 \n" \ |
| 173 | " .set arch=r4000 \n" \ | 173 | " .set "MIPS_ISA_ARCH_LEVEL" \n" \ |
| 174 | " " st " $1, %1 \n" \ | 174 | " " st " $1, %1 \n" \ |
| 175 | " beqz $1, 1b \n" \ | 175 | " beqz $1, 1b \n" \ |
| 176 | " .set pop \n" \ | 176 | " .set pop \n" \ |