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authorLinus Torvalds <torvalds@linux-foundation.org>2015-04-17 15:50:54 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-04-17 15:50:54 -0400
commitbfaf245022b4b8661af2e35f467cf0e91943c24c (patch)
treeb5a6ee49a047557a791eb897c8c9545a155e36b7 /arch/mips/include/asm/cacheflush.h
parent96d928ed75c4ba4253e82910a697ec7b06ace8b4 (diff)
parent3e20a26b02bd4f24945c87407df51948dd488620 (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "This is the main pull request for MIPS for Linux 4.1. Most noteworthy: - Add more Octeon-optimized crypto functions - Octeon crypto preemption and locking fixes - Little endian support for Octeon - Use correct CSR to soft reset Octeons - Support LEDs on the Octeon-based DSR-1000N - Fix PCI interrupt mapping for the Octeon-based DSR-1000N - Mark prom_free_prom_memory() as __init for a number of systems - Support for Imagination's Pistachio SOC. This includes arch and CLK bits. I'd like to merge pinctrl bits later - Improve parallelism of csum_partial for certain pipelines - Organize DTB files in subdirs like other architectures - Implement read_sched_clock for all MIPS platforms other than Octeon - Massive series of 38 fixes and cleanups for the FPU emulator / kernel - Further FPU remulator work to support new features. This sits on a separate branch which also has been pulled into the 4.1 KVM branch - Clean up and fixes for the SEAD3 eval board; remove unused file - Various updates for Netlogic platforms - A number of small updates for Loongson 3 platforms - Increase the memory limit for ATH79 platforms to 256MB - A fair number of fixes and updates for BCM47xx platforms - Finish the implementation of XPA support - MIPS FDC support. No, not floppy controller but Fast Debug Channel :) - Detect the R16000 used in SGI legacy platforms - Fix Kconfig dependencies for the SSB bus support" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (265 commits) MIPS: Makefile: Fix MIPS ASE detection code MIPS: asm: elf: Set O32 default FPU flags MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G MIPS: Kconfig: Disable SMP/CPS for 64-bit MIPS: Hibernate: flush TLB entries earlier MIPS: smp-cps: cpu_set FPU mask if FPU present MIPS: lose_fpu(): Disable FPU when MSA enabled MIPS: ralink: add missing symbol for RALINK_ILL_ACC MIPS: ralink: Fix bad config symbol in PCI makefile. SSB: fix Kconfig dependencies MIPS: Malta: Detect and fix bad memsize values Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores." MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard. MIPS: Fix cpu_has_mips_r2_exec_hazard. MIPS: kernel: entry.S: Set correct ISA level for mips_ihb MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter MIPS: unaligned: Fix regular load/store instruction emulation for EVA MIPS: unaligned: Surround load/store macros in do {} while statements ...
Diffstat (limited to 'arch/mips/include/asm/cacheflush.h')
-rw-r--r--arch/mips/include/asm/cacheflush.h38
1 files changed, 23 insertions, 15 deletions
diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h
index e08381a37f8b..723229f4cf27 100644
--- a/arch/mips/include/asm/cacheflush.h
+++ b/arch/mips/include/asm/cacheflush.h
@@ -29,6 +29,20 @@
29 * - flush_icache_all() flush the entire instruction cache 29 * - flush_icache_all() flush the entire instruction cache
30 * - flush_data_cache_page() flushes a page from the data cache 30 * - flush_data_cache_page() flushes a page from the data cache
31 */ 31 */
32
33 /*
34 * This flag is used to indicate that the page pointed to by a pte
35 * is dirty and requires cleaning before returning it to the user.
36 */
37#define PG_dcache_dirty PG_arch_1
38
39#define Page_dcache_dirty(page) \
40 test_bit(PG_dcache_dirty, &(page)->flags)
41#define SetPageDcacheDirty(page) \
42 set_bit(PG_dcache_dirty, &(page)->flags)
43#define ClearPageDcacheDirty(page) \
44 clear_bit(PG_dcache_dirty, &(page)->flags)
45
32extern void (*flush_cache_all)(void); 46extern void (*flush_cache_all)(void);
33extern void (*__flush_cache_all)(void); 47extern void (*__flush_cache_all)(void);
34extern void (*flush_cache_mm)(struct mm_struct *mm); 48extern void (*flush_cache_mm)(struct mm_struct *mm);
@@ -37,13 +51,15 @@ extern void (*flush_cache_range)(struct vm_area_struct *vma,
37 unsigned long start, unsigned long end); 51 unsigned long start, unsigned long end);
38extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); 52extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
39extern void __flush_dcache_page(struct page *page); 53extern void __flush_dcache_page(struct page *page);
54extern void __flush_icache_page(struct vm_area_struct *vma, struct page *page);
40 55
41#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 56#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
42static inline void flush_dcache_page(struct page *page) 57static inline void flush_dcache_page(struct page *page)
43{ 58{
44 if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) 59 if (cpu_has_dc_aliases)
45 __flush_dcache_page(page); 60 __flush_dcache_page(page);
46 61 else if (!cpu_has_ic_fills_f_dc)
62 SetPageDcacheDirty(page);
47} 63}
48 64
49#define flush_dcache_mmap_lock(mapping) do { } while (0) 65#define flush_dcache_mmap_lock(mapping) do { } while (0)
@@ -61,6 +77,11 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
61static inline void flush_icache_page(struct vm_area_struct *vma, 77static inline void flush_icache_page(struct vm_area_struct *vma,
62 struct page *page) 78 struct page *page)
63{ 79{
80 if (!cpu_has_ic_fills_f_dc && (vma->vm_flags & VM_EXEC) &&
81 Page_dcache_dirty(page)) {
82 __flush_icache_page(vma, page);
83 ClearPageDcacheDirty(page);
84 }
64} 85}
65 86
66extern void (*flush_icache_range)(unsigned long start, unsigned long end); 87extern void (*flush_icache_range)(unsigned long start, unsigned long end);
@@ -95,19 +116,6 @@ extern void (*flush_icache_all)(void);
95extern void (*local_flush_data_cache_page)(void * addr); 116extern void (*local_flush_data_cache_page)(void * addr);
96extern void (*flush_data_cache_page)(unsigned long addr); 117extern void (*flush_data_cache_page)(unsigned long addr);
97 118
98/*
99 * This flag is used to indicate that the page pointed to by a pte
100 * is dirty and requires cleaning before returning it to the user.
101 */
102#define PG_dcache_dirty PG_arch_1
103
104#define Page_dcache_dirty(page) \
105 test_bit(PG_dcache_dirty, &(page)->flags)
106#define SetPageDcacheDirty(page) \
107 set_bit(PG_dcache_dirty, &(page)->flags)
108#define ClearPageDcacheDirty(page) \
109 clear_bit(PG_dcache_dirty, &(page)->flags)
110
111/* Run kernel code uncached, useful for cache probing functions. */ 119/* Run kernel code uncached, useful for cache probing functions. */
112unsigned long run_uncached(void *func); 120unsigned long run_uncached(void *func);
113 121