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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2007-01-07 12:14:29 -0500
committerRalf Baechle <ralf@linux-mips.org>2007-02-06 11:53:08 -0500
commit97dcb82de6cc99a5669eb8e342efc24cceb1e77e (patch)
treee195fd57deda8d38652c746c04a7c374cdf951a0 /arch/mips/ddb5xxx
parentb6ec8f069bf202d2bd888aa9137b2cc3aad4c573 (diff)
[MIPS] Define MIPS_CPU_IRQ_BASE in generic header
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all platforms and are same value on most platforms (0 or 16, depends on CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make them customizable. This will save a few cycle on each CPU interrupt. A good side effect is removing some dependencies to MALTA in generic SMTC code. Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing them might cause some header dependency problem and there seems no good reason to customize it. So currently only VR41XX is using custom MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259. Testing this patch on those platforms is greatly appreciated. Thank you. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ddb5xxx')
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c
index a8bd2e66705c..bd7cd7c5f485 100644
--- a/arch/mips/ddb5xxx/ddb5477/irq.c
+++ b/arch/mips/ddb5xxx/ddb5477/irq.c
@@ -17,6 +17,7 @@
17#include <linux/ptrace.h> 17#include <linux/ptrace.h>
18 18
19#include <asm/i8259.h> 19#include <asm/i8259.h>
20#include <asm/irq_cpu.h>
20#include <asm/system.h> 21#include <asm/system.h>
21#include <asm/mipsregs.h> 22#include <asm/mipsregs.h>
22#include <asm/debug.h> 23#include <asm/debug.h>
@@ -73,7 +74,6 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
73} 74}
74 75
75extern void vrc5477_irq_init(u32 base); 76extern void vrc5477_irq_init(u32 base);
76extern void mips_cpu_irq_init(u32 base);
77static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; 77static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
78 78
79void __init arch_init_irq(void) 79void __init arch_init_irq(void)
@@ -125,7 +125,7 @@ void __init arch_init_irq(void)
125 125
126 /* init all controllers */ 126 /* init all controllers */
127 init_i8259_irqs(); 127 init_i8259_irqs();
128 mips_cpu_irq_init(CPU_IRQ_BASE); 128 mips_cpu_irq_init();
129 vrc5477_irq_init(VRC5477_IRQ_BASE); 129 vrc5477_irq_init(VRC5477_IRQ_BASE);
130 130
131 131