aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/ddb5xxx/ddb5074
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/ddb5xxx/ddb5074
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/mips/ddb5xxx/ddb5074')
-rw-r--r--arch/mips/ddb5xxx/ddb5074/Makefile8
-rw-r--r--arch/mips/ddb5xxx/ddb5074/int-handler.S120
-rw-r--r--arch/mips/ddb5xxx/ddb5074/irq.c159
-rw-r--r--arch/mips/ddb5xxx/ddb5074/nile4_pic.c287
-rw-r--r--arch/mips/ddb5xxx/ddb5074/setup.c235
5 files changed, 809 insertions, 0 deletions
diff --git a/arch/mips/ddb5xxx/ddb5074/Makefile b/arch/mips/ddb5xxx/ddb5074/Makefile
new file mode 100644
index 000000000000..488206b8d94e
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5074/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for the NEC DDB Vrc-5074 specific kernel interface routines
3# under Linux.
4#
5
6obj-y += setup.o irq.o int-handler.o nile4_pic.o
7
8EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/ddb5xxx/ddb5074/int-handler.S b/arch/mips/ddb5xxx/ddb5074/int-handler.S
new file mode 100644
index 000000000000..a78644150b37
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5074/int-handler.S
@@ -0,0 +1,120 @@
1/*
2 * arch/mips/ddb5074/int-handler.S -- NEC DDB Vrc-5074 interrupt handler
3 *
4 * Based on arch/mips/sgi/kernel/indyIRQ.S
5 *
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 *
8 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
9 * Sony Software Development Center Europe (SDCE), Brussels
10 */
11#include <asm/asm.h>
12#include <asm/mipsregs.h>
13#include <asm/regdef.h>
14#include <asm/stackframe.h>
15
16/* A lot of complication here is taken away because:
17 *
18 * 1) We handle one interrupt and return, sitting in a loop and moving across
19 * all the pending IRQ bits in the cause register is _NOT_ the answer, the
20 * common case is one pending IRQ so optimize in that direction.
21 *
22 * 2) We need not check against bits in the status register IRQ mask, that
23 * would make this routine slow as hell.
24 *
25 * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
26 * between like BSD spl() brain-damage.
27 *
28 * Furthermore, the IRQs on the INDY look basically (barring software IRQs
29 * which we don't use at all) like:
30 *
31 * MIPS IRQ Source
32 * -------- ------
33 * 0 Software (ignored)
34 * 1 Software (ignored)
35 * 2 Local IRQ level zero
36 * 3 Local IRQ level one
37 * 4 8254 Timer zero
38 * 5 8254 Timer one
39 * 6 Bus Error
40 * 7 R4k timer (what we use)
41 *
42 * We handle the IRQ according to _our_ priority which is:
43 *
44 * Highest ---- R4k Timer
45 * Local IRQ zero
46 * Local IRQ one
47 * Bus Error
48 * 8254 Timer zero
49 * Lowest ---- 8254 Timer one
50 *
51 * then we just return, if multiple IRQs are pending then we will just take
52 * another exception, big deal.
53 */
54
55 .text
56 .set noreorder
57 .set noat
58 .align 5
59 NESTED(ddbIRQ, PT_SIZE, sp)
60 SAVE_ALL
61 CLI
62 .set at
63 mfc0 s0, CP0_CAUSE # get irq mask
64
65#if 1
66 mfc0 t2,CP0_STATUS # get enabled interrupts
67 and s0,t2 # isolate allowed ones
68#endif
69 /* First we check for r4k counter/timer IRQ. */
70 andi a0, s0, CAUSEF_IP2 # delay slot, check local level zero
71 beq a0, zero, 1f
72 andi a0, s0, CAUSEF_IP3 # delay slot, check local level one
73
74 /* Wheee, local level zero interrupt. */
75 jal ddb_local0_irqdispatch
76 move a0, sp # delay slot
77
78 j ret_from_irq
79 nop # delay slot
80
811:
82 beq a0, zero, 1f
83 andi a0, s0, CAUSEF_IP6 # delay slot, check bus error
84
85 /* Wheee, local level one interrupt. */
86 move a0, sp
87 jal ddb_local1_irqdispatch
88 nop
89
90 j ret_from_irq
91 nop
92
931:
94 beq a0, zero, 1f
95 nop
96
97 /* Wheee, an asynchronous bus error... */
98 move a0, sp
99 jal ddb_buserror_irq
100 nop
101
102 j ret_from_irq
103 nop
104
1051:
106 /* Here by mistake? This is possible, what can happen
107 * is that by the time we take the exception the IRQ
108 * pin goes low, so just leave if this is the case.
109 */
110 andi a0, s0, (CAUSEF_IP4 | CAUSEF_IP5)
111 beq a0, zero, 1f
112
113 /* Must be one of the 8254 timers... */
114 move a0, sp
115 jal ddb_8254timer_irq
116 nop
1171:
118 j ret_from_irq
119 nop
120 END(ddbIRQ)
diff --git a/arch/mips/ddb5xxx/ddb5074/irq.c b/arch/mips/ddb5xxx/ddb5074/irq.c
new file mode 100644
index 000000000000..45088a1be414
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5074/irq.c
@@ -0,0 +1,159 @@
1/*
2 * arch/mips/ddb5074/irq.c -- NEC DDB Vrc-5074 interrupt routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7#include <linux/init.h>
8#include <linux/irq.h>
9#include <linux/signal.h>
10#include <linux/sched.h>
11#include <linux/types.h>
12#include <linux/interrupt.h>
13#include <linux/ioport.h>
14
15#include <asm/i8259.h>
16#include <asm/io.h>
17#include <asm/irq_cpu.h>
18#include <asm/ptrace.h>
19#include <asm/nile4.h>
20#include <asm/ddb5xxx/ddb5xxx.h>
21#include <asm/ddb5xxx/ddb5074.h>
22
23
24extern asmlinkage void ddbIRQ(void);
25
26static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
27
28#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
29#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */
30#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */
31
32#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */
33#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */
34#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */
35
36#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */
37#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */
38
39#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */
40#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */
41
42#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */
43#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */
44
45
46static void m1543_irq_setup(void)
47{
48 /*
49 * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all
50 * the possible IO sources in the M1543 are in use by us. We will
51 * use the following mapping:
52 *
53 * IRQ1 - keyboard (default set by M1543)
54 * IRQ3 - reserved for UART B (default set by M1543) (note that
55 * the schematics for the DDB Vrc-5074 board seem to
56 * indicate that IRQ3 is connected to the DS1386
57 * watchdog timer interrupt output so we might have
58 * a conflict)
59 * IRQ4 - reserved for UART A (default set by M1543)
60 * IRQ5 - parallel (default set by M1543)
61 * IRQ8 - DS1386 time of day (RTC) interrupt
62 * IRQ12 - mouse
63 */
64
65 /*
66 * Assing mouse interrupt to IRQ12
67 */
68
69 /* Enter configuration mode */
70 outb(0x51, M1543_PNP_CONFIG);
71 outb(0x23, M1543_PNP_CONFIG);
72
73 /* Select logical device 7 (Keyboard) */
74 outb(0x07, M1543_PNP_INDEX);
75 outb(0x07, M1543_PNP_DATA);
76
77 /* Select IRQ12 */
78 outb(0x72, M1543_PNP_INDEX);
79 outb(0x0c, M1543_PNP_DATA);
80
81 outb(0x30, M1543_PNP_INDEX);
82 printk("device 7, 0x30: %02x\n",inb(M1543_PNP_DATA));
83
84 outb(0x70, M1543_PNP_INDEX);
85 printk("device 7, 0x70: %02x\n",inb(M1543_PNP_DATA));
86
87 /* Leave configration mode */
88 outb(0xbb, M1543_PNP_CONFIG);
89
90
91}
92
93void ddb_local0_irqdispatch(struct pt_regs *regs)
94{
95 u32 mask;
96 int nile4_irq;
97
98 mask = nile4_get_irq_stat(0);
99
100 /* Handle the timer interrupt first */
101#if 0
102 if (mask & (1 << NILE4_INT_GPT)) {
103 do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
104 mask &= ~(1 << NILE4_INT_GPT);
105 }
106#endif
107 for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
108 if (mask & 1) {
109 if (nile4_irq == NILE4_INT_INTE) {
110 int i8259_irq;
111
112 nile4_clear_irq(NILE4_INT_INTE);
113 i8259_irq = nile4_i8259_iack();
114 do_IRQ(i8259_irq, regs);
115 } else
116 do_IRQ(nile4_to_irq(nile4_irq), regs);
117
118 }
119}
120
121void ddb_local1_irqdispatch(void)
122{
123 printk("ddb_local1_irqdispatch called\n");
124}
125
126void ddb_buserror_irq(void)
127{
128 printk("ddb_buserror_irq called\n");
129}
130
131void ddb_8254timer_irq(void)
132{
133 printk("ddb_8254timer_irq called\n");
134}
135
136void __init arch_init_irq(void)
137{
138 /* setup cascade interrupts */
139 setup_irq(NILE4_IRQ_BASE + NILE4_INT_INTE, &irq_cascade);
140 setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade);
141
142 set_except_vector(0, ddbIRQ);
143
144 nile4_irq_setup(NILE4_IRQ_BASE);
145 m1543_irq_setup();
146 init_i8259_irqs();
147
148
149 printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE);
150
151 mips_cpu_irq_init(CPU_IRQ_BASE);
152
153 printk("enabling 8259 cascade\n");
154
155 ddb5074_led_hex(0);
156
157 /* Enable the interrupt cascade */
158 nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE);
159}
diff --git a/arch/mips/ddb5xxx/ddb5074/nile4_pic.c b/arch/mips/ddb5xxx/ddb5074/nile4_pic.c
new file mode 100644
index 000000000000..68c127cd70c9
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5074/nile4_pic.c
@@ -0,0 +1,287 @@
1/*
2 * arch/mips/ddb5476/nile4.c --
3 * low-level PIC code for NEC Vrc-5476 (Nile 4)
4 *
5 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
6 * Sony Software Development Center Europe (SDCE), Brussels
7 *
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 */
12#include <linux/config.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/ioport.h>
17
18#include <asm/addrspace.h>
19
20#include <asm/ddb5xxx/ddb5xxx.h>
21
22static int irq_base;
23
24/*
25 * Interrupt Programming
26 */
27void nile4_map_irq(int nile4_irq, int cpu_irq)
28{
29 u32 offset, t;
30
31 offset = DDB_INTCTRL;
32 if (nile4_irq >= 8) {
33 offset += 4;
34 nile4_irq -= 8;
35 }
36 t = ddb_in32(offset);
37 t &= ~(7 << (nile4_irq * 4));
38 t |= cpu_irq << (nile4_irq * 4);
39 ddb_out32(offset, t);
40}
41
42void nile4_map_irq_all(int cpu_irq)
43{
44 u32 all, t;
45
46 all = cpu_irq;
47 all |= all << 4;
48 all |= all << 8;
49 all |= all << 16;
50 t = ddb_in32(DDB_INTCTRL);
51 t &= 0x88888888;
52 t |= all;
53 ddb_out32(DDB_INTCTRL, t);
54 t = ddb_in32(DDB_INTCTRL + 4);
55 t &= 0x88888888;
56 t |= all;
57 ddb_out32(DDB_INTCTRL + 4, t);
58}
59
60void nile4_enable_irq(unsigned int nile4_irq)
61{
62 u32 offset, t;
63
64 nile4_irq-=irq_base;
65
66 ddb5074_led_hex(8);
67
68 offset = DDB_INTCTRL;
69 if (nile4_irq >= 8) {
70 offset += 4;
71 nile4_irq -= 8;
72 }
73 ddb5074_led_hex(9);
74 t = ddb_in32(offset);
75 ddb5074_led_hex(0xa);
76 t |= 8 << (nile4_irq * 4);
77 ddb_out32(offset, t);
78 ddb5074_led_hex(0xb);
79}
80
81void nile4_disable_irq(unsigned int nile4_irq)
82{
83 u32 offset, t;
84
85 nile4_irq-=irq_base;
86
87 offset = DDB_INTCTRL;
88 if (nile4_irq >= 8) {
89 offset += 4;
90 nile4_irq -= 8;
91 }
92 t = ddb_in32(offset);
93 t &= ~(8 << (nile4_irq * 4));
94 ddb_out32(offset, t);
95}
96
97void nile4_disable_irq_all(void)
98{
99 ddb_out32(DDB_INTCTRL, 0);
100 ddb_out32(DDB_INTCTRL + 4, 0);
101}
102
103u16 nile4_get_irq_stat(int cpu_irq)
104{
105 return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
106}
107
108void nile4_enable_irq_output(int cpu_irq)
109{
110 u32 t;
111
112 t = ddb_in32(DDB_INTSTAT1 + 4);
113 t |= 1 << (16 + cpu_irq);
114 ddb_out32(DDB_INTSTAT1, t);
115}
116
117void nile4_disable_irq_output(int cpu_irq)
118{
119 u32 t;
120
121 t = ddb_in32(DDB_INTSTAT1 + 4);
122 t &= ~(1 << (16 + cpu_irq));
123 ddb_out32(DDB_INTSTAT1, t);
124}
125
126void nile4_set_pci_irq_polarity(int pci_irq, int high)
127{
128 u32 t;
129
130 t = ddb_in32(DDB_INTPPES);
131 if (high)
132 t &= ~(1 << (pci_irq * 2));
133 else
134 t |= 1 << (pci_irq * 2);
135 ddb_out32(DDB_INTPPES, t);
136}
137
138void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
139{
140 u32 t;
141
142 t = ddb_in32(DDB_INTPPES);
143 if (level)
144 t |= 2 << (pci_irq * 2);
145 else
146 t &= ~(2 << (pci_irq * 2));
147 ddb_out32(DDB_INTPPES, t);
148}
149
150void nile4_clear_irq(int nile4_irq)
151{
152 nile4_irq-=irq_base;
153 ddb_out32(DDB_INTCLR, 1 << nile4_irq);
154}
155
156void nile4_clear_irq_mask(u32 mask)
157{
158 ddb_out32(DDB_INTCLR, mask);
159}
160
161u8 nile4_i8259_iack(void)
162{
163 u8 irq;
164 u32 reg;
165
166 /* Set window 0 for interrupt acknowledge */
167 reg = ddb_in32(DDB_PCIINIT0);
168
169 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
170 irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
171 /* restore window 0 for PCI I/O space */
172 // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
173 ddb_out32(DDB_PCIINIT0, reg);
174
175 /* i8269.c set the base vector to be 0x0 */
176 return irq ;
177}
178
179static unsigned int nile4_irq_startup(unsigned int irq) {
180
181 nile4_enable_irq(irq);
182 return 0;
183
184}
185
186static void nile4_ack_irq(unsigned int irq) {
187
188 ddb5074_led_hex(4);
189
190 nile4_clear_irq(irq);
191 ddb5074_led_hex(2);
192 nile4_disable_irq(irq);
193
194 ddb5074_led_hex(0);
195}
196
197static void nile4_irq_end(unsigned int irq) {
198
199 ddb5074_led_hex(3);
200 if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
201 ddb5074_led_hex(5);
202 nile4_enable_irq(irq);
203 ddb5074_led_hex(7);
204 }
205
206 ddb5074_led_hex(1);
207}
208
209#define nile4_irq_shutdown nile4_disable_irq
210
211static hw_irq_controller nile4_irq_controller = {
212 "nile4",
213 nile4_irq_startup,
214 nile4_irq_shutdown,
215 nile4_enable_irq,
216 nile4_disable_irq,
217 nile4_ack_irq,
218 nile4_irq_end,
219 NULL
220};
221
222void nile4_irq_setup(u32 base) {
223
224 int i;
225
226 irq_base=base;
227
228 /* Map all interrupts to CPU int #0 */
229 nile4_map_irq_all(0);
230
231 /* PCI INTA#-E# must be level triggered */
232 nile4_set_pci_irq_level_or_edge(0, 1);
233 nile4_set_pci_irq_level_or_edge(1, 1);
234 nile4_set_pci_irq_level_or_edge(2, 1);
235 nile4_set_pci_irq_level_or_edge(3, 1);
236 nile4_set_pci_irq_level_or_edge(4, 1);
237
238 /* PCI INTA#-D# must be active low, INTE# must be active high */
239 nile4_set_pci_irq_polarity(0, 0);
240 nile4_set_pci_irq_polarity(1, 0);
241 nile4_set_pci_irq_polarity(2, 0);
242 nile4_set_pci_irq_polarity(3, 0);
243 nile4_set_pci_irq_polarity(4, 1);
244
245
246 for (i = 0; i < 16; i++) {
247 nile4_clear_irq(i);
248 nile4_disable_irq(i);
249 }
250
251 /* Enable CPU int #0 */
252 nile4_enable_irq_output(0);
253
254 for (i= base; i< base + NUM_NILE4_INTERRUPTS; i++) {
255 irq_desc[i].status = IRQ_DISABLED;
256 irq_desc[i].action = NULL;
257 irq_desc[i].depth = 1;
258 irq_desc[i].handler = &nile4_irq_controller;
259 }
260}
261
262#if defined(CONFIG_RUNTIME_DEBUG)
263void nile4_dump_irq_status(void)
264{
265 printk(KERN_DEBUG "
266 CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
267 (void *) ddb_in32(DDB_CPUSTAT));
268 printk(KERN_DEBUG "
269 INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
270 (void *) ddb_in32(DDB_INTCTRL));
271 printk(KERN_DEBUG
272 "INTSTAT0 = %p:%p\n",
273 (void *) ddb_in32(DDB_INTSTAT0 + 4),
274 (void *) ddb_in32(DDB_INTSTAT0));
275 printk(KERN_DEBUG
276 "INTSTAT1 = %p:%p\n",
277 (void *) ddb_in32(DDB_INTSTAT1 + 4),
278 (void *) ddb_in32(DDB_INTSTAT1));
279 printk(KERN_DEBUG
280 "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
281 (void *) ddb_in32(DDB_INTCLR));
282 printk(KERN_DEBUG
283 "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
284 (void *) ddb_in32(DDB_INTPPES));
285}
286
287#endif
diff --git a/arch/mips/ddb5xxx/ddb5074/setup.c b/arch/mips/ddb5xxx/ddb5074/setup.c
new file mode 100644
index 000000000000..a73a5978d550
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5074/setup.c
@@ -0,0 +1,235 @@
1/*
2 * arch/mips/ddb5074/setup.c -- NEC DDB Vrc-5074 setup routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7#include <linux/init.h>
8#include <linux/kbd_ll.h>
9#include <linux/kernel.h>
10#include <linux/kdev_t.h>
11#include <linux/types.h>
12#include <linux/sched.h>
13#include <linux/pci.h>
14#include <linux/ide.h>
15#include <linux/ioport.h>
16#include <linux/irq.h>
17
18#include <asm/addrspace.h>
19#include <asm/bcache.h>
20#include <asm/irq.h>
21#include <asm/reboot.h>
22#include <asm/gdb-stub.h>
23#include <asm/time.h>
24#include <asm/nile4.h>
25#include <asm/ddb5xxx/ddb5074.h>
26#include <asm/ddb5xxx/ddb5xxx.h>
27
28static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
29
30static void ddb_machine_restart(char *command)
31{
32 u32 t;
33
34 /* PCI cold reset */
35 t = nile4_in32(NILE4_PCICTRL + 4);
36 t |= 0x40000000;
37 nile4_out32(NILE4_PCICTRL + 4, t);
38 /* CPU cold reset */
39 t = nile4_in32(NILE4_CPUSTAT);
40 t |= 1;
41 nile4_out32(NILE4_CPUSTAT, t);
42 /* Call the PROM */
43 back_to_prom();
44}
45
46static void ddb_machine_halt(void)
47{
48 printk("DDB Vrc-5074 halted.\n");
49 do {
50 } while (1);
51}
52
53static void ddb_machine_power_off(void)
54{
55 printk("DDB Vrc-5074 halted. Please turn off the power.\n");
56 do {
57 } while (1);
58}
59
60extern void rtc_ds1386_init(unsigned long base);
61
62extern void (*board_timer_setup) (struct irqaction * irq);
63
64static void __init ddb_timer_init(struct irqaction *irq)
65{
66 /* set the clock to 1 Hz */
67 nile4_out32(NILE4_T2CTRL, 1000000);
68 /* enable the General-Purpose Timer */
69 nile4_out32(NILE4_T2CTRL + 4, 0x00000001);
70 /* reset timer */
71 nile4_out32(NILE4_T2CNTR, 0);
72 /* enable interrupt */
73 setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
74 nile4_enable_irq(nile4_to_irq(NILE4_INT_GPT));
75 change_c0_status(ST0_IM,
76 IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
77
78}
79
80static void __init ddb_time_init(void)
81{
82 /* we have ds1396 RTC chip */
83 rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
84}
85
86
87
88static void __init ddb5074_setup(void)
89{
90 set_io_port_base(NILE4_PCI_IO_BASE);
91 isa_slot_offset = NILE4_PCI_MEM_BASE;
92 board_timer_setup = ddb_timer_init;
93 board_time_init = ddb_time_init;
94
95
96 _machine_restart = ddb_machine_restart;
97 _machine_halt = ddb_machine_halt;
98 _machine_power_off = ddb_machine_power_off;
99
100 ddb_out32(DDB_BAR0, 0);
101
102 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, 0x10);
103 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE , 0x10);
104
105 /* Reboot on panic */
106 panic_timeout = 180;
107}
108
109early_initcall(ddb5074_setup);
110
111#define USE_NILE4_SERIAL 0
112
113#if USE_NILE4_SERIAL
114#define ns16550_in(reg) nile4_in8((reg)*8)
115#define ns16550_out(reg, val) nile4_out8((reg)*8, (val))
116#else
117#define NS16550_BASE (NILE4_PCI_IO_BASE+0x03f8)
118static inline u8 ns16550_in(u32 reg)
119{
120 return *(volatile u8 *) (NS16550_BASE + reg);
121}
122
123static inline void ns16550_out(u32 reg, u8 val)
124{
125 *(volatile u8 *) (NS16550_BASE + reg) = val;
126}
127#endif
128
129#define NS16550_RBR 0
130#define NS16550_THR 0
131#define NS16550_DLL 0
132#define NS16550_IER 1
133#define NS16550_DLM 1
134#define NS16550_FCR 2
135#define NS16550_IIR 2
136#define NS16550_LCR 3
137#define NS16550_MCR 4
138#define NS16550_LSR 5
139#define NS16550_MSR 6
140#define NS16550_SCR 7
141
142#define NS16550_LSR_DR 0x01 /* Data ready */
143#define NS16550_LSR_OE 0x02 /* Overrun */
144#define NS16550_LSR_PE 0x04 /* Parity error */
145#define NS16550_LSR_FE 0x08 /* Framing error */
146#define NS16550_LSR_BI 0x10 /* Break */
147#define NS16550_LSR_THRE 0x20 /* Xmit holding register empty */
148#define NS16550_LSR_TEMT 0x40 /* Xmitter empty */
149#define NS16550_LSR_ERR 0x80 /* Error */
150
151
152void _serinit(void)
153{
154#if USE_NILE4_SERIAL
155 ns16550_out(NS16550_LCR, 0x80);
156 ns16550_out(NS16550_DLM, 0x00);
157 ns16550_out(NS16550_DLL, 0x36); /* 9600 baud */
158 ns16550_out(NS16550_LCR, 0x00);
159 ns16550_out(NS16550_LCR, 0x03);
160 ns16550_out(NS16550_FCR, 0x47);
161#else
162 /* done by PMON */
163#endif
164}
165
166void _putc(char c)
167{
168 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
169 ns16550_out(NS16550_THR, c);
170 if (c == '\n') {
171 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
172 ns16550_out(NS16550_THR, '\r');
173 }
174}
175
176void _puts(const char *s)
177{
178 char c;
179 while ((c = *s++))
180 _putc(c);
181}
182
183char _getc(void)
184{
185 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_DR));
186 return ns16550_in(NS16550_RBR);
187}
188
189int _testc(void)
190{
191 return (ns16550_in(NS16550_LSR) & NS16550_LSR_DR) != 0;
192}
193
194
195/*
196 * Hexadecimal 7-segment LED
197 */
198void ddb5074_led_hex(int hex)
199{
200 outb(hex, 0x80);
201}
202
203
204/*
205 * LEDs D2 and D3, connected to the GPIO pins of the PMU in the ALi M1543
206 */
207struct pci_dev *pci_pmu = NULL;
208
209void ddb5074_led_d2(int on)
210{
211 u8 t;
212
213 if (pci_pmu) {
214 pci_read_config_byte(pci_pmu, 0x7e, &t);
215 if (on)
216 t &= 0x7f;
217 else
218 t |= 0x80;
219 pci_write_config_byte(pci_pmu, 0x7e, t);
220 }
221}
222
223void ddb5074_led_d3(int on)
224{
225 u8 t;
226
227 if (pci_pmu) {
228 pci_read_config_byte(pci_pmu, 0x7e, &t);
229 if (on)
230 t &= 0xbf;
231 else
232 t |= 0x40;
233 pci_write_config_byte(pci_pmu, 0x7e, t);
234 }
235}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 13:12:02 -0500