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authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2006-10-13 11:25:04 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-11-29 20:14:43 -0500
commit56ae58333031bb0564c141f955d1e42276cade55 (patch)
treede1e272dbebb07f268b6d9bc1fd553279f517ac8 /arch/mips/cobalt
parent4e3884fc83f40b5daabceeee3a428a8ebebbbe4a (diff)
[MIPS] Rewrite GALILEO_INL/GALILEO_OUTL to GT_READ/GT_WRITE
This patch has rewritten GALILEO_INL/GALILEO_OUTL using GT_READ/GT_WRITE. This patch tested on Cobalt Qube2. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/cobalt')
-rw-r--r--arch/mips/cobalt/irq.c31
-rw-r--r--arch/mips/cobalt/setup.c16
2 files changed, 22 insertions, 25 deletions
diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c
index 82e569d5b02c..4c46f0e73783 100644
--- a/arch/mips/cobalt/irq.c
+++ b/arch/mips/cobalt/irq.c
@@ -45,25 +45,22 @@ static inline void galileo_irq(void)
45{ 45{
46 unsigned int mask, pending, devfn; 46 unsigned int mask, pending, devfn;
47 47
48 mask = GALILEO_INL(GT_INTRMASK_OFS); 48 mask = GT_READ(GT_INTRMASK_OFS);
49 pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask; 49 pending = GT_READ(GT_INTRCAUSE_OFS) & mask;
50 50
51 if (pending & GALILEO_INTR_T0EXP) { 51 if (pending & GT_INTR_T0EXP_MSK) {
52 52 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);
53 GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);
54 do_IRQ(COBALT_GALILEO_IRQ); 53 do_IRQ(COBALT_GALILEO_IRQ);
55 54 } else if (pending & GT_INTR_RETRYCTR0_MSK) {
56 } else if (pending & GALILEO_INTR_RETRY_CTR) { 55 devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;
57 56 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);
58 devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8; 57 printk(KERN_WARNING
59 GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS); 58 "Galileo: PCI retry count exceeded (%02x.%u)\n",
60 printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n", 59 PCI_SLOT(devfn), PCI_FUNC(devfn));
61 PCI_SLOT(devfn), PCI_FUNC(devfn));
62
63 } else { 60 } else {
64 61 GT_WRITE(GT_INTRMASK_OFS, mask & ~pending);
65 GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS); 62 printk(KERN_WARNING
66 printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending); 63 "Galileo: masking unexpected interrupt %08x\n", pending);
67 } 64 }
68} 65}
69 66
@@ -104,7 +101,7 @@ void __init arch_init_irq(void)
104 * Mask all Galileo interrupts. The Galileo 101 * Mask all Galileo interrupts. The Galileo
105 * handler is set in cobalt_timer_setup() 102 * handler is set in cobalt_timer_setup()
106 */ 103 */
107 GALILEO_OUTL(0, GT_INTRMASK_OFS); 104 GT_WRITE(GT_INTRMASK_OFS, 0);
108 105
109 init_i8259_irqs(); /* 0 ... 15 */ 106 init_i8259_irqs(); /* 0 ... 15 */
110 mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */ 107 mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */
diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index bf9dc72b9720..e8f0f20b852d 100644
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -51,23 +51,23 @@ const char *get_system_type(void)
51void __init plat_timer_setup(struct irqaction *irq) 51void __init plat_timer_setup(struct irqaction *irq)
52{ 52{
53 /* Load timer value for HZ (TCLK is 50MHz) */ 53 /* Load timer value for HZ (TCLK is 50MHz) */
54 GALILEO_OUTL(50*1000*1000 / HZ, GT_TC0_OFS); 54 GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
55 55
56 /* Enable timer */ 56 /* Enable timer */
57 GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS); 57 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
58 58
59 /* Register interrupt */ 59 /* Register interrupt */
60 setup_irq(COBALT_GALILEO_IRQ, irq); 60 setup_irq(COBALT_GALILEO_IRQ, irq);
61 61
62 /* Enable interrupt */ 62 /* Enable interrupt */
63 GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS); 63 GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
64} 64}
65 65
66extern struct pci_ops gt64111_pci_ops; 66extern struct pci_ops gt64111_pci_ops;
67 67
68static struct resource cobalt_mem_resource = { 68static struct resource cobalt_mem_resource = {
69 .start = GT64111_MEM_BASE, 69 .start = GT_DEF_PCI0_MEM0_BASE,
70 .end = GT64111_MEM_END, 70 .end = GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1,
71 .name = "PCI memory", 71 .name = "PCI memory",
72 .flags = IORESOURCE_MEM 72 .flags = IORESOURCE_MEM
73}; 73};
@@ -115,7 +115,7 @@ static struct pci_controller cobalt_pci_controller = {
115 .mem_resource = &cobalt_mem_resource, 115 .mem_resource = &cobalt_mem_resource,
116 .mem_offset = 0, 116 .mem_offset = 0,
117 .io_resource = &cobalt_io_resource, 117 .io_resource = &cobalt_io_resource,
118 .io_offset = 0 - GT64111_IO_BASE 118 .io_offset = 0 - GT_DEF_PCI0_IO_BASE,
119}; 119};
120 120
121void __init plat_mem_setup(void) 121void __init plat_mem_setup(void)
@@ -128,7 +128,7 @@ void __init plat_mem_setup(void)
128 _machine_halt = cobalt_machine_halt; 128 _machine_halt = cobalt_machine_halt;
129 pm_power_off = cobalt_machine_power_off; 129 pm_power_off = cobalt_machine_power_off;
130 130
131 set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE)); 131 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
132 132
133 /* I/O port resource must include UART and LCD/buttons */ 133 /* I/O port resource must include UART and LCD/buttons */
134 ioport_resource.end = 0x0fffffff; 134 ioport_resource.end = 0x0fffffff;
@@ -139,7 +139,7 @@ void __init plat_mem_setup(void)
139 139
140 /* Read the cobalt id register out of the PCI config space */ 140 /* Read the cobalt id register out of the PCI config space */
141 PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3)); 141 PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));
142 cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS); 142 cobalt_board_id = GT_READ(GT_PCI0_CFGDATA_OFS);
143 cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8); 143 cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
144 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id); 144 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
145 145