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authorDavid Daney <david.daney@cavium.com>2012-04-26 14:10:28 -0400
committerRalf Baechle <ralf@linux-mips.org>2012-12-13 12:15:24 -0500
commit43f01da0f2794b464ade2ffe1f780c69d7ce7b75 (patch)
treedcbf33bffe33aa06d967c451df48e0b78c32ebdb /arch/mips/cavium-octeon
parentf772cdb2bd544eeb3e83a8bb42629d155c1b53fd (diff)
MIPS/OCTEON/ata: Convert pata_octeon_cf.c to use device tree.
The patch needs to eliminate the definition of OCTEON_IRQ_BOOTDMA so that the device tree code can map the interrupt, so in order to not temporarily break things, we do a single patch to both the interrupt registration code and the pata_octeon_cf driver. Also rolled in is a conversion to use hrtimers and corrections to the timing calculations. Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: David Daney <david.daney@cavium.com>
Diffstat (limited to 'arch/mips/cavium-octeon')
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c1
-rw-r--r--arch/mips/cavium-octeon/octeon-platform.c102
2 files changed, 0 insertions, 103 deletions
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 02b15eed4bcd..46f5dbceeecc 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -1266,7 +1266,6 @@ static void __init octeon_irq_init_ciu(void)
1266 octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52); 1266 octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52);
1267 1267
1268 octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 0, 56); 1268 octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 0, 56);
1269 octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_BOOTDMA, 0, 63);
1270 1269
1271 /* CIU_1 */ 1270 /* CIU_1 */
1272 for (i = 0; i < 16; i++) 1271 for (i = 0; i < 16; i++)
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index 0938df10a71c..3c1b625a5859 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -24,108 +24,6 @@
24#include <asm/octeon/cvmx-helper.h> 24#include <asm/octeon/cvmx-helper.h>
25#include <asm/octeon/cvmx-helper-board.h> 25#include <asm/octeon/cvmx-helper-board.h>
26 26
27static struct octeon_cf_data octeon_cf_data;
28
29static int __init octeon_cf_device_init(void)
30{
31 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
32 unsigned long base_ptr, region_base, region_size;
33 struct platform_device *pd;
34 struct resource cf_resources[3];
35 unsigned int num_resources;
36 int i;
37 int ret = 0;
38
39 /* Setup octeon-cf platform device if present. */
40 base_ptr = 0;
41 if (octeon_bootinfo->major_version == 1
42 && octeon_bootinfo->minor_version >= 1) {
43 if (octeon_bootinfo->compact_flash_common_base_addr)
44 base_ptr =
45 octeon_bootinfo->compact_flash_common_base_addr;
46 } else {
47 base_ptr = 0x1d000800;
48 }
49
50 if (!base_ptr)
51 return ret;
52
53 /* Find CS0 region. */
54 for (i = 0; i < 8; i++) {
55 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
56 region_base = mio_boot_reg_cfg.s.base << 16;
57 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
58 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
59 && base_ptr < region_base + region_size)
60 break;
61 }
62 if (i >= 7) {
63 /* i and i + 1 are CS0 and CS1, both must be less than 8. */
64 goto out;
65 }
66 octeon_cf_data.base_region = i;
67 octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
68 octeon_cf_data.base_region_bias = base_ptr - region_base;
69 memset(cf_resources, 0, sizeof(cf_resources));
70 num_resources = 0;
71 cf_resources[num_resources].flags = IORESOURCE_MEM;
72 cf_resources[num_resources].start = region_base;
73 cf_resources[num_resources].end = region_base + region_size - 1;
74 num_resources++;
75
76
77 if (!(base_ptr & 0xfffful)) {
78 /*
79 * Boot loader signals availability of DMA (true_ide
80 * mode) by setting low order bits of base_ptr to
81 * zero.
82 */
83
84 /* Assume that CS1 immediately follows. */
85 mio_boot_reg_cfg.u64 =
86 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
87 region_base = mio_boot_reg_cfg.s.base << 16;
88 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
89 if (!mio_boot_reg_cfg.s.en)
90 goto out;
91
92 cf_resources[num_resources].flags = IORESOURCE_MEM;
93 cf_resources[num_resources].start = region_base;
94 cf_resources[num_resources].end = region_base + region_size - 1;
95 num_resources++;
96
97 octeon_cf_data.dma_engine = 0;
98 cf_resources[num_resources].flags = IORESOURCE_IRQ;
99 cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
100 cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
101 num_resources++;
102 } else {
103 octeon_cf_data.dma_engine = -1;
104 }
105
106 pd = platform_device_alloc("pata_octeon_cf", -1);
107 if (!pd) {
108 ret = -ENOMEM;
109 goto out;
110 }
111 pd->dev.platform_data = &octeon_cf_data;
112
113 ret = platform_device_add_resources(pd, cf_resources, num_resources);
114 if (ret)
115 goto fail;
116
117 ret = platform_device_add(pd);
118 if (ret)
119 goto fail;
120
121 return ret;
122fail:
123 platform_device_put(pd);
124out:
125 return ret;
126}
127device_initcall(octeon_cf_device_init);
128
129/* Octeon Random Number Generator. */ 27/* Octeon Random Number Generator. */
130static int __init octeon_rng_device_init(void) 28static int __init octeon_rng_device_init(void)
131{ 29{