[MIPS] Alchemy: work around clock misdetection on early Au1000

Work around the CPU clock miscalculation on Au1000DA/HA/HB due the
sys_cpupll register being write-only, i.e. actually do what the comment
before cal_r4off() function advertised for years but the code failed at.
This is achieved by just giving user a chance to define the clock
explicitly  in the board config. via CONFIG_SOC_AU1000_FREQUENCY option,
defaulting to 396 MHz if the option is not given...

The patch is based on the AMD's big unpublished patch, the issue seems to
be an undocumented errata (or feature :-)...

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 10 insertions, 3 deletions

diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c
index d885e3848ec6..9e4ab80caab6 100644
--- a/arch/mips/au1000/common/setup.c
+++ b/arch/mips/au1000/common/setup.c
@@ -57,7 +57,7 @@ void __init plat_mem_setup(void)
 {
         struct  cpu_spec *sp;
         char *argptr;
-        unsigned long prid, cpupll, bclk = 1;
+        unsigned long prid, cpufreq, bclk = 1;
 
         set_cpuspec();
         sp = cur_cpu_spec[0];
@@ -65,8 +65,15 @@ void __init plat_mem_setup(void)
         board_setup();  /* board specific setup */
 
         prid = read_c0_prid();
-        cpupll = (au_readl(0xB1900060) & 0x3F) * 12;
-        printk("(PRId %08lx) @ %ldMHZ\n", prid, cpupll);
+        if (sp->cpu_pll_wo)
+#ifdef CONFIG_SOC_AU1000_FREQUENCY
+                cpufreq = CONFIG_SOC_AU1000_FREQUENCY / 1000000;
+#else
+                cpufreq = 396;
+#endif
+        else
+                cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12;
+        printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq);
 
         bclk = sp->cpu_bclk;
         if (bclk)