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authorManuel Lauss <manuel.lauss@googlemail.com>2011-08-02 13:51:03 -0400
committerRalf Baechle <ralf@linux-mips.org>2011-10-24 18:34:23 -0400
commitce1d43b9a9e8a3db8fe91696c0b0e3ac1a154e34 (patch)
tree7e47005c61e98f44005c17a636457c4398c73fdd /arch/mips/alchemy
parent2e8fd2e5efe6b7cebba0beec44c6c2f474c6b726 (diff)
MIPS: Alchemy: support multiple GPIO styles in one kernel
For GPIOLIB=y decide at runtime which gpiochips to register; in the GPIOLIB=n case, the gpio headers need to be reshuffled a bit to make multiple implementations coexist peacefully. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2679/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy')
-rw-r--r--arch/mips/alchemy/common/Makefile4
-rw-r--r--arch/mips/alchemy/common/gpiolib.c (renamed from arch/mips/alchemy/common/gpiolib-au1000.c)35
2 files changed, 22 insertions, 17 deletions
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index 27811fe341d6..62f0d39e93cd 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -12,9 +12,7 @@ obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o
12 12
13# optional gpiolib support 13# optional gpiolib support
14ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) 14ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
15 ifeq ($(CONFIG_GPIOLIB),y) 15 obj-$(CONFIG_GPIOLIB) += gpiolib.o
16 obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += gpiolib-au1000.o
17 endif
18endif 16endif
19 17
20obj-$(CONFIG_PCI) += pci.o 18obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/mips/alchemy/common/gpiolib-au1000.c b/arch/mips/alchemy/common/gpiolib.c
index c8e1a94d4a95..91fb4d9e30fd 100644
--- a/arch/mips/alchemy/common/gpiolib-au1000.c
+++ b/arch/mips/alchemy/common/gpiolib.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org> 2 * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
3 * GPIOLIB support for Au1000, Au1500, Au1100, Au1550 and Au12x0. 3 * GPIOLIB support for Alchemy chips.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
@@ -23,18 +23,18 @@
23 * 675 Mass Ave, Cambridge, MA 02139, USA. 23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 * 24 *
25 * Notes : 25 * Notes :
26 * au1000 SoC have only one GPIO block : GPIO1 26 * This file must ONLY be built when CONFIG_GPIOLIB=y and
27 * Au1100, Au15x0, Au12x0 have a second one : GPIO2 27 * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail!
28 * au1000 SoC have only one GPIO block : GPIO1
29 * Au1100, Au15x0, Au12x0 have a second one : GPIO2
28 */ 30 */
29 31
32#include <linux/init.h>
30#include <linux/kernel.h> 33#include <linux/kernel.h>
31#include <linux/module.h> 34#include <linux/module.h>
32#include <linux/types.h> 35#include <linux/types.h>
33#include <linux/platform_device.h>
34#include <linux/gpio.h> 36#include <linux/gpio.h>
35 37#include <asm/mach-au1x00/gpio-au1000.h>
36#include <asm/mach-au1x00/au1000.h>
37#include <asm/mach-au1x00/gpio.h>
38 38
39static int gpio2_get(struct gpio_chip *chip, unsigned offset) 39static int gpio2_get(struct gpio_chip *chip, unsigned offset)
40{ 40{
@@ -115,12 +115,19 @@ struct gpio_chip alchemy_gpio_chip[] = {
115 }, 115 },
116}; 116};
117 117
118static int __init alchemy_gpiolib_init(void) 118static int __init alchemy_gpiochip_init(void)
119{ 119{
120 gpiochip_add(&alchemy_gpio_chip[0]); 120 int ret = 0;
121 if (alchemy_get_cputype() != ALCHEMY_CPU_AU1000) 121
122 gpiochip_add(&alchemy_gpio_chip[1]); 122 switch (alchemy_get_cputype()) {
123 123 case ALCHEMY_CPU_AU1000:
124 return 0; 124 ret = gpiochip_add(&alchemy_gpio_chip[0]);
125 break;
126 case ALCHEMY_CPU_AU1500...ALCHEMY_CPU_AU1200:
127 ret = gpiochip_add(&alchemy_gpio_chip[0]);
128 ret |= gpiochip_add(&alchemy_gpio_chip[1]);
129 break;
130 }
131 return ret;
125} 132}
126arch_initcall(alchemy_gpiolib_init); 133arch_initcall(alchemy_gpiochip_init);