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authorThomas Gleixner <tglx@linutronix.de>2011-05-20 14:06:24 -0400
committerThomas Gleixner <tglx@linutronix.de>2011-05-20 14:08:05 -0400
commit250f972d85effad5b6e10da4bbd877e6a4b503b6 (patch)
tree007393a6fc6439af7e0121dd99a6f9f9fb8405bc /arch/mips/alchemy/xxs1500
parent7372b0b122af0f6675f3ab65bfd91c8a438e0480 (diff)
parentbbe7b8bef48c567f5ff3f6041c1fb011292e8f12 (diff)
Merge branch 'timers/urgent' into timers/core
Reason: Get upstream fixes and kfree_rcu which is necessary for a follow up patch. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/mips/alchemy/xxs1500')
-rw-r--r--arch/mips/alchemy/xxs1500/board_setup.c11
-rw-r--r--arch/mips/alchemy/xxs1500/init.c7
2 files changed, 7 insertions, 11 deletions
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index febfb0fb0896..81e57fad07ab 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -66,13 +66,10 @@ void __init board_setup(void)
66 au_writel(pin_func, SYS_PINFUNC); 66 au_writel(pin_func, SYS_PINFUNC);
67 67
68 /* Enable UART */ 68 /* Enable UART */
69 au_writel(0x01, UART3_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */ 69 alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
70 mdelay(10); 70 /* Enable DTR (MCR bit 0) = USB power up */
71 au_writel(0x03, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */ 71 __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
72 mdelay(10); 72 wmb();
73
74 /* Enable DTR = USB power up */
75 au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */
76 73
77#ifdef CONFIG_PCI 74#ifdef CONFIG_PCI
78#if defined(__MIPSEB__) 75#if defined(__MIPSEB__)
diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c
index 15125c2fda7d..0ee02cfa989d 100644
--- a/arch/mips/alchemy/xxs1500/init.c
+++ b/arch/mips/alchemy/xxs1500/init.c
@@ -51,14 +51,13 @@ void __init prom_init(void)
51 prom_init_cmdline(); 51 prom_init_cmdline();
52 52
53 memsize_str = prom_getenv("memsize"); 53 memsize_str = prom_getenv("memsize");
54 if (!memsize_str) 54 if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))
55 memsize = 0x04000000; 55 memsize = 0x04000000;
56 else 56
57 strict_strtoul(memsize_str, 0, &memsize);
58 add_memory_region(0, memsize, BOOT_MEM_RAM); 57 add_memory_region(0, memsize, BOOT_MEM_RAM);
59} 58}
60 59
61void prom_putchar(unsigned char c) 60void prom_putchar(unsigned char c)
62{ 61{
63 alchemy_uart_putchar(UART0_PHYS_ADDR, c); 62 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
64} 63}