Merge branch 'linus' into x86/platform

Reason: Import mainline device tree changes on which further patches
        depend on or conflict.

Trivial conflict in: drivers/spi/pxa2xx_spi_pci.c

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

7 files changed, 41 insertions, 33 deletions

diff --git a/arch/microblaze/include/asm/irqflags.h b/arch/microblaze/include/asm/irqflags.h
index 5fd31905775d..c4532f032b3b 100644
--- a/arch/microblaze/include/asm/irqflags.h
+++ b/arch/microblaze/include/asm/irqflags.h
@@ -12,7 +12,7 @@
 #include <linux/types.h>
 #include <asm/registers.h>
 
-#ifdef CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
+#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
 
 static inline unsigned long arch_local_irq_save(void)
 {
diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h
index b23f68075879..885574a73f01 100644
--- a/arch/microblaze/include/asm/pgtable.h
+++ b/arch/microblaze/include/asm/pgtable.h
@@ -411,20 +411,19 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 static inline unsigned long pte_update(pte_t *p, unsigned long clr,
                                 unsigned long set)
 {
-        unsigned long old, tmp, msr;
-
-        __asm__ __volatile__("\
-        msrclr  %2, 0x2\n\
-        nop\n\
-        lw      %0, %4, r0\n\
-        andn    %1, %0, %5\n\
-        or      %1, %1, %6\n\
-        sw      %1, %4, r0\n\
-        mts     rmsr, %2\n\
-        nop"
-        : "=&r" (old), "=&r" (tmp), "=&r" (msr), "=m" (*p)
-        : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set), "m" (*p)
-        : "cc");
+        unsigned long flags, old, tmp;
+
+        raw_local_irq_save(flags);
+
+        __asm__ __volatile__(   "lw     %0, %2, r0      \n"
+                                "andn   %1, %0, %3      \n"
+                                "or     %1, %1, %4      \n"
+                                "sw     %1, %2, r0      \n"
+                        : "=&r" (old), "=&r" (tmp)
+                        : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set)
+                        : "cc");
+
+        raw_local_irq_restore(flags);
 
         return old;
 }
diff --git a/arch/microblaze/kernel/cpu/pvr.c b/arch/microblaze/kernel/cpu/pvr.c
index e01afa68273e..488c1ed24e38 100644
--- a/arch/microblaze/kernel/cpu/pvr.c
+++ b/arch/microblaze/kernel/cpu/pvr.c
@@ -27,7 +27,7 @@
         register unsigned tmp __asm__("r3");                    \
         tmp = 0x0;      /* Prevent warning about unused */      \
         __asm__ __volatile__ (                                  \
-                        "mfs    %0, rpvr" #pvrid ";"    \
+                        "mfs    %0, rpvr" #pvrid ";"            \
                         : "=r" (tmp) : : "memory");             \
         val = tmp;                                              \
 }
@@ -54,7 +54,7 @@ int cpu_has_pvr(void)
         if (!(flags & PVR_MSR_BIT))
                 return 0;
 
-        get_single_pvr(0x00, pvr0);
+        get_single_pvr(0, pvr0);
         pr_debug("%s: pvr0 is 0x%08x\n", __func__, pvr0);
 
         if (pvr0 & PVR0_PVR_FULL_MASK)
diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S
index 42434008209e..778a5ce2e4fc 100644
--- a/arch/microblaze/kernel/head.S
+++ b/arch/microblaze/kernel/head.S
@@ -62,23 +62,32 @@ real_start:
         andi    r1, r1, ~2
         mts     rmsr, r1
 /*
- * Here is checking mechanism which check if Microblaze has msr instructions
- * We load msr and compare it with previous r1 value - if is the same,
- * msr instructions works if not - cpu don't have them.
+ * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
+ * if the msrclr instruction is not enabled. We use this to detect
+ * if the opcode is available, by issuing msrclr and then testing the result.
+ * r8 == 0 - msr instructions are implemented
+ * r8 != 0 - msr instructions are not implemented
  */
-        /* r8=0 - I have msr instr, 1 - I don't have them */
-        rsubi   r0, r0, 1       /* set the carry bit */
-        msrclr  r0, 0x4         /* try to clear it */
-        /* read the carry bit, r8 will be '0' if msrclr exists */
-        addik   r8, r0, 0
+        msrclr  r8, 0 /* clear nothing - just read msr for test */
+        cmpu    r8, r8, r1 /* r1 must contain msr reg content */
 
 /* r7 may point to an FDT, or there may be one linked in.
    if it's in r7, we've got to save it away ASAP.
    We ensure r7 points to a valid FDT, just in case the bootloader
    is broken or non-existent */
         beqi    r7, no_fdt_arg                  /* NULL pointer?  don't copy */
-        lw      r11, r0, r7                     /* Does r7 point to a */
-        rsubi   r11, r11, OF_DT_HEADER          /* valid FDT? */
+/* Does r7 point to a valid FDT? Load HEADER magic number */
+        /* Run time Big/Little endian platform */
+        /* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */
+        addik   r11, r0, 0x1 /* BIG/LITTLE checking value */
+        /* __bss_start will be zeroed later - it is just temp location */
+        swi     r11, r0, TOPHYS(__bss_start)
+        lbui    r11, r0, TOPHYS(__bss_start)
+        beqid   r11, big_endian /* DO NOT break delay stop dependency */
+        lw      r11, r0, r7 /* Big endian load in delay slot */
+        lwr     r11, r0, r7 /* Little endian load */
+big_endian:
+        rsubi   r11, r11, OF_DT_HEADER  /* Check FDT header */
         beqi    r11, _prepare_copy_fdt
         or      r7, r0, r0              /* clear R7 when not valid DTB */
         bnei    r11, no_fdt_arg                 /* No - get out of here */
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index 25f6e07d8de8..782680de3121 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -147,10 +147,6 @@
         #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0
         #define BSRLI(rD, rA, imm)      \
                 bsrli rD, rA, imm
-        #elif CONFIG_XILINX_MICROBLAZE0_USE_DIV > 0
-        #define BSRLI(rD, rA, imm)      \
-                ori rD, r0, (1 << imm); \
-                idivu rD, rD, rA
         #else
         #define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA)
         /* Only the used shift constants defined here - add more if needed */
diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c
index bb1558e4b283..9312fbb37efd 100644
--- a/arch/microblaze/kernel/setup.c
+++ b/arch/microblaze/kernel/setup.c
@@ -161,11 +161,11 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
 #if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
         if (msr)
                 eprintk("!!!Your kernel has setup MSR instruction but "
-                                "CPU don't have it %d\n", msr);
+                                "CPU don't have it %x\n", msr);
 #else
         if (!msr)
                 eprintk("!!!Your kernel not setup MSR instruction but "
-                                "CPU have it %d\n", msr);
+                                "CPU have it %x\n", msr);
 #endif
 
         for (src = __ivt_start; src < __ivt_end; src++, dst++)
diff --git a/arch/microblaze/lib/fastcopy.S b/arch/microblaze/lib/fastcopy.S
index fdc48bb065d8..62021d7e249e 100644
--- a/arch/microblaze/lib/fastcopy.S
+++ b/arch/microblaze/lib/fastcopy.S
@@ -29,6 +29,10 @@
  *      between mem locations with size of xfer spec'd in bytes
  */
 
+#ifdef __MICROBLAZEEL__
+#error Microblaze LE not support ASM optimized lib func. Disable OPT_LIB_ASM.
+#endif
+
 #include <linux/linkage.h>
         .text
         .globl  memcpy