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authorAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
committerAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
commitada47b5fe13d89735805b566185f4885f5a3f750 (patch)
tree644b88f8a71896307d71438e9b3af49126ffb22b /arch/microblaze/pci
parent43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff)
parent3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff)
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'arch/microblaze/pci')
-rw-r--r--arch/microblaze/pci/Makefile6
-rw-r--r--arch/microblaze/pci/indirect_pci.c163
-rw-r--r--arch/microblaze/pci/iomap.c39
-rw-r--r--arch/microblaze/pci/pci-common.c1642
-rw-r--r--arch/microblaze/pci/pci_32.c431
-rw-r--r--arch/microblaze/pci/xilinx_pci.c168
6 files changed, 2449 insertions, 0 deletions
diff --git a/arch/microblaze/pci/Makefile b/arch/microblaze/pci/Makefile
new file mode 100644
index 000000000000..9889cc2e1294
--- /dev/null
+++ b/arch/microblaze/pci/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile
3#
4
5obj-$(CONFIG_PCI) += pci_32.o pci-common.o indirect_pci.o iomap.o
6obj-$(CONFIG_PCI_XILINX) += xilinx_pci.o
diff --git a/arch/microblaze/pci/indirect_pci.c b/arch/microblaze/pci/indirect_pci.c
new file mode 100644
index 000000000000..25f18f017f21
--- /dev/null
+++ b/arch/microblaze/pci/indirect_pci.c
@@ -0,0 +1,163 @@
1/*
2 * Support for indirect PCI bridges.
3 *
4 * Copyright (C) 1998 Gabriel Paubert.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/pci.h>
14#include <linux/delay.h>
15#include <linux/string.h>
16#include <linux/init.h>
17
18#include <asm/io.h>
19#include <asm/prom.h>
20#include <asm/pci-bridge.h>
21
22static int
23indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
24 int len, u32 *val)
25{
26 struct pci_controller *hose = pci_bus_to_host(bus);
27 volatile void __iomem *cfg_data;
28 u8 cfg_type = 0;
29 u32 bus_no, reg;
30
31 if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
32 if (bus->number != hose->first_busno)
33 return PCIBIOS_DEVICE_NOT_FOUND;
34 if (devfn != 0)
35 return PCIBIOS_DEVICE_NOT_FOUND;
36 }
37
38 if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE)
39 if (bus->number != hose->first_busno)
40 cfg_type = 1;
41
42 bus_no = (bus->number == hose->first_busno) ?
43 hose->self_busno : bus->number;
44
45 if (hose->indirect_type & INDIRECT_TYPE_EXT_REG)
46 reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
47 else
48 reg = offset & 0xfc; /* Only 3 bits for function */
49
50 if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
51 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
52 (devfn << 8) | reg | cfg_type));
53 else
54 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
55 (devfn << 8) | reg | cfg_type));
56
57 /*
58 * Note: the caller has already checked that offset is
59 * suitably aligned and that len is 1, 2 or 4.
60 */
61 cfg_data = hose->cfg_data + (offset & 3); /* Only 3 bits for function */
62 switch (len) {
63 case 1:
64 *val = in_8(cfg_data);
65 break;
66 case 2:
67 *val = in_le16(cfg_data);
68 break;
69 default:
70 *val = in_le32(cfg_data);
71 break;
72 }
73 return PCIBIOS_SUCCESSFUL;
74}
75
76static int
77indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
78 int len, u32 val)
79{
80 struct pci_controller *hose = pci_bus_to_host(bus);
81 volatile void __iomem *cfg_data;
82 u8 cfg_type = 0;
83 u32 bus_no, reg;
84
85 if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
86 if (bus->number != hose->first_busno)
87 return PCIBIOS_DEVICE_NOT_FOUND;
88 if (devfn != 0)
89 return PCIBIOS_DEVICE_NOT_FOUND;
90 }
91
92 if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE)
93 if (bus->number != hose->first_busno)
94 cfg_type = 1;
95
96 bus_no = (bus->number == hose->first_busno) ?
97 hose->self_busno : bus->number;
98
99 if (hose->indirect_type & INDIRECT_TYPE_EXT_REG)
100 reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
101 else
102 reg = offset & 0xfc;
103
104 if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
105 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
106 (devfn << 8) | reg | cfg_type));
107 else
108 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
109 (devfn << 8) | reg | cfg_type));
110
111 /* surpress setting of PCI_PRIMARY_BUS */
112 if (hose->indirect_type & INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
113 if ((offset == PCI_PRIMARY_BUS) &&
114 (bus->number == hose->first_busno))
115 val &= 0xffffff00;
116
117 /* Workaround for PCI_28 Errata in 440EPx/GRx */
118 if ((hose->indirect_type & INDIRECT_TYPE_BROKEN_MRM) &&
119 offset == PCI_CACHE_LINE_SIZE) {
120 val = 0;
121 }
122
123 /*
124 * Note: the caller has already checked that offset is
125 * suitably aligned and that len is 1, 2 or 4.
126 */
127 cfg_data = hose->cfg_data + (offset & 3);
128 switch (len) {
129 case 1:
130 out_8(cfg_data, val);
131 break;
132 case 2:
133 out_le16(cfg_data, val);
134 break;
135 default:
136 out_le32(cfg_data, val);
137 break;
138 }
139
140 return PCIBIOS_SUCCESSFUL;
141}
142
143static struct pci_ops indirect_pci_ops = {
144 .read = indirect_read_config,
145 .write = indirect_write_config,
146};
147
148void __init
149setup_indirect_pci(struct pci_controller *hose,
150 resource_size_t cfg_addr,
151 resource_size_t cfg_data, u32 flags)
152{
153 resource_size_t base = cfg_addr & PAGE_MASK;
154 void __iomem *mbase;
155
156 mbase = ioremap(base, PAGE_SIZE);
157 hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
158 if ((cfg_data & PAGE_MASK) != base)
159 mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
160 hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
161 hose->ops = &indirect_pci_ops;
162 hose->indirect_type = flags;
163}
diff --git a/arch/microblaze/pci/iomap.c b/arch/microblaze/pci/iomap.c
new file mode 100644
index 000000000000..3fbf16f4e16c
--- /dev/null
+++ b/arch/microblaze/pci/iomap.c
@@ -0,0 +1,39 @@
1/*
2 * ppc64 "iomap" interface implementation.
3 *
4 * (C) Copyright 2004 Linus Torvalds
5 */
6#include <linux/init.h>
7#include <linux/pci.h>
8#include <linux/mm.h>
9#include <asm/io.h>
10#include <asm/pci-bridge.h>
11
12void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
13{
14 resource_size_t start = pci_resource_start(dev, bar);
15 resource_size_t len = pci_resource_len(dev, bar);
16 unsigned long flags = pci_resource_flags(dev, bar);
17
18 if (!len)
19 return NULL;
20 if (max && len > max)
21 len = max;
22 if (flags & IORESOURCE_IO)
23 return ioport_map(start, len);
24 if (flags & IORESOURCE_MEM)
25 return ioremap(start, len);
26 /* What? */
27 return NULL;
28}
29EXPORT_SYMBOL(pci_iomap);
30
31void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
32{
33 if (isa_vaddr_is_ioport(addr))
34 return;
35 if (pcibios_vaddr_is_ioport(addr))
36 return;
37 iounmap(addr);
38}
39EXPORT_SYMBOL(pci_iounmap);
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
new file mode 100644
index 000000000000..9cb782b8e036
--- /dev/null
+++ b/arch/microblaze/pci/pci-common.c
@@ -0,0 +1,1642 @@
1/*
2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
4 *
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
7 *
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
10 *
11 * Common pmac/prep/chrp pci routines. -- Cort
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
24#include <linux/mm.h>
25#include <linux/list.h>
26#include <linux/syscalls.h>
27#include <linux/irq.h>
28#include <linux/vmalloc.h>
29#include <linux/slab.h>
30
31#include <asm/processor.h>
32#include <asm/io.h>
33#include <asm/prom.h>
34#include <asm/pci-bridge.h>
35#include <asm/byteorder.h>
36
37static DEFINE_SPINLOCK(hose_spinlock);
38LIST_HEAD(hose_list);
39
40/* XXX kill that some day ... */
41static int global_phb_number; /* Global phb counter */
42
43/* ISA Memory physical address */
44resource_size_t isa_mem_base;
45
46/* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
47unsigned int pci_flags;
48
49static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
50
51void set_pci_dma_ops(struct dma_map_ops *dma_ops)
52{
53 pci_dma_ops = dma_ops;
54}
55
56struct dma_map_ops *get_pci_dma_ops(void)
57{
58 return pci_dma_ops;
59}
60EXPORT_SYMBOL(get_pci_dma_ops);
61
62int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
63{
64 return dma_set_mask(&dev->dev, mask);
65}
66
67int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
68{
69 int rc;
70
71 rc = dma_set_mask(&dev->dev, mask);
72 dev->dev.coherent_dma_mask = dev->dma_mask;
73
74 return rc;
75}
76
77struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
78{
79 struct pci_controller *phb;
80
81 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
82 if (!phb)
83 return NULL;
84 spin_lock(&hose_spinlock);
85 phb->global_number = global_phb_number++;
86 list_add_tail(&phb->list_node, &hose_list);
87 spin_unlock(&hose_spinlock);
88 phb->dn = dev;
89 phb->is_dynamic = mem_init_done;
90 return phb;
91}
92
93void pcibios_free_controller(struct pci_controller *phb)
94{
95 spin_lock(&hose_spinlock);
96 list_del(&phb->list_node);
97 spin_unlock(&hose_spinlock);
98
99 if (phb->is_dynamic)
100 kfree(phb);
101}
102
103static resource_size_t pcibios_io_size(const struct pci_controller *hose)
104{
105 return hose->io_resource.end - hose->io_resource.start + 1;
106}
107
108int pcibios_vaddr_is_ioport(void __iomem *address)
109{
110 int ret = 0;
111 struct pci_controller *hose;
112 resource_size_t size;
113
114 spin_lock(&hose_spinlock);
115 list_for_each_entry(hose, &hose_list, list_node) {
116 size = pcibios_io_size(hose);
117 if (address >= hose->io_base_virt &&
118 address < (hose->io_base_virt + size)) {
119 ret = 1;
120 break;
121 }
122 }
123 spin_unlock(&hose_spinlock);
124 return ret;
125}
126
127unsigned long pci_address_to_pio(phys_addr_t address)
128{
129 struct pci_controller *hose;
130 resource_size_t size;
131 unsigned long ret = ~0;
132
133 spin_lock(&hose_spinlock);
134 list_for_each_entry(hose, &hose_list, list_node) {
135 size = pcibios_io_size(hose);
136 if (address >= hose->io_base_phys &&
137 address < (hose->io_base_phys + size)) {
138 unsigned long base =
139 (unsigned long)hose->io_base_virt - _IO_BASE;
140 ret = base + (address - hose->io_base_phys);
141 break;
142 }
143 }
144 spin_unlock(&hose_spinlock);
145
146 return ret;
147}
148EXPORT_SYMBOL_GPL(pci_address_to_pio);
149
150/*
151 * Return the domain number for this bus.
152 */
153int pci_domain_nr(struct pci_bus *bus)
154{
155 struct pci_controller *hose = pci_bus_to_host(bus);
156
157 return hose->global_number;
158}
159EXPORT_SYMBOL(pci_domain_nr);
160
161/* This routine is meant to be used early during boot, when the
162 * PCI bus numbers have not yet been assigned, and you need to
163 * issue PCI config cycles to an OF device.
164 * It could also be used to "fix" RTAS config cycles if you want
165 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
166 * config cycles.
167 */
168struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
169{
170 while (node) {
171 struct pci_controller *hose, *tmp;
172 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
173 if (hose->dn == node)
174 return hose;
175 node = node->parent;
176 }
177 return NULL;
178}
179
180static ssize_t pci_show_devspec(struct device *dev,
181 struct device_attribute *attr, char *buf)
182{
183 struct pci_dev *pdev;
184 struct device_node *np;
185
186 pdev = to_pci_dev(dev);
187 np = pci_device_to_OF_node(pdev);
188 if (np == NULL || np->full_name == NULL)
189 return 0;
190 return sprintf(buf, "%s", np->full_name);
191}
192static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
193
194/* Add sysfs properties */
195int pcibios_add_platform_entries(struct pci_dev *pdev)
196{
197 return device_create_file(&pdev->dev, &dev_attr_devspec);
198}
199
200char __devinit *pcibios_setup(char *str)
201{
202 return str;
203}
204
205/*
206 * Reads the interrupt pin to determine if interrupt is use by card.
207 * If the interrupt is used, then gets the interrupt line from the
208 * openfirmware and sets it in the pci_dev and pci_config line.
209 */
210int pci_read_irq_line(struct pci_dev *pci_dev)
211{
212 struct of_irq oirq;
213 unsigned int virq;
214
215 /* The current device-tree that iSeries generates from the HV
216 * PCI informations doesn't contain proper interrupt routing,
217 * and all the fallback would do is print out crap, so we
218 * don't attempt to resolve the interrupts here at all, some
219 * iSeries specific fixup does it.
220 *
221 * In the long run, we will hopefully fix the generated device-tree
222 * instead.
223 */
224 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
225
226#ifdef DEBUG
227 memset(&oirq, 0xff, sizeof(oirq));
228#endif
229 /* Try to get a mapping from the device-tree */
230 if (of_irq_map_pci(pci_dev, &oirq)) {
231 u8 line, pin;
232
233 /* If that fails, lets fallback to what is in the config
234 * space and map that through the default controller. We
235 * also set the type to level low since that's what PCI
236 * interrupts are. If your platform does differently, then
237 * either provide a proper interrupt tree or don't use this
238 * function.
239 */
240 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
241 return -1;
242 if (pin == 0)
243 return -1;
244 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
245 line == 0xff || line == 0) {
246 return -1;
247 }
248 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
249 line, pin);
250
251 virq = irq_create_mapping(NULL, line);
252 if (virq != NO_IRQ)
253 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
254 } else {
255 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
256 oirq.size, oirq.specifier[0], oirq.specifier[1],
257 oirq.controller ? oirq.controller->full_name :
258 "<default>");
259
260 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
261 oirq.size);
262 }
263 if (virq == NO_IRQ) {
264 pr_debug(" Failed to map !\n");
265 return -1;
266 }
267
268 pr_debug(" Mapped to linux irq %d\n", virq);
269
270 pci_dev->irq = virq;
271
272 return 0;
273}
274EXPORT_SYMBOL(pci_read_irq_line);
275
276/*
277 * Platform support for /proc/bus/pci/X/Y mmap()s,
278 * modelled on the sparc64 implementation by Dave Miller.
279 * -- paulus.
280 */
281
282/*
283 * Adjust vm_pgoff of VMA such that it is the physical page offset
284 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
285 *
286 * Basically, the user finds the base address for his device which he wishes
287 * to mmap. They read the 32-bit value from the config space base register,
288 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
289 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
290 *
291 * Returns negative error code on failure, zero on success.
292 */
293static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
294 resource_size_t *offset,
295 enum pci_mmap_state mmap_state)
296{
297 struct pci_controller *hose = pci_bus_to_host(dev->bus);
298 unsigned long io_offset = 0;
299 int i, res_bit;
300
301 if (hose == 0)
302 return NULL; /* should never happen */
303
304 /* If memory, add on the PCI bridge address offset */
305 if (mmap_state == pci_mmap_mem) {
306#if 0 /* See comment in pci_resource_to_user() for why this is disabled */
307 *offset += hose->pci_mem_offset;
308#endif
309 res_bit = IORESOURCE_MEM;
310 } else {
311 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
312 *offset += io_offset;
313 res_bit = IORESOURCE_IO;
314 }
315
316 /*
317 * Check that the offset requested corresponds to one of the
318 * resources of the device.
319 */
320 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
321 struct resource *rp = &dev->resource[i];
322 int flags = rp->flags;
323
324 /* treat ROM as memory (should be already) */
325 if (i == PCI_ROM_RESOURCE)
326 flags |= IORESOURCE_MEM;
327
328 /* Active and same type? */
329 if ((flags & res_bit) == 0)
330 continue;
331
332 /* In the range of this resource? */
333 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
334 continue;
335
336 /* found it! construct the final physical address */
337 if (mmap_state == pci_mmap_io)
338 *offset += hose->io_base_phys - io_offset;
339 return rp;
340 }
341
342 return NULL;
343}
344
345/*
346 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
347 * device mapping.
348 */
349static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
350 pgprot_t protection,
351 enum pci_mmap_state mmap_state,
352 int write_combine)
353{
354 pgprot_t prot = protection;
355
356 /* Write combine is always 0 on non-memory space mappings. On
357 * memory space, if the user didn't pass 1, we check for a
358 * "prefetchable" resource. This is a bit hackish, but we use
359 * this to workaround the inability of /sysfs to provide a write
360 * combine bit
361 */
362 if (mmap_state != pci_mmap_mem)
363 write_combine = 0;
364 else if (write_combine == 0) {
365 if (rp->flags & IORESOURCE_PREFETCH)
366 write_combine = 1;
367 }
368
369 return pgprot_noncached(prot);
370}
371
372/*
373 * This one is used by /dev/mem and fbdev who have no clue about the
374 * PCI device, it tries to find the PCI device first and calls the
375 * above routine
376 */
377pgprot_t pci_phys_mem_access_prot(struct file *file,
378 unsigned long pfn,
379 unsigned long size,
380 pgprot_t prot)
381{
382 struct pci_dev *pdev = NULL;
383 struct resource *found = NULL;
384 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
385 int i;
386
387 if (page_is_ram(pfn))
388 return prot;
389
390 prot = pgprot_noncached(prot);
391 for_each_pci_dev(pdev) {
392 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
393 struct resource *rp = &pdev->resource[i];
394 int flags = rp->flags;
395
396 /* Active and same type? */
397 if ((flags & IORESOURCE_MEM) == 0)
398 continue;
399 /* In the range of this resource? */
400 if (offset < (rp->start & PAGE_MASK) ||
401 offset > rp->end)
402 continue;
403 found = rp;
404 break;
405 }
406 if (found)
407 break;
408 }
409 if (found) {
410 if (found->flags & IORESOURCE_PREFETCH)
411 prot = pgprot_noncached_wc(prot);
412 pci_dev_put(pdev);
413 }
414
415 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
416 (unsigned long long)offset, pgprot_val(prot));
417
418 return prot;
419}
420
421/*
422 * Perform the actual remap of the pages for a PCI device mapping, as
423 * appropriate for this architecture. The region in the process to map
424 * is described by vm_start and vm_end members of VMA, the base physical
425 * address is found in vm_pgoff.
426 * The pci device structure is provided so that architectures may make mapping
427 * decisions on a per-device or per-bus basis.
428 *
429 * Returns a negative error code on failure, zero on success.
430 */
431int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
432 enum pci_mmap_state mmap_state, int write_combine)
433{
434 resource_size_t offset =
435 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
436 struct resource *rp;
437 int ret;
438
439 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
440 if (rp == NULL)
441 return -EINVAL;
442
443 vma->vm_pgoff = offset >> PAGE_SHIFT;
444 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
445 vma->vm_page_prot,
446 mmap_state, write_combine);
447
448 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
449 vma->vm_end - vma->vm_start, vma->vm_page_prot);
450
451 return ret;
452}
453
454/* This provides legacy IO read access on a bus */
455int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
456{
457 unsigned long offset;
458 struct pci_controller *hose = pci_bus_to_host(bus);
459 struct resource *rp = &hose->io_resource;
460 void __iomem *addr;
461
462 /* Check if port can be supported by that bus. We only check
463 * the ranges of the PHB though, not the bus itself as the rules
464 * for forwarding legacy cycles down bridges are not our problem
465 * here. So if the host bridge supports it, we do it.
466 */
467 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
468 offset += port;
469
470 if (!(rp->flags & IORESOURCE_IO))
471 return -ENXIO;
472 if (offset < rp->start || (offset + size) > rp->end)
473 return -ENXIO;
474 addr = hose->io_base_virt + port;
475
476 switch (size) {
477 case 1:
478 *((u8 *)val) = in_8(addr);
479 return 1;
480 case 2:
481 if (port & 1)
482 return -EINVAL;
483 *((u16 *)val) = in_le16(addr);
484 return 2;
485 case 4:
486 if (port & 3)
487 return -EINVAL;
488 *((u32 *)val) = in_le32(addr);
489 return 4;
490 }
491 return -EINVAL;
492}
493
494/* This provides legacy IO write access on a bus */
495int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
496{
497 unsigned long offset;
498 struct pci_controller *hose = pci_bus_to_host(bus);
499 struct resource *rp = &hose->io_resource;
500 void __iomem *addr;
501
502 /* Check if port can be supported by that bus. We only check
503 * the ranges of the PHB though, not the bus itself as the rules
504 * for forwarding legacy cycles down bridges are not our problem
505 * here. So if the host bridge supports it, we do it.
506 */
507 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
508 offset += port;
509
510 if (!(rp->flags & IORESOURCE_IO))
511 return -ENXIO;
512 if (offset < rp->start || (offset + size) > rp->end)
513 return -ENXIO;
514 addr = hose->io_base_virt + port;
515
516 /* WARNING: The generic code is idiotic. It gets passed a pointer
517 * to what can be a 1, 2 or 4 byte quantity and always reads that
518 * as a u32, which means that we have to correct the location of
519 * the data read within those 32 bits for size 1 and 2
520 */
521 switch (size) {
522 case 1:
523 out_8(addr, val >> 24);
524 return 1;
525 case 2:
526 if (port & 1)
527 return -EINVAL;
528 out_le16(addr, val >> 16);
529 return 2;
530 case 4:
531 if (port & 3)
532 return -EINVAL;
533 out_le32(addr, val);
534 return 4;
535 }
536 return -EINVAL;
537}
538
539/* This provides legacy IO or memory mmap access on a bus */
540int pci_mmap_legacy_page_range(struct pci_bus *bus,
541 struct vm_area_struct *vma,
542 enum pci_mmap_state mmap_state)
543{
544 struct pci_controller *hose = pci_bus_to_host(bus);
545 resource_size_t offset =
546 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
547 resource_size_t size = vma->vm_end - vma->vm_start;
548 struct resource *rp;
549
550 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
551 pci_domain_nr(bus), bus->number,
552 mmap_state == pci_mmap_mem ? "MEM" : "IO",
553 (unsigned long long)offset,
554 (unsigned long long)(offset + size - 1));
555
556 if (mmap_state == pci_mmap_mem) {
557 /* Hack alert !
558 *
559 * Because X is lame and can fail starting if it gets an error
560 * trying to mmap legacy_mem (instead of just moving on without
561 * legacy memory access) we fake it here by giving it anonymous
562 * memory, effectively behaving just like /dev/zero
563 */
564 if ((offset + size) > hose->isa_mem_size) {
565#ifdef CONFIG_MMU
566 printk(KERN_DEBUG
567 "Process %s (pid:%d) mapped non-existing PCI"
568 "legacy memory for 0%04x:%02x\n",
569 current->comm, current->pid, pci_domain_nr(bus),
570 bus->number);
571#endif
572 if (vma->vm_flags & VM_SHARED)
573 return shmem_zero_setup(vma);
574 return 0;
575 }
576 offset += hose->isa_mem_phys;
577 } else {
578 unsigned long io_offset = (unsigned long)hose->io_base_virt - \
579 _IO_BASE;
580 unsigned long roffset = offset + io_offset;
581 rp = &hose->io_resource;
582 if (!(rp->flags & IORESOURCE_IO))
583 return -ENXIO;
584 if (roffset < rp->start || (roffset + size) > rp->end)
585 return -ENXIO;
586 offset += hose->io_base_phys;
587 }
588 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
589
590 vma->vm_pgoff = offset >> PAGE_SHIFT;
591 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
592 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
593 vma->vm_end - vma->vm_start,
594 vma->vm_page_prot);
595}
596
597void pci_resource_to_user(const struct pci_dev *dev, int bar,
598 const struct resource *rsrc,
599 resource_size_t *start, resource_size_t *end)
600{
601 struct pci_controller *hose = pci_bus_to_host(dev->bus);
602 resource_size_t offset = 0;
603
604 if (hose == NULL)
605 return;
606
607 if (rsrc->flags & IORESOURCE_IO)
608 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
609
610 /* We pass a fully fixed up address to userland for MMIO instead of
611 * a BAR value because X is lame and expects to be able to use that
612 * to pass to /dev/mem !
613 *
614 * That means that we'll have potentially 64 bits values where some
615 * userland apps only expect 32 (like X itself since it thinks only
616 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
617 * 32 bits CHRPs :-(
618 *
619 * Hopefully, the sysfs insterface is immune to that gunk. Once X
620 * has been fixed (and the fix spread enough), we can re-enable the
621 * 2 lines below and pass down a BAR value to userland. In that case
622 * we'll also have to re-enable the matching code in
623 * __pci_mmap_make_offset().
624 *
625 * BenH.
626 */
627#if 0
628 else if (rsrc->flags & IORESOURCE_MEM)
629 offset = hose->pci_mem_offset;
630#endif
631
632 *start = rsrc->start - offset;
633 *end = rsrc->end - offset;
634}
635
636/**
637 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
638 * @hose: newly allocated pci_controller to be setup
639 * @dev: device node of the host bridge
640 * @primary: set if primary bus (32 bits only, soon to be deprecated)
641 *
642 * This function will parse the "ranges" property of a PCI host bridge device
643 * node and setup the resource mapping of a pci controller based on its
644 * content.
645 *
646 * Life would be boring if it wasn't for a few issues that we have to deal
647 * with here:
648 *
649 * - We can only cope with one IO space range and up to 3 Memory space
650 * ranges. However, some machines (thanks Apple !) tend to split their
651 * space into lots of small contiguous ranges. So we have to coalesce.
652 *
653 * - We can only cope with all memory ranges having the same offset
654 * between CPU addresses and PCI addresses. Unfortunately, some bridges
655 * are setup for a large 1:1 mapping along with a small "window" which
656 * maps PCI address 0 to some arbitrary high address of the CPU space in
657 * order to give access to the ISA memory hole.
658 * The way out of here that I've chosen for now is to always set the
659 * offset based on the first resource found, then override it if we
660 * have a different offset and the previous was set by an ISA hole.
661 *
662 * - Some busses have IO space not starting at 0, which causes trouble with
663 * the way we do our IO resource renumbering. The code somewhat deals with
664 * it for 64 bits but I would expect problems on 32 bits.
665 *
666 * - Some 32 bits platforms such as 4xx can have physical space larger than
667 * 32 bits so we need to use 64 bits values for the parsing
668 */
669void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
670 struct device_node *dev,
671 int primary)
672{
673 const u32 *ranges;
674 int rlen;
675 int pna = of_n_addr_cells(dev);
676 int np = pna + 5;
677 int memno = 0, isa_hole = -1;
678 u32 pci_space;
679 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
680 unsigned long long isa_mb = 0;
681 struct resource *res;
682
683 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
684 dev->full_name, primary ? "(primary)" : "");
685
686 /* Get ranges property */
687 ranges = of_get_property(dev, "ranges", &rlen);
688 if (ranges == NULL)
689 return;
690
691 /* Parse it */
692 pr_debug("Parsing ranges property...\n");
693 while ((rlen -= np * 4) >= 0) {
694 /* Read next ranges element */
695 pci_space = ranges[0];
696 pci_addr = of_read_number(ranges + 1, 2);
697 cpu_addr = of_translate_address(dev, ranges + 3);
698 size = of_read_number(ranges + pna + 3, 2);
699
700 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx "
701 "cpu_addr:0x%016llx size:0x%016llx\n",
702 pci_space, pci_addr, cpu_addr, size);
703
704 ranges += np;
705
706 /* If we failed translation or got a zero-sized region
707 * (some FW try to feed us with non sensical zero sized regions
708 * such as power3 which look like some kind of attempt
709 * at exposing the VGA memory hole)
710 */
711 if (cpu_addr == OF_BAD_ADDR || size == 0)
712 continue;
713
714 /* Now consume following elements while they are contiguous */
715 for (; rlen >= np * sizeof(u32);
716 ranges += np, rlen -= np * 4) {
717 if (ranges[0] != pci_space)
718 break;
719 pci_next = of_read_number(ranges + 1, 2);
720 cpu_next = of_translate_address(dev, ranges + 3);
721 if (pci_next != pci_addr + size ||
722 cpu_next != cpu_addr + size)
723 break;
724 size += of_read_number(ranges + pna + 3, 2);
725 }
726
727 /* Act based on address space type */
728 res = NULL;
729 switch ((pci_space >> 24) & 0x3) {
730 case 1: /* PCI IO space */
731 printk(KERN_INFO
732 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
733 cpu_addr, cpu_addr + size - 1, pci_addr);
734
735 /* We support only one IO range */
736 if (hose->pci_io_size) {
737 printk(KERN_INFO
738 " \\--> Skipped (too many) !\n");
739 continue;
740 }
741 /* On 32 bits, limit I/O space to 16MB */
742 if (size > 0x01000000)
743 size = 0x01000000;
744
745 /* 32 bits needs to map IOs here */
746 hose->io_base_virt = ioremap(cpu_addr, size);
747
748 /* Expect trouble if pci_addr is not 0 */
749 if (primary)
750 isa_io_base =
751 (unsigned long)hose->io_base_virt;
752 /* pci_io_size and io_base_phys always represent IO
753 * space starting at 0 so we factor in pci_addr
754 */
755 hose->pci_io_size = pci_addr + size;
756 hose->io_base_phys = cpu_addr - pci_addr;
757
758 /* Build resource */
759 res = &hose->io_resource;
760 res->flags = IORESOURCE_IO;
761 res->start = pci_addr;
762 break;
763 case 2: /* PCI Memory space */
764 case 3: /* PCI 64 bits Memory space */
765 printk(KERN_INFO
766 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
767 cpu_addr, cpu_addr + size - 1, pci_addr,
768 (pci_space & 0x40000000) ? "Prefetch" : "");
769
770 /* We support only 3 memory ranges */
771 if (memno >= 3) {
772 printk(KERN_INFO
773 " \\--> Skipped (too many) !\n");
774 continue;
775 }
776 /* Handles ISA memory hole space here */
777 if (pci_addr == 0) {
778 isa_mb = cpu_addr;
779 isa_hole = memno;
780 if (primary || isa_mem_base == 0)
781 isa_mem_base = cpu_addr;
782 hose->isa_mem_phys = cpu_addr;
783 hose->isa_mem_size = size;
784 }
785
786 /* We get the PCI/Mem offset from the first range or
787 * the, current one if the offset came from an ISA
788 * hole. If they don't match, bugger.
789 */
790 if (memno == 0 ||
791 (isa_hole >= 0 && pci_addr != 0 &&
792 hose->pci_mem_offset == isa_mb))
793 hose->pci_mem_offset = cpu_addr - pci_addr;
794 else if (pci_addr != 0 &&
795 hose->pci_mem_offset != cpu_addr - pci_addr) {
796 printk(KERN_INFO
797 " \\--> Skipped (offset mismatch) !\n");
798 continue;
799 }
800
801 /* Build resource */
802 res = &hose->mem_resources[memno++];
803 res->flags = IORESOURCE_MEM;
804 if (pci_space & 0x40000000)
805 res->flags |= IORESOURCE_PREFETCH;
806 res->start = cpu_addr;
807 break;
808 }
809 if (res != NULL) {
810 res->name = dev->full_name;
811 res->end = res->start + size - 1;
812 res->parent = NULL;
813 res->sibling = NULL;
814 res->child = NULL;
815 }
816 }
817
818 /* If there's an ISA hole and the pci_mem_offset is -not- matching
819 * the ISA hole offset, then we need to remove the ISA hole from
820 * the resource list for that brige
821 */
822 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
823 unsigned int next = isa_hole + 1;
824 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb);
825 if (next < memno)
826 memmove(&hose->mem_resources[isa_hole],
827 &hose->mem_resources[next],
828 sizeof(struct resource) * (memno - next));
829 hose->mem_resources[--memno].flags = 0;
830 }
831}
832
833/* Decide whether to display the domain number in /proc */
834int pci_proc_domain(struct pci_bus *bus)
835{
836 struct pci_controller *hose = pci_bus_to_host(bus);
837
838 if (!(pci_flags & PCI_ENABLE_PROC_DOMAINS))
839 return 0;
840 if (pci_flags & PCI_COMPAT_DOMAIN_0)
841 return hose->global_number != 0;
842 return 1;
843}
844
845void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
846 struct resource *res)
847{
848 resource_size_t offset = 0, mask = (resource_size_t)-1;
849 struct pci_controller *hose = pci_bus_to_host(dev->bus);
850
851 if (!hose)
852 return;
853 if (res->flags & IORESOURCE_IO) {
854 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
855 mask = 0xffffffffu;
856 } else if (res->flags & IORESOURCE_MEM)
857 offset = hose->pci_mem_offset;
858
859 region->start = (res->start - offset) & mask;
860 region->end = (res->end - offset) & mask;
861}
862EXPORT_SYMBOL(pcibios_resource_to_bus);
863
864void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
865 struct pci_bus_region *region)
866{
867 resource_size_t offset = 0, mask = (resource_size_t)-1;
868 struct pci_controller *hose = pci_bus_to_host(dev->bus);
869
870 if (!hose)
871 return;
872 if (res->flags & IORESOURCE_IO) {
873 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
874 mask = 0xffffffffu;
875 } else if (res->flags & IORESOURCE_MEM)
876 offset = hose->pci_mem_offset;
877 res->start = (region->start + offset) & mask;
878 res->end = (region->end + offset) & mask;
879}
880EXPORT_SYMBOL(pcibios_bus_to_resource);
881
882/* Fixup a bus resource into a linux resource */
883static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
884{
885 struct pci_controller *hose = pci_bus_to_host(dev->bus);
886 resource_size_t offset = 0, mask = (resource_size_t)-1;
887
888 if (res->flags & IORESOURCE_IO) {
889 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
890 mask = 0xffffffffu;
891 } else if (res->flags & IORESOURCE_MEM)
892 offset = hose->pci_mem_offset;
893
894 res->start = (res->start + offset) & mask;
895 res->end = (res->end + offset) & mask;
896}
897
898/* This header fixup will do the resource fixup for all devices as they are
899 * probed, but not for bridge ranges
900 */
901static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
902{
903 struct pci_controller *hose = pci_bus_to_host(dev->bus);
904 int i;
905
906 if (!hose) {
907 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
908 pci_name(dev));
909 return;
910 }
911 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
912 struct resource *res = dev->resource + i;
913 if (!res->flags)
914 continue;
915 /* On platforms that have PCI_PROBE_ONLY set, we don't
916 * consider 0 as an unassigned BAR value. It's technically
917 * a valid value, but linux doesn't like it... so when we can
918 * re-assign things, we do so, but if we can't, we keep it
919 * around and hope for the best...
920 */
921 if (res->start == 0 && !(pci_flags & PCI_PROBE_ONLY)) {
922 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]" \
923 "is unassigned\n",
924 pci_name(dev), i,
925 (unsigned long long)res->start,
926 (unsigned long long)res->end,
927 (unsigned int)res->flags);
928 res->end -= res->start;
929 res->start = 0;
930 res->flags |= IORESOURCE_UNSET;
931 continue;
932 }
933
934 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
935 pci_name(dev), i,
936 (unsigned long long)res->start,\
937 (unsigned long long)res->end,
938 (unsigned int)res->flags);
939
940 fixup_resource(res, dev);
941
942 pr_debug("PCI:%s %016llx-%016llx\n",
943 pci_name(dev),
944 (unsigned long long)res->start,
945 (unsigned long long)res->end);
946 }
947}
948DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
949
950/* This function tries to figure out if a bridge resource has been initialized
951 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
952 * things go more smoothly when it gets it right. It should covers cases such
953 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
954 */
955static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
956 struct resource *res)
957{
958 struct pci_controller *hose = pci_bus_to_host(bus);
959 struct pci_dev *dev = bus->self;
960 resource_size_t offset;
961 u16 command;
962 int i;
963
964 /* We don't do anything if PCI_PROBE_ONLY is set */
965 if (pci_flags & PCI_PROBE_ONLY)
966 return 0;
967
968 /* Job is a bit different between memory and IO */
969 if (res->flags & IORESOURCE_MEM) {
970 /* If the BAR is non-0 (res != pci_mem_offset) then it's
971 * probably been initialized by somebody
972 */
973 if (res->start != hose->pci_mem_offset)
974 return 0;
975
976 /* The BAR is 0, let's check if memory decoding is enabled on
977 * the bridge. If not, we consider it unassigned
978 */
979 pci_read_config_word(dev, PCI_COMMAND, &command);
980 if ((command & PCI_COMMAND_MEMORY) == 0)
981 return 1;
982
983 /* Memory decoding is enabled and the BAR is 0. If any of
984 * the bridge resources covers that starting address (0 then
985 * it's good enough for us for memory
986 */
987 for (i = 0; i < 3; i++) {
988 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
989 hose->mem_resources[i].start == hose->pci_mem_offset)
990 return 0;
991 }
992
993 /* Well, it starts at 0 and we know it will collide so we may as
994 * well consider it as unassigned. That covers the Apple case.
995 */
996 return 1;
997 } else {
998 /* If the BAR is non-0, then we consider it assigned */
999 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1000 if (((res->start - offset) & 0xfffffffful) != 0)
1001 return 0;
1002
1003 /* Here, we are a bit different than memory as typically IO
1004 * space starting at low addresses -is- valid. What we do
1005 * instead if that we consider as unassigned anything that
1006 * doesn't have IO enabled in the PCI command register,
1007 * and that's it.
1008 */
1009 pci_read_config_word(dev, PCI_COMMAND, &command);
1010 if (command & PCI_COMMAND_IO)
1011 return 0;
1012
1013 /* It's starting at 0 and IO is disabled in the bridge, consider
1014 * it unassigned
1015 */
1016 return 1;
1017 }
1018}
1019
1020/* Fixup resources of a PCI<->PCI bridge */
1021static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
1022{
1023 struct resource *res;
1024 int i;
1025
1026 struct pci_dev *dev = bus->self;
1027
1028 pci_bus_for_each_resource(bus, res, i) {
1029 res = bus->resource[i];
1030 if (!res)
1031 continue;
1032 if (!res->flags)
1033 continue;
1034 if (i >= 3 && bus->self->transparent)
1035 continue;
1036
1037 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1038 pci_name(dev), i,
1039 (unsigned long long)res->start,\
1040 (unsigned long long)res->end,
1041 (unsigned int)res->flags);
1042
1043 /* Perform fixup */
1044 fixup_resource(res, dev);
1045
1046 /* Try to detect uninitialized P2P bridge resources,
1047 * and clear them out so they get re-assigned later
1048 */
1049 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1050 res->flags = 0;
1051 pr_debug("PCI:%s (unassigned)\n",
1052 pci_name(dev));
1053 } else {
1054 pr_debug("PCI:%s %016llx-%016llx\n",
1055 pci_name(dev),
1056 (unsigned long long)res->start,
1057 (unsigned long long)res->end);
1058 }
1059 }
1060}
1061
1062void __devinit pcibios_setup_bus_self(struct pci_bus *bus)
1063{
1064 /* Fix up the bus resources for P2P bridges */
1065 if (bus->self != NULL)
1066 pcibios_fixup_bridge(bus);
1067}
1068
1069void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
1070{
1071 struct pci_dev *dev;
1072
1073 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1074 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1075
1076 list_for_each_entry(dev, &bus->devices, bus_list) {
1077 struct dev_archdata *sd = &dev->dev.archdata;
1078
1079 /* Setup OF node pointer in archdata */
1080 sd->of_node = pci_device_to_OF_node(dev);
1081
1082 /* Fixup NUMA node as it may not be setup yet by the generic
1083 * code and is needed by the DMA init
1084 */
1085 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1086
1087 /* Hook up default DMA ops */
1088 sd->dma_ops = pci_dma_ops;
1089 sd->dma_data = (void *)PCI_DRAM_OFFSET;
1090
1091 /* Read default IRQs and fixup if necessary */
1092 pci_read_irq_line(dev);
1093 }
1094}
1095
1096void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1097{
1098 /* When called from the generic PCI probe, read PCI<->PCI bridge
1099 * bases. This is -not- called when generating the PCI tree from
1100 * the OF device-tree.
1101 */
1102 if (bus->self != NULL)
1103 pci_read_bridge_bases(bus);
1104
1105 /* Now fixup the bus bus */
1106 pcibios_setup_bus_self(bus);
1107
1108 /* Now fixup devices on that bus */
1109 pcibios_setup_bus_devices(bus);
1110}
1111EXPORT_SYMBOL(pcibios_fixup_bus);
1112
1113static int skip_isa_ioresource_align(struct pci_dev *dev)
1114{
1115 if ((pci_flags & PCI_CAN_SKIP_ISA_ALIGN) &&
1116 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1117 return 1;
1118 return 0;
1119}
1120
1121/*
1122 * We need to avoid collisions with `mirrored' VGA ports
1123 * and other strange ISA hardware, so we always want the
1124 * addresses to be allocated in the 0x000-0x0ff region
1125 * modulo 0x400.
1126 *
1127 * Why? Because some silly external IO cards only decode
1128 * the low 10 bits of the IO address. The 0x00-0xff region
1129 * is reserved for motherboard devices that decode all 16
1130 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1131 * but we want to try to avoid allocating at 0x2900-0x2bff
1132 * which might have be mirrored at 0x0100-0x03ff..
1133 */
1134resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1135 resource_size_t size, resource_size_t align)
1136{
1137 struct pci_dev *dev = data;
1138 resource_size_t start = res->start;
1139
1140 if (res->flags & IORESOURCE_IO) {
1141 if (skip_isa_ioresource_align(dev))
1142 return start;
1143 if (start & 0x300)
1144 start = (start + 0x3ff) & ~0x3ff;
1145 }
1146
1147 return start;
1148}
1149EXPORT_SYMBOL(pcibios_align_resource);
1150
1151/*
1152 * Reparent resource children of pr that conflict with res
1153 * under res, and make res replace those children.
1154 */
1155static int __init reparent_resources(struct resource *parent,
1156 struct resource *res)
1157{
1158 struct resource *p, **pp;
1159 struct resource **firstpp = NULL;
1160
1161 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1162 if (p->end < res->start)
1163 continue;
1164 if (res->end < p->start)
1165 break;
1166 if (p->start < res->start || p->end > res->end)
1167 return -1; /* not completely contained */
1168 if (firstpp == NULL)
1169 firstpp = pp;
1170 }
1171 if (firstpp == NULL)
1172 return -1; /* didn't find any conflicting entries? */
1173 res->parent = parent;
1174 res->child = *firstpp;
1175 res->sibling = *pp;
1176 *firstpp = res;
1177 *pp = NULL;
1178 for (p = res->child; p != NULL; p = p->sibling) {
1179 p->parent = res;
1180 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1181 p->name,
1182 (unsigned long long)p->start,
1183 (unsigned long long)p->end, res->name);
1184 }
1185 return 0;
1186}
1187
1188/*
1189 * Handle resources of PCI devices. If the world were perfect, we could
1190 * just allocate all the resource regions and do nothing more. It isn't.
1191 * On the other hand, we cannot just re-allocate all devices, as it would
1192 * require us to know lots of host bridge internals. So we attempt to
1193 * keep as much of the original configuration as possible, but tweak it
1194 * when it's found to be wrong.
1195 *
1196 * Known BIOS problems we have to work around:
1197 * - I/O or memory regions not configured
1198 * - regions configured, but not enabled in the command register
1199 * - bogus I/O addresses above 64K used
1200 * - expansion ROMs left enabled (this may sound harmless, but given
1201 * the fact the PCI specs explicitly allow address decoders to be
1202 * shared between expansion ROMs and other resource regions, it's
1203 * at least dangerous)
1204 *
1205 * Our solution:
1206 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1207 * This gives us fixed barriers on where we can allocate.
1208 * (2) Allocate resources for all enabled devices. If there is
1209 * a collision, just mark the resource as unallocated. Also
1210 * disable expansion ROMs during this step.
1211 * (3) Try to allocate resources for disabled devices. If the
1212 * resources were assigned correctly, everything goes well,
1213 * if they weren't, they won't disturb allocation of other
1214 * resources.
1215 * (4) Assign new addresses to resources which were either
1216 * not configured at all or misconfigured. If explicitly
1217 * requested by the user, configure expansion ROM address
1218 * as well.
1219 */
1220
1221void pcibios_allocate_bus_resources(struct pci_bus *bus)
1222{
1223 struct pci_bus *b;
1224 int i;
1225 struct resource *res, *pr;
1226
1227 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1228 pci_domain_nr(bus), bus->number);
1229
1230 pci_bus_for_each_resource(bus, res, i) {
1231 res = bus->resource[i];
1232 if (!res || !res->flags
1233 || res->start > res->end || res->parent)
1234 continue;
1235 if (bus->parent == NULL)
1236 pr = (res->flags & IORESOURCE_IO) ?
1237 &ioport_resource : &iomem_resource;
1238 else {
1239 /* Don't bother with non-root busses when
1240 * re-assigning all resources. We clear the
1241 * resource flags as if they were colliding
1242 * and as such ensure proper re-allocation
1243 * later.
1244 */
1245 if (pci_flags & PCI_REASSIGN_ALL_RSRC)
1246 goto clear_resource;
1247 pr = pci_find_parent_resource(bus->self, res);
1248 if (pr == res) {
1249 /* this happens when the generic PCI
1250 * code (wrongly) decides that this
1251 * bridge is transparent -- paulus
1252 */
1253 continue;
1254 }
1255 }
1256
1257 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1258 "[0x%x], parent %p (%s)\n",
1259 bus->self ? pci_name(bus->self) : "PHB",
1260 bus->number, i,
1261 (unsigned long long)res->start,
1262 (unsigned long long)res->end,
1263 (unsigned int)res->flags,
1264 pr, (pr && pr->name) ? pr->name : "nil");
1265
1266 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1267 if (request_resource(pr, res) == 0)
1268 continue;
1269 /*
1270 * Must be a conflict with an existing entry.
1271 * Move that entry (or entries) under the
1272 * bridge resource and try again.
1273 */
1274 if (reparent_resources(pr, res) == 0)
1275 continue;
1276 }
1277 printk(KERN_WARNING "PCI: Cannot allocate resource region "
1278 "%d of PCI bridge %d, will remap\n", i, bus->number);
1279clear_resource:
1280 res->flags = 0;
1281 }
1282
1283 list_for_each_entry(b, &bus->children, node)
1284 pcibios_allocate_bus_resources(b);
1285}
1286
1287static inline void __devinit alloc_resource(struct pci_dev *dev, int idx)
1288{
1289 struct resource *pr, *r = &dev->resource[idx];
1290
1291 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1292 pci_name(dev), idx,
1293 (unsigned long long)r->start,
1294 (unsigned long long)r->end,
1295 (unsigned int)r->flags);
1296
1297 pr = pci_find_parent_resource(dev, r);
1298 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1299 request_resource(pr, r) < 0) {
1300 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1301 " of device %s, will remap\n", idx, pci_name(dev));
1302 if (pr)
1303 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1304 pr,
1305 (unsigned long long)pr->start,
1306 (unsigned long long)pr->end,
1307 (unsigned int)pr->flags);
1308 /* We'll assign a new address later */
1309 r->flags |= IORESOURCE_UNSET;
1310 r->end -= r->start;
1311 r->start = 0;
1312 }
1313}
1314
1315static void __init pcibios_allocate_resources(int pass)
1316{
1317 struct pci_dev *dev = NULL;
1318 int idx, disabled;
1319 u16 command;
1320 struct resource *r;
1321
1322 for_each_pci_dev(dev) {
1323 pci_read_config_word(dev, PCI_COMMAND, &command);
1324 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1325 r = &dev->resource[idx];
1326 if (r->parent) /* Already allocated */
1327 continue;
1328 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1329 continue; /* Not assigned at all */
1330 /* We only allocate ROMs on pass 1 just in case they
1331 * have been screwed up by firmware
1332 */
1333 if (idx == PCI_ROM_RESOURCE)
1334 disabled = 1;
1335 if (r->flags & IORESOURCE_IO)
1336 disabled = !(command & PCI_COMMAND_IO);
1337 else
1338 disabled = !(command & PCI_COMMAND_MEMORY);
1339 if (pass == disabled)
1340 alloc_resource(dev, idx);
1341 }
1342 if (pass)
1343 continue;
1344 r = &dev->resource[PCI_ROM_RESOURCE];
1345 if (r->flags) {
1346 /* Turn the ROM off, leave the resource region,
1347 * but keep it unregistered.
1348 */
1349 u32 reg;
1350 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
1351 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1352 pr_debug("PCI: Switching off ROM of %s\n",
1353 pci_name(dev));
1354 r->flags &= ~IORESOURCE_ROM_ENABLE;
1355 pci_write_config_dword(dev, dev->rom_base_reg,
1356 reg & ~PCI_ROM_ADDRESS_ENABLE);
1357 }
1358 }
1359 }
1360}
1361
1362static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1363{
1364 struct pci_controller *hose = pci_bus_to_host(bus);
1365 resource_size_t offset;
1366 struct resource *res, *pres;
1367 int i;
1368
1369 pr_debug("Reserving legacy ranges for domain %04x\n",
1370 pci_domain_nr(bus));
1371
1372 /* Check for IO */
1373 if (!(hose->io_resource.flags & IORESOURCE_IO))
1374 goto no_io;
1375 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1376 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1377 BUG_ON(res == NULL);
1378 res->name = "Legacy IO";
1379 res->flags = IORESOURCE_IO;
1380 res->start = offset;
1381 res->end = (offset + 0xfff) & 0xfffffffful;
1382 pr_debug("Candidate legacy IO: %pR\n", res);
1383 if (request_resource(&hose->io_resource, res)) {
1384 printk(KERN_DEBUG
1385 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1386 pci_domain_nr(bus), bus->number, res);
1387 kfree(res);
1388 }
1389
1390 no_io:
1391 /* Check for memory */
1392 offset = hose->pci_mem_offset;
1393 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1394 for (i = 0; i < 3; i++) {
1395 pres = &hose->mem_resources[i];
1396 if (!(pres->flags & IORESOURCE_MEM))
1397 continue;
1398 pr_debug("hose mem res: %pR\n", pres);
1399 if ((pres->start - offset) <= 0xa0000 &&
1400 (pres->end - offset) >= 0xbffff)
1401 break;
1402 }
1403 if (i >= 3)
1404 return;
1405 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1406 BUG_ON(res == NULL);
1407 res->name = "Legacy VGA memory";
1408 res->flags = IORESOURCE_MEM;
1409 res->start = 0xa0000 + offset;
1410 res->end = 0xbffff + offset;
1411 pr_debug("Candidate VGA memory: %pR\n", res);
1412 if (request_resource(pres, res)) {
1413 printk(KERN_DEBUG
1414 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1415 pci_domain_nr(bus), bus->number, res);
1416 kfree(res);
1417 }
1418}
1419
1420void __init pcibios_resource_survey(void)
1421{
1422 struct pci_bus *b;
1423
1424 /* Allocate and assign resources. If we re-assign everything, then
1425 * we skip the allocate phase
1426 */
1427 list_for_each_entry(b, &pci_root_buses, node)
1428 pcibios_allocate_bus_resources(b);
1429
1430 if (!(pci_flags & PCI_REASSIGN_ALL_RSRC)) {
1431 pcibios_allocate_resources(0);
1432 pcibios_allocate_resources(1);
1433 }
1434
1435 /* Before we start assigning unassigned resource, we try to reserve
1436 * the low IO area and the VGA memory area if they intersect the
1437 * bus available resources to avoid allocating things on top of them
1438 */
1439 if (!(pci_flags & PCI_PROBE_ONLY)) {
1440 list_for_each_entry(b, &pci_root_buses, node)
1441 pcibios_reserve_legacy_regions(b);
1442 }
1443
1444 /* Now, if the platform didn't decide to blindly trust the firmware,
1445 * we proceed to assigning things that were left unassigned
1446 */
1447 if (!(pci_flags & PCI_PROBE_ONLY)) {
1448 pr_debug("PCI: Assigning unassigned resources...\n");
1449 pci_assign_unassigned_resources();
1450 }
1451}
1452
1453#ifdef CONFIG_HOTPLUG
1454
1455/* This is used by the PCI hotplug driver to allocate resource
1456 * of newly plugged busses. We can try to consolidate with the
1457 * rest of the code later, for now, keep it as-is as our main
1458 * resource allocation function doesn't deal with sub-trees yet.
1459 */
1460void __devinit pcibios_claim_one_bus(struct pci_bus *bus)
1461{
1462 struct pci_dev *dev;
1463 struct pci_bus *child_bus;
1464
1465 list_for_each_entry(dev, &bus->devices, bus_list) {
1466 int i;
1467
1468 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1469 struct resource *r = &dev->resource[i];
1470
1471 if (r->parent || !r->start || !r->flags)
1472 continue;
1473
1474 pr_debug("PCI: Claiming %s: "
1475 "Resource %d: %016llx..%016llx [%x]\n",
1476 pci_name(dev), i,
1477 (unsigned long long)r->start,
1478 (unsigned long long)r->end,
1479 (unsigned int)r->flags);
1480
1481 pci_claim_resource(dev, i);
1482 }
1483 }
1484
1485 list_for_each_entry(child_bus, &bus->children, node)
1486 pcibios_claim_one_bus(child_bus);
1487}
1488EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1489
1490
1491/* pcibios_finish_adding_to_bus
1492 *
1493 * This is to be called by the hotplug code after devices have been
1494 * added to a bus, this include calling it for a PHB that is just
1495 * being added
1496 */
1497void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1498{
1499 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1500 pci_domain_nr(bus), bus->number);
1501
1502 /* Allocate bus and devices resources */
1503 pcibios_allocate_bus_resources(bus);
1504 pcibios_claim_one_bus(bus);
1505
1506 /* Add new devices to global lists. Register in proc, sysfs. */
1507 pci_bus_add_devices(bus);
1508
1509 /* Fixup EEH */
1510 /* eeh_add_device_tree_late(bus); */
1511}
1512EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1513
1514#endif /* CONFIG_HOTPLUG */
1515
1516int pcibios_enable_device(struct pci_dev *dev, int mask)
1517{
1518 return pci_enable_resources(dev, mask);
1519}
1520
1521void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
1522{
1523 struct pci_bus *bus = hose->bus;
1524 struct resource *res;
1525 int i;
1526
1527 /* Hookup PHB IO resource */
1528 bus->resource[0] = res = &hose->io_resource;
1529
1530 if (!res->flags) {
1531 printk(KERN_WARNING "PCI: I/O resource not set for host"
1532 " bridge %s (domain %d)\n",
1533 hose->dn->full_name, hose->global_number);
1534 /* Workaround for lack of IO resource only on 32-bit */
1535 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1536 res->end = res->start + IO_SPACE_LIMIT;
1537 res->flags = IORESOURCE_IO;
1538 }
1539
1540 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1541 (unsigned long long)res->start,
1542 (unsigned long long)res->end,
1543 (unsigned long)res->flags);
1544
1545 /* Hookup PHB Memory resources */
1546 for (i = 0; i < 3; ++i) {
1547 res = &hose->mem_resources[i];
1548 if (!res->flags) {
1549 if (i > 0)
1550 continue;
1551 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1552 "host bridge %s (domain %d)\n",
1553 hose->dn->full_name, hose->global_number);
1554
1555 /* Workaround for lack of MEM resource only on 32-bit */
1556 res->start = hose->pci_mem_offset;
1557 res->end = (resource_size_t)-1LL;
1558 res->flags = IORESOURCE_MEM;
1559
1560 }
1561 bus->resource[i+1] = res;
1562
1563 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1564 i, (unsigned long long)res->start,
1565 (unsigned long long)res->end,
1566 (unsigned long)res->flags);
1567 }
1568
1569 pr_debug("PCI: PHB MEM offset = %016llx\n",
1570 (unsigned long long)hose->pci_mem_offset);
1571 pr_debug("PCI: PHB IO offset = %08lx\n",
1572 (unsigned long)hose->io_base_virt - _IO_BASE);
1573}
1574
1575/*
1576 * Null PCI config access functions, for the case when we can't
1577 * find a hose.
1578 */
1579#define NULL_PCI_OP(rw, size, type) \
1580static int \
1581null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1582{ \
1583 return PCIBIOS_DEVICE_NOT_FOUND; \
1584}
1585
1586static int
1587null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1588 int len, u32 *val)
1589{
1590 return PCIBIOS_DEVICE_NOT_FOUND;
1591}
1592
1593static int
1594null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1595 int len, u32 val)
1596{
1597 return PCIBIOS_DEVICE_NOT_FOUND;
1598}
1599
1600static struct pci_ops null_pci_ops = {
1601 .read = null_read_config,
1602 .write = null_write_config,
1603};
1604
1605/*
1606 * These functions are used early on before PCI scanning is done
1607 * and all of the pci_dev and pci_bus structures have been created.
1608 */
1609static struct pci_bus *
1610fake_pci_bus(struct pci_controller *hose, int busnr)
1611{
1612 static struct pci_bus bus;
1613
1614 if (!hose)
1615 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1616
1617 bus.number = busnr;
1618 bus.sysdata = hose;
1619 bus.ops = hose ? hose->ops : &null_pci_ops;
1620 return &bus;
1621}
1622
1623#define EARLY_PCI_OP(rw, size, type) \
1624int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1625 int devfn, int offset, type value) \
1626{ \
1627 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1628 devfn, offset, value); \
1629}
1630
1631EARLY_PCI_OP(read, byte, u8 *)
1632EARLY_PCI_OP(read, word, u16 *)
1633EARLY_PCI_OP(read, dword, u32 *)
1634EARLY_PCI_OP(write, byte, u8)
1635EARLY_PCI_OP(write, word, u16)
1636EARLY_PCI_OP(write, dword, u32)
1637
1638int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1639 int cap)
1640{
1641 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1642}
diff --git a/arch/microblaze/pci/pci_32.c b/arch/microblaze/pci/pci_32.c
new file mode 100644
index 000000000000..3c3d808d7ce0
--- /dev/null
+++ b/arch/microblaze/pci/pci_32.c
@@ -0,0 +1,431 @@
1/*
2 * Common pmac/prep/chrp pci routines. -- Cort
3 */
4
5#include <linux/kernel.h>
6#include <linux/pci.h>
7#include <linux/delay.h>
8#include <linux/string.h>
9#include <linux/init.h>
10#include <linux/capability.h>
11#include <linux/sched.h>
12#include <linux/errno.h>
13#include <linux/bootmem.h>
14#include <linux/irq.h>
15#include <linux/list.h>
16#include <linux/of.h>
17#include <linux/slab.h>
18
19#include <asm/processor.h>
20#include <asm/io.h>
21#include <asm/prom.h>
22#include <asm/sections.h>
23#include <asm/pci-bridge.h>
24#include <asm/byteorder.h>
25#include <asm/uaccess.h>
26
27#undef DEBUG
28
29unsigned long isa_io_base;
30unsigned long pci_dram_offset;
31int pcibios_assign_bus_offset = 1;
32
33static u8 *pci_to_OF_bus_map;
34
35/* By default, we don't re-assign bus numbers. We do this only on
36 * some pmacs
37 */
38static int pci_assign_all_buses;
39
40static int pci_bus_count;
41
42/*
43 * Functions below are used on OpenFirmware machines.
44 */
45static void
46make_one_node_map(struct device_node *node, u8 pci_bus)
47{
48 const int *bus_range;
49 int len;
50
51 if (pci_bus >= pci_bus_count)
52 return;
53 bus_range = of_get_property(node, "bus-range", &len);
54 if (bus_range == NULL || len < 2 * sizeof(int)) {
55 printk(KERN_WARNING "Can't get bus-range for %s, "
56 "assuming it starts at 0\n", node->full_name);
57 pci_to_OF_bus_map[pci_bus] = 0;
58 } else
59 pci_to_OF_bus_map[pci_bus] = bus_range[0];
60
61 for_each_child_of_node(node, node) {
62 struct pci_dev *dev;
63 const unsigned int *class_code, *reg;
64
65 class_code = of_get_property(node, "class-code", NULL);
66 if (!class_code ||
67 ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
68 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
69 continue;
70 reg = of_get_property(node, "reg", NULL);
71 if (!reg)
72 continue;
73 dev = pci_get_bus_and_slot(pci_bus, ((reg[0] >> 8) & 0xff));
74 if (!dev || !dev->subordinate) {
75 pci_dev_put(dev);
76 continue;
77 }
78 make_one_node_map(node, dev->subordinate->number);
79 pci_dev_put(dev);
80 }
81}
82
83void
84pcibios_make_OF_bus_map(void)
85{
86 int i;
87 struct pci_controller *hose, *tmp;
88 struct property *map_prop;
89 struct device_node *dn;
90
91 pci_to_OF_bus_map = kmalloc(pci_bus_count, GFP_KERNEL);
92 if (!pci_to_OF_bus_map) {
93 printk(KERN_ERR "Can't allocate OF bus map !\n");
94 return;
95 }
96
97 /* We fill the bus map with invalid values, that helps
98 * debugging.
99 */
100 for (i = 0; i < pci_bus_count; i++)
101 pci_to_OF_bus_map[i] = 0xff;
102
103 /* For each hose, we begin searching bridges */
104 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
105 struct device_node *node = hose->dn;
106
107 if (!node)
108 continue;
109 make_one_node_map(node, hose->first_busno);
110 }
111 dn = of_find_node_by_path("/");
112 map_prop = of_find_property(dn, "pci-OF-bus-map", NULL);
113 if (map_prop) {
114 BUG_ON(pci_bus_count > map_prop->length);
115 memcpy(map_prop->value, pci_to_OF_bus_map, pci_bus_count);
116 }
117 of_node_put(dn);
118#ifdef DEBUG
119 printk(KERN_INFO "PCI->OF bus map:\n");
120 for (i = 0; i < pci_bus_count; i++) {
121 if (pci_to_OF_bus_map[i] == 0xff)
122 continue;
123 printk(KERN_INFO "%d -> %d\n", i, pci_to_OF_bus_map[i]);
124 }
125#endif
126}
127
128typedef int (*pci_OF_scan_iterator)(struct device_node *node, void *data);
129
130static struct device_node *scan_OF_pci_childs(struct device_node *parent,
131 pci_OF_scan_iterator filter, void *data)
132{
133 struct device_node *node;
134 struct device_node *sub_node;
135
136 for_each_child_of_node(parent, node) {
137 const unsigned int *class_code;
138
139 if (filter(node, data)) {
140 of_node_put(node);
141 return node;
142 }
143
144 /* For PCI<->PCI bridges or CardBus bridges, we go down
145 * Note: some OFs create a parent node "multifunc-device" as
146 * a fake root for all functions of a multi-function device,
147 * we go down them as well.
148 */
149 class_code = of_get_property(node, "class-code", NULL);
150 if ((!class_code ||
151 ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
152 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
153 strcmp(node->name, "multifunc-device"))
154 continue;
155 sub_node = scan_OF_pci_childs(node, filter, data);
156 if (sub_node) {
157 of_node_put(node);
158 return sub_node;
159 }
160 }
161 return NULL;
162}
163
164static struct device_node *scan_OF_for_pci_dev(struct device_node *parent,
165 unsigned int devfn)
166{
167 struct device_node *np, *cnp;
168 const u32 *reg;
169 unsigned int psize;
170
171 for_each_child_of_node(parent, np) {
172 reg = of_get_property(np, "reg", &psize);
173 if (reg && psize >= 4 && ((reg[0] >> 8) & 0xff) == devfn)
174 return np;
175
176 /* Note: some OFs create a parent node "multifunc-device" as
177 * a fake root for all functions of a multi-function device,
178 * we go down them as well. */
179 if (!strcmp(np->name, "multifunc-device")) {
180 cnp = scan_OF_for_pci_dev(np, devfn);
181 if (cnp)
182 return cnp;
183 }
184 }
185 return NULL;
186}
187
188
189static struct device_node *scan_OF_for_pci_bus(struct pci_bus *bus)
190{
191 struct device_node *parent, *np;
192
193 /* Are we a root bus ? */
194 if (bus->self == NULL || bus->parent == NULL) {
195 struct pci_controller *hose = pci_bus_to_host(bus);
196 if (hose == NULL)
197 return NULL;
198 return of_node_get(hose->dn);
199 }
200
201 /* not a root bus, we need to get our parent */
202 parent = scan_OF_for_pci_bus(bus->parent);
203 if (parent == NULL)
204 return NULL;
205
206 /* now iterate for children for a match */
207 np = scan_OF_for_pci_dev(parent, bus->self->devfn);
208 of_node_put(parent);
209
210 return np;
211}
212
213/*
214 * Scans the OF tree for a device node matching a PCI device
215 */
216struct device_node *
217pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
218{
219 struct device_node *parent, *np;
220
221 pr_debug("pci_busdev_to_OF_node(%d,0x%x)\n", bus->number, devfn);
222 parent = scan_OF_for_pci_bus(bus);
223 if (parent == NULL)
224 return NULL;
225 pr_debug(" parent is %s\n", parent ? parent->full_name : "<NULL>");
226 np = scan_OF_for_pci_dev(parent, devfn);
227 of_node_put(parent);
228 pr_debug(" result is %s\n", np ? np->full_name : "<NULL>");
229
230 /* XXX most callers don't release the returned node
231 * mostly because ppc64 doesn't increase the refcount,
232 * we need to fix that.
233 */
234 return np;
235}
236EXPORT_SYMBOL(pci_busdev_to_OF_node);
237
238struct device_node*
239pci_device_to_OF_node(struct pci_dev *dev)
240{
241 return pci_busdev_to_OF_node(dev->bus, dev->devfn);
242}
243EXPORT_SYMBOL(pci_device_to_OF_node);
244
245static int
246find_OF_pci_device_filter(struct device_node *node, void *data)
247{
248 return ((void *)node == data);
249}
250
251/*
252 * Returns the PCI device matching a given OF node
253 */
254int
255pci_device_from_OF_node(struct device_node *node, u8 *bus, u8 *devfn)
256{
257 const unsigned int *reg;
258 struct pci_controller *hose;
259 struct pci_dev *dev = NULL;
260
261 /* Make sure it's really a PCI device */
262 hose = pci_find_hose_for_OF_device(node);
263 if (!hose || !hose->dn)
264 return -ENODEV;
265 if (!scan_OF_pci_childs(hose->dn,
266 find_OF_pci_device_filter, (void *)node))
267 return -ENODEV;
268 reg = of_get_property(node, "reg", NULL);
269 if (!reg)
270 return -ENODEV;
271 *bus = (reg[0] >> 16) & 0xff;
272 *devfn = ((reg[0] >> 8) & 0xff);
273
274 /* Ok, here we need some tweak. If we have already renumbered
275 * all busses, we can't rely on the OF bus number any more.
276 * the pci_to_OF_bus_map is not enough as several PCI busses
277 * may match the same OF bus number.
278 */
279 if (!pci_to_OF_bus_map)
280 return 0;
281
282 for_each_pci_dev(dev)
283 if (pci_to_OF_bus_map[dev->bus->number] == *bus &&
284 dev->devfn == *devfn) {
285 *bus = dev->bus->number;
286 pci_dev_put(dev);
287 return 0;
288 }
289
290 return -ENODEV;
291}
292EXPORT_SYMBOL(pci_device_from_OF_node);
293
294/* We create the "pci-OF-bus-map" property now so it appears in the
295 * /proc device tree
296 */
297void __init
298pci_create_OF_bus_map(void)
299{
300 struct property *of_prop;
301 struct device_node *dn;
302
303 of_prop = (struct property *) alloc_bootmem(sizeof(struct property) + \
304 256);
305 if (!of_prop)
306 return;
307 dn = of_find_node_by_path("/");
308 if (dn) {
309 memset(of_prop, -1, sizeof(struct property) + 256);
310 of_prop->name = "pci-OF-bus-map";
311 of_prop->length = 256;
312 of_prop->value = &of_prop[1];
313 prom_add_property(dn, of_prop);
314 of_node_put(dn);
315 }
316}
317
318static void __devinit pcibios_scan_phb(struct pci_controller *hose)
319{
320 struct pci_bus *bus;
321 struct device_node *node = hose->dn;
322 unsigned long io_offset;
323 struct resource *res = &hose->io_resource;
324
325 pr_debug("PCI: Scanning PHB %s\n",
326 node ? node->full_name : "<NO NAME>");
327
328 /* Create an empty bus for the toplevel */
329 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose);
330 if (bus == NULL) {
331 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
332 hose->global_number);
333 return;
334 }
335 bus->secondary = hose->first_busno;
336 hose->bus = bus;
337
338 /* Fixup IO space offset */
339 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
340 res->start = (res->start + io_offset) & 0xffffffffu;
341 res->end = (res->end + io_offset) & 0xffffffffu;
342
343 /* Wire up PHB bus resources */
344 pcibios_setup_phb_resources(hose);
345
346 /* Scan children */
347 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
348}
349
350static int __init pcibios_init(void)
351{
352 struct pci_controller *hose, *tmp;
353 int next_busno = 0;
354
355 printk(KERN_INFO "PCI: Probing PCI hardware\n");
356
357 if (pci_flags & PCI_REASSIGN_ALL_BUS) {
358 printk(KERN_INFO "setting pci_asign_all_busses\n");
359 pci_assign_all_buses = 1;
360 }
361
362 /* Scan all of the recorded PCI controllers. */
363 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
364 if (pci_assign_all_buses)
365 hose->first_busno = next_busno;
366 hose->last_busno = 0xff;
367 pcibios_scan_phb(hose);
368 printk(KERN_INFO "calling pci_bus_add_devices()\n");
369 pci_bus_add_devices(hose->bus);
370 if (pci_assign_all_buses || next_busno <= hose->last_busno)
371 next_busno = hose->last_busno + \
372 pcibios_assign_bus_offset;
373 }
374 pci_bus_count = next_busno;
375
376 /* OpenFirmware based machines need a map of OF bus
377 * numbers vs. kernel bus numbers since we may have to
378 * remap them.
379 */
380 if (pci_assign_all_buses)
381 pcibios_make_OF_bus_map();
382
383 /* Call common code to handle resource allocation */
384 pcibios_resource_survey();
385
386 return 0;
387}
388
389subsys_initcall(pcibios_init);
390
391static struct pci_controller*
392pci_bus_to_hose(int bus)
393{
394 struct pci_controller *hose, *tmp;
395
396 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
397 if (bus >= hose->first_busno && bus <= hose->last_busno)
398 return hose;
399 return NULL;
400}
401
402/* Provide information on locations of various I/O regions in physical
403 * memory. Do this on a per-card basis so that we choose the right
404 * root bridge.
405 * Note that the returned IO or memory base is a physical address
406 */
407
408long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
409{
410 struct pci_controller *hose;
411 long result = -EOPNOTSUPP;
412
413 hose = pci_bus_to_hose(bus);
414 if (!hose)
415 return -ENODEV;
416
417 switch (which) {
418 case IOBASE_BRIDGE_NUMBER:
419 return (long)hose->first_busno;
420 case IOBASE_MEMORY:
421 return (long)hose->pci_mem_offset;
422 case IOBASE_IO:
423 return (long)hose->io_base_phys;
424 case IOBASE_ISA_IO:
425 return (long)isa_io_base;
426 case IOBASE_ISA_MEM:
427 return (long)isa_mem_base;
428 }
429
430 return result;
431}
diff --git a/arch/microblaze/pci/xilinx_pci.c b/arch/microblaze/pci/xilinx_pci.c
new file mode 100644
index 000000000000..7869a41b0f94
--- /dev/null
+++ b/arch/microblaze/pci/xilinx_pci.c
@@ -0,0 +1,168 @@
1/*
2 * PCI support for Xilinx plbv46_pci soft-core which can be used on
3 * Xilinx Virtex ML410 / ML510 boards.
4 *
5 * Copyright 2009 Roderick Colenbrander
6 * Copyright 2009 Secret Lab Technologies Ltd.
7 *
8 * The pci bridge fixup code was copied from ppc4xx_pci.c and was written
9 * by Benjamin Herrenschmidt.
10 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
11 *
12 * This file is licensed under the terms of the GNU General Public License
13 * version 2. This program is licensed "as is" without any warranty of any
14 * kind, whether express or implied.
15 */
16
17#include <linux/ioport.h>
18#include <linux/of.h>
19#include <linux/pci.h>
20#include <asm/io.h>
21
22#define XPLB_PCI_ADDR 0x10c
23#define XPLB_PCI_DATA 0x110
24#define XPLB_PCI_BUS 0x114
25
26#define PCI_HOST_ENABLE_CMD (PCI_COMMAND_SERR | PCI_COMMAND_PARITY | \
27 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)
28
29static struct of_device_id xilinx_pci_match[] = {
30 { .compatible = "xlnx,plbv46-pci-1.03.a", },
31 {}
32};
33
34/**
35 * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration.
36 */
37static void xilinx_pci_fixup_bridge(struct pci_dev *dev)
38{
39 struct pci_controller *hose;
40 int i;
41
42 if (dev->devfn || dev->bus->self)
43 return;
44
45 hose = pci_bus_to_host(dev->bus);
46 if (!hose)
47 return;
48
49 if (!of_match_node(xilinx_pci_match, hose->dn))
50 return;
51
52 /* Hide the PCI host BARs from the kernel as their content doesn't
53 * fit well in the resource management
54 */
55 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
56 dev->resource[i].start = 0;
57 dev->resource[i].end = 0;
58 dev->resource[i].flags = 0;
59 }
60
61 dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n",
62 pci_name(dev));
63}
64DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge);
65
66#ifdef DEBUG
67/**
68 * xilinx_pci_exclude_device - Don't do config access for non-root bus
69 *
70 * This is a hack. Config access to any bus other than bus 0 does not
71 * currently work on the ML510 so we prevent it here.
72 */
73static int
74xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn)
75{
76 return (bus != 0);
77}
78
79/**
80 * xilinx_early_pci_scan - List pci config space for available devices
81 *
82 * List pci devices in very early phase.
83 */
84void __init xilinx_early_pci_scan(struct pci_controller *hose)
85{
86 u32 bus = 0;
87 u32 val, dev, func, offset;
88
89 /* Currently we have only 2 device connected - up-to 32 devices */
90 for (dev = 0; dev < 2; dev++) {
91 /* List only first function number - up-to 8 functions */
92 for (func = 0; func < 1; func++) {
93 printk(KERN_INFO "%02x:%02x:%02x", bus, dev, func);
94 /* read the first 64 standardized bytes */
95 /* Up-to 192 bytes can be list of capabilities */
96 for (offset = 0; offset < 64; offset += 4) {
97 early_read_config_dword(hose, bus,
98 PCI_DEVFN(dev, func), offset, &val);
99 if (offset == 0 && val == 0xFFFFFFFF) {
100 printk(KERN_CONT "\nABSENT");
101 break;
102 }
103 if (!(offset % 0x10))
104 printk(KERN_CONT "\n%04x: ", offset);
105
106 printk(KERN_CONT "%08x ", val);
107 }
108 printk(KERN_INFO "\n");
109 }
110 }
111}
112#else
113void __init xilinx_early_pci_scan(struct pci_controller *hose)
114{
115}
116#endif
117
118/**
119 * xilinx_pci_init - Find and register a Xilinx PCI host bridge
120 */
121void __init xilinx_pci_init(void)
122{
123 struct pci_controller *hose;
124 struct resource r;
125 void __iomem *pci_reg;
126 struct device_node *pci_node;
127
128 pci_node = of_find_matching_node(NULL, xilinx_pci_match);
129 if (!pci_node)
130 return;
131
132 if (of_address_to_resource(pci_node, 0, &r)) {
133 pr_err("xilinx-pci: cannot resolve base address\n");
134 return;
135 }
136
137 hose = pcibios_alloc_controller(pci_node);
138 if (!hose) {
139 pr_err("xilinx-pci: pcibios_alloc_controller() failed\n");
140 return;
141 }
142
143 /* Setup config space */
144 setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR,
145 r.start + XPLB_PCI_DATA,
146 INDIRECT_TYPE_SET_CFG_TYPE);
147
148 /* According to the xilinx plbv46_pci documentation the soft-core starts
149 * a self-init when the bus master enable bit is set. Without this bit
150 * set the pci bus can't be scanned.
151 */
152 early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD);
153
154 /* Set the max latency timer to 255 */
155 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff);
156
157 /* Set the max bus number to 255, and bus/subbus no's to 0 */
158 pci_reg = of_iomap(pci_node, 0);
159 out_be32(pci_reg + XPLB_PCI_BUS, 0x000000ff);
160 iounmap(pci_reg);
161
162 /* Register the host bridge with the linux kernel! */
163 pci_process_bridge_OF_ranges(hose, pci_node,
164 INDIRECT_TYPE_SET_CFG_TYPE);
165
166 pr_info("xilinx-pci: Registered PCI host bridge\n");
167 xilinx_early_pci_scan(hose);
168}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-21 06:19:34 -0400