diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2013-08-27 06:04:39 -0400 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2013-09-03 10:31:15 -0400 |
| commit | 5955563ae2ff85e6ae30a2dc8c3ba071edeee957 (patch) | |
| tree | 96856efb218c4ecc5bbc2bf27811b466a0db2107 /arch/microblaze/kernel | |
| parent | 1e52980370e14cd1a336467b6839fb41a759c255 (diff) | |
microblaze: timer: Replace microblaze_ prefix by xilinx_
The main reason that this driver can be used by ARM
and PPC. The part of preparing of move to generic location.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/microblaze/kernel')
| -rw-r--r-- | arch/microblaze/kernel/timer.c | 78 |
1 files changed, 39 insertions, 39 deletions
diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c index 1b803960717d..e4b3f33ef34c 100644 --- a/arch/microblaze/kernel/timer.c +++ b/arch/microblaze/kernel/timer.c | |||
| @@ -42,13 +42,13 @@ static unsigned int timer_clock_freq; | |||
| 42 | #define TCSR_PWMA (1<<9) | 42 | #define TCSR_PWMA (1<<9) |
| 43 | #define TCSR_ENALL (1<<10) | 43 | #define TCSR_ENALL (1<<10) |
| 44 | 44 | ||
| 45 | static inline void microblaze_timer0_stop(void) | 45 | static inline void xilinx_timer0_stop(void) |
| 46 | { | 46 | { |
| 47 | out_be32(timer_baseaddr + TCSR0, | 47 | out_be32(timer_baseaddr + TCSR0, |
| 48 | in_be32(timer_baseaddr + TCSR0) & ~TCSR_ENT); | 48 | in_be32(timer_baseaddr + TCSR0) & ~TCSR_ENT); |
| 49 | } | 49 | } |
| 50 | 50 | ||
| 51 | static inline void microblaze_timer0_start_periodic(unsigned long load_val) | 51 | static inline void xilinx_timer0_start_periodic(unsigned long load_val) |
| 52 | { | 52 | { |
| 53 | if (!load_val) | 53 | if (!load_val) |
| 54 | load_val = 1; | 54 | load_val = 1; |
| @@ -75,7 +75,7 @@ static inline void microblaze_timer0_start_periodic(unsigned long load_val) | |||
| 75 | TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); | 75 | TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); |
| 76 | } | 76 | } |
| 77 | 77 | ||
| 78 | static inline void microblaze_timer0_start_oneshot(unsigned long load_val) | 78 | static inline void xilinx_timer0_start_oneshot(unsigned long load_val) |
| 79 | { | 79 | { |
| 80 | if (!load_val) | 80 | if (!load_val) |
| 81 | load_val = 1; | 81 | load_val = 1; |
| @@ -89,21 +89,21 @@ static inline void microblaze_timer0_start_oneshot(unsigned long load_val) | |||
| 89 | TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); | 89 | TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); |
| 90 | } | 90 | } |
| 91 | 91 | ||
| 92 | static int microblaze_timer_set_next_event(unsigned long delta, | 92 | static int xilinx_timer_set_next_event(unsigned long delta, |
| 93 | struct clock_event_device *dev) | 93 | struct clock_event_device *dev) |
| 94 | { | 94 | { |
| 95 | pr_debug("%s: next event, delta %x\n", __func__, (u32)delta); | 95 | pr_debug("%s: next event, delta %x\n", __func__, (u32)delta); |
| 96 | microblaze_timer0_start_oneshot(delta); | 96 | xilinx_timer0_start_oneshot(delta); |
| 97 | return 0; | 97 | return 0; |
| 98 | } | 98 | } |
| 99 | 99 | ||
| 100 | static void microblaze_timer_set_mode(enum clock_event_mode mode, | 100 | static void xilinx_timer_set_mode(enum clock_event_mode mode, |
| 101 | struct clock_event_device *evt) | 101 | struct clock_event_device *evt) |
| 102 | { | 102 | { |
| 103 | switch (mode) { | 103 | switch (mode) { |
| 104 | case CLOCK_EVT_MODE_PERIODIC: | 104 | case CLOCK_EVT_MODE_PERIODIC: |
| 105 | pr_info("%s: periodic\n", __func__); | 105 | pr_info("%s: periodic\n", __func__); |
| 106 | microblaze_timer0_start_periodic(freq_div_hz); | 106 | xilinx_timer0_start_periodic(freq_div_hz); |
| 107 | break; | 107 | break; |
| 108 | case CLOCK_EVT_MODE_ONESHOT: | 108 | case CLOCK_EVT_MODE_ONESHOT: |
| 109 | pr_info("%s: oneshot\n", __func__); | 109 | pr_info("%s: oneshot\n", __func__); |
| @@ -113,7 +113,7 @@ static void microblaze_timer_set_mode(enum clock_event_mode mode, | |||
| 113 | break; | 113 | break; |
| 114 | case CLOCK_EVT_MODE_SHUTDOWN: | 114 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 115 | pr_info("%s: shutdown\n", __func__); | 115 | pr_info("%s: shutdown\n", __func__); |
| 116 | microblaze_timer0_stop(); | 116 | xilinx_timer0_stop(); |
| 117 | break; | 117 | break; |
| 118 | case CLOCK_EVT_MODE_RESUME: | 118 | case CLOCK_EVT_MODE_RESUME: |
| 119 | pr_info("%s: resume\n", __func__); | 119 | pr_info("%s: resume\n", __func__); |
| @@ -121,13 +121,13 @@ static void microblaze_timer_set_mode(enum clock_event_mode mode, | |||
| 121 | } | 121 | } |
| 122 | } | 122 | } |
| 123 | 123 | ||
| 124 | static struct clock_event_device clockevent_microblaze_timer = { | 124 | static struct clock_event_device clockevent_xilinx_timer = { |
| 125 | .name = "microblaze_clockevent", | 125 | .name = "xilinx_clockevent", |
| 126 | .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, | 126 | .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, |
| 127 | .shift = 8, | 127 | .shift = 8, |
| 128 | .rating = 300, | 128 | .rating = 300, |
| 129 | .set_next_event = microblaze_timer_set_next_event, | 129 | .set_next_event = xilinx_timer_set_next_event, |
| 130 | .set_mode = microblaze_timer_set_mode, | 130 | .set_mode = xilinx_timer_set_mode, |
| 131 | }; | 131 | }; |
| 132 | 132 | ||
| 133 | static inline void timer_ack(void) | 133 | static inline void timer_ack(void) |
| @@ -137,7 +137,7 @@ static inline void timer_ack(void) | |||
| 137 | 137 | ||
| 138 | static irqreturn_t timer_interrupt(int irq, void *dev_id) | 138 | static irqreturn_t timer_interrupt(int irq, void *dev_id) |
| 139 | { | 139 | { |
| 140 | struct clock_event_device *evt = &clockevent_microblaze_timer; | 140 | struct clock_event_device *evt = &clockevent_xilinx_timer; |
| 141 | #ifdef CONFIG_HEART_BEAT | 141 | #ifdef CONFIG_HEART_BEAT |
| 142 | heartbeat(); | 142 | heartbeat(); |
| 143 | #endif | 143 | #endif |
| @@ -150,62 +150,62 @@ static struct irqaction timer_irqaction = { | |||
| 150 | .handler = timer_interrupt, | 150 | .handler = timer_interrupt, |
| 151 | .flags = IRQF_DISABLED | IRQF_TIMER, | 151 | .flags = IRQF_DISABLED | IRQF_TIMER, |
| 152 | .name = "timer", | 152 | .name = "timer", |
| 153 | .dev_id = &clockevent_microblaze_timer, | 153 | .dev_id = &clockevent_xilinx_timer, |
| 154 | }; | 154 | }; |
| 155 | 155 | ||
| 156 | static __init void microblaze_clockevent_init(void) | 156 | static __init void xilinx_clockevent_init(void) |
| 157 | { | 157 | { |
| 158 | clockevent_microblaze_timer.mult = | 158 | clockevent_xilinx_timer.mult = |
| 159 | div_sc(timer_clock_freq, NSEC_PER_SEC, | 159 | div_sc(timer_clock_freq, NSEC_PER_SEC, |
| 160 | clockevent_microblaze_timer.shift); | 160 | clockevent_xilinx_timer.shift); |
| 161 | clockevent_microblaze_timer.max_delta_ns = | 161 | clockevent_xilinx_timer.max_delta_ns = |
| 162 | clockevent_delta2ns((u32)~0, &clockevent_microblaze_timer); | 162 | clockevent_delta2ns((u32)~0, &clockevent_xilinx_timer); |
| 163 | clockevent_microblaze_timer.min_delta_ns = | 163 | clockevent_xilinx_timer.min_delta_ns = |
| 164 | clockevent_delta2ns(1, &clockevent_microblaze_timer); | 164 | clockevent_delta2ns(1, &clockevent_xilinx_timer); |
| 165 | clockevent_microblaze_timer.cpumask = cpumask_of(0); | 165 | clockevent_xilinx_timer.cpumask = cpumask_of(0); |
| 166 | clockevents_register_device(&clockevent_microblaze_timer); | 166 | clockevents_register_device(&clockevent_xilinx_timer); |
| 167 | } | 167 | } |
| 168 | 168 | ||
| 169 | static cycle_t microblaze_read(struct clocksource *cs) | 169 | static cycle_t xilinx_read(struct clocksource *cs) |
| 170 | { | 170 | { |
| 171 | /* reading actual value of timer 1 */ | 171 | /* reading actual value of timer 1 */ |
| 172 | return (cycle_t) (in_be32(timer_baseaddr + TCR1)); | 172 | return (cycle_t) (in_be32(timer_baseaddr + TCR1)); |
| 173 | } | 173 | } |
| 174 | 174 | ||
| 175 | static struct timecounter microblaze_tc = { | 175 | static struct timecounter xilinx_tc = { |
| 176 | .cc = NULL, | 176 | .cc = NULL, |
| 177 | }; | 177 | }; |
| 178 | 178 | ||
| 179 | static cycle_t microblaze_cc_read(const struct cyclecounter *cc) | 179 | static cycle_t xilinx_cc_read(const struct cyclecounter *cc) |
| 180 | { | 180 | { |
| 181 | return microblaze_read(NULL); | 181 | return xilinx_read(NULL); |
| 182 | } | 182 | } |
| 183 | 183 | ||
| 184 | static struct cyclecounter microblaze_cc = { | 184 | static struct cyclecounter xilinx_cc = { |
| 185 | .read = microblaze_cc_read, | 185 | .read = xilinx_cc_read, |
| 186 | .mask = CLOCKSOURCE_MASK(32), | 186 | .mask = CLOCKSOURCE_MASK(32), |
| 187 | .shift = 8, | 187 | .shift = 8, |
| 188 | }; | 188 | }; |
| 189 | 189 | ||
| 190 | static int __init init_microblaze_timecounter(void) | 190 | static int __init init_xilinx_timecounter(void) |
| 191 | { | 191 | { |
| 192 | microblaze_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC, | 192 | xilinx_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC, |
| 193 | microblaze_cc.shift); | 193 | xilinx_cc.shift); |
| 194 | 194 | ||
| 195 | timecounter_init(µblaze_tc, µblaze_cc, sched_clock()); | 195 | timecounter_init(&xilinx_tc, &xilinx_cc, sched_clock()); |
| 196 | 196 | ||
| 197 | return 0; | 197 | return 0; |
| 198 | } | 198 | } |
| 199 | 199 | ||
| 200 | static struct clocksource clocksource_microblaze = { | 200 | static struct clocksource clocksource_microblaze = { |
| 201 | .name = "microblaze_clocksource", | 201 | .name = "xilinx_clocksource", |
| 202 | .rating = 300, | 202 | .rating = 300, |
| 203 | .read = microblaze_read, | 203 | .read = xilinx_read, |
| 204 | .mask = CLOCKSOURCE_MASK(32), | 204 | .mask = CLOCKSOURCE_MASK(32), |
| 205 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 205 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 206 | }; | 206 | }; |
| 207 | 207 | ||
| 208 | static int __init microblaze_clocksource_init(void) | 208 | static int __init xilinx_clocksource_init(void) |
| 209 | { | 209 | { |
| 210 | if (clocksource_register_hz(&clocksource_microblaze, timer_clock_freq)) | 210 | if (clocksource_register_hz(&clocksource_microblaze, timer_clock_freq)) |
| 211 | panic("failed to register clocksource"); | 211 | panic("failed to register clocksource"); |
| @@ -217,7 +217,7 @@ static int __init microblaze_clocksource_init(void) | |||
| 217 | out_be32(timer_baseaddr + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT); | 217 | out_be32(timer_baseaddr + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT); |
| 218 | 218 | ||
| 219 | /* register timecounter - for ftrace support */ | 219 | /* register timecounter - for ftrace support */ |
| 220 | init_microblaze_timecounter(); | 220 | init_xilinx_timecounter(); |
| 221 | return 0; | 221 | return 0; |
| 222 | } | 222 | } |
| 223 | 223 | ||
| @@ -260,8 +260,8 @@ static void __init xilinx_timer_init(struct device_node *timer) | |||
| 260 | #ifdef CONFIG_HEART_BEAT | 260 | #ifdef CONFIG_HEART_BEAT |
| 261 | setup_heartbeat(); | 261 | setup_heartbeat(); |
| 262 | #endif | 262 | #endif |
| 263 | microblaze_clocksource_init(); | 263 | xilinx_clocksource_init(); |
| 264 | microblaze_clockevent_init(); | 264 | xilinx_clockevent_init(); |
| 265 | timer_initialized = 1; | 265 | timer_initialized = 1; |
| 266 | } | 266 | } |
| 267 | 267 | ||
