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authorGrant Likely <grant.likely@secretlab.ca>2010-01-28 16:38:25 -0500
committerGrant Likely <grant.likely@secretlab.ca>2010-01-28 16:38:25 -0500
commit0ada0a73120c28cc432bcdbac061781465c2f48f (patch)
treed17cadd4ea47e25d9e48e7d409a39c84268fbd27 /arch/microblaze/include
parent6016a363f6b56b46b24655bcfc0499b715851cf3 (diff)
parent92dcffb916d309aa01778bf8963a6932e4014d07 (diff)
Merge commit 'v2.6.33-rc5' into secretlab/test-devicetree
Diffstat (limited to 'arch/microblaze/include')
-rw-r--r--arch/microblaze/include/asm/asm-offsets.h1
-rw-r--r--arch/microblaze/include/asm/cache.h16
-rw-r--r--arch/microblaze/include/asm/cacheflush.h124
-rw-r--r--arch/microblaze/include/asm/cpuinfo.h5
-rw-r--r--arch/microblaze/include/asm/device.h12
-rw-r--r--arch/microblaze/include/asm/elf.h1
-rw-r--r--arch/microblaze/include/asm/ftrace.h25
-rw-r--r--arch/microblaze/include/asm/futex.h127
-rw-r--r--arch/microblaze/include/asm/irqflags.h112
-rw-r--r--arch/microblaze/include/asm/page.h3
-rw-r--r--arch/microblaze/include/asm/pgalloc.h9
-rw-r--r--arch/microblaze/include/asm/ptrace.h14
-rw-r--r--arch/microblaze/include/asm/pvr.h30
-rw-r--r--arch/microblaze/include/asm/setup.h2
-rw-r--r--arch/microblaze/include/asm/system.h2
-rw-r--r--arch/microblaze/include/asm/uaccess.h12
-rw-r--r--arch/microblaze/include/asm/unistd.h5
17 files changed, 332 insertions, 168 deletions
diff --git a/arch/microblaze/include/asm/asm-offsets.h b/arch/microblaze/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/microblaze/include/asm/asm-offsets.h
@@ -0,0 +1 @@
#include <generated/asm-offsets.h>
diff --git a/arch/microblaze/include/asm/cache.h b/arch/microblaze/include/asm/cache.h
index c209c47509d5..e52210891d78 100644
--- a/arch/microblaze/include/asm/cache.h
+++ b/arch/microblaze/include/asm/cache.h
@@ -21,20 +21,4 @@
21 21
22#define SMP_CACHE_BYTES L1_CACHE_BYTES 22#define SMP_CACHE_BYTES L1_CACHE_BYTES
23 23
24void _enable_icache(void);
25void _disable_icache(void);
26void _invalidate_icache(unsigned int addr);
27
28#define __enable_icache() _enable_icache()
29#define __disable_icache() _disable_icache()
30#define __invalidate_icache(addr) _invalidate_icache(addr)
31
32void _enable_dcache(void);
33void _disable_dcache(void);
34void _invalidate_dcache(unsigned int addr);
35
36#define __enable_dcache() _enable_dcache()
37#define __disable_dcache() _disable_dcache()
38#define __invalidate_dcache(addr) _invalidate_dcache(addr)
39
40#endif /* _ASM_MICROBLAZE_CACHE_H */ 24#endif /* _ASM_MICROBLAZE_CACHE_H */
diff --git a/arch/microblaze/include/asm/cacheflush.h b/arch/microblaze/include/asm/cacheflush.h
index f989d6aad648..a6edd356cd08 100644
--- a/arch/microblaze/include/asm/cacheflush.h
+++ b/arch/microblaze/include/asm/cacheflush.h
@@ -18,6 +18,8 @@
18/* Somebody depends on this; sigh... */ 18/* Somebody depends on this; sigh... */
19#include <linux/mm.h> 19#include <linux/mm.h>
20 20
21/* Look at Documentation/cachetlb.txt */
22
21/* 23/*
22 * Cache handling functions. 24 * Cache handling functions.
23 * Microblaze has a write-through data cache, meaning that the data cache 25 * Microblaze has a write-through data cache, meaning that the data cache
@@ -27,77 +29,81 @@
27 * instruction cache to make sure we don't fetch old, bad code. 29 * instruction cache to make sure we don't fetch old, bad code.
28 */ 30 */
29 31
32/* struct cache, d=dcache, i=icache, fl = flush, iv = invalidate,
33 * suffix r = range */
34struct scache {
35 /* icache */
36 void (*ie)(void); /* enable */
37 void (*id)(void); /* disable */
38 void (*ifl)(void); /* flush */
39 void (*iflr)(unsigned long a, unsigned long b);
40 void (*iin)(void); /* invalidate */
41 void (*iinr)(unsigned long a, unsigned long b);
42 /* dcache */
43 void (*de)(void); /* enable */
44 void (*dd)(void); /* disable */
45 void (*dfl)(void); /* flush */
46 void (*dflr)(unsigned long a, unsigned long b);
47 void (*din)(void); /* invalidate */
48 void (*dinr)(unsigned long a, unsigned long b);
49};
50
51/* microblaze cache */
52extern struct scache *mbc;
53
54void microblaze_cache_init(void);
55
56#define enable_icache() mbc->ie();
57#define disable_icache() mbc->id();
58#define flush_icache() mbc->ifl();
59#define flush_icache_range(start, end) mbc->iflr(start, end);
60#define invalidate_icache() mbc->iin();
61#define invalidate_icache_range(start, end) mbc->iinr(start, end);
62
63
64#define flush_icache_user_range(vma, pg, adr, len) flush_icache();
65#define flush_icache_page(vma, pg) do { } while (0)
66
67#define enable_dcache() mbc->de();
68#define disable_dcache() mbc->dd();
30/* FIXME for LL-temac driver */ 69/* FIXME for LL-temac driver */
31#define invalidate_dcache_range(start, end) \ 70#define invalidate_dcache() mbc->din();
32 __invalidate_dcache_range(start, end) 71#define invalidate_dcache_range(start, end) mbc->dinr(start, end);
33 72#define flush_dcache() mbc->dfl();
34#define flush_cache_all() __invalidate_cache_all() 73#define flush_dcache_range(start, end) mbc->dflr(start, end);
35#define flush_cache_mm(mm) do { } while (0)
36#define flush_cache_range(vma, start, end) __invalidate_cache_all()
37#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
38 74
39#define flush_dcache_range(start, end) __invalidate_dcache_range(start, end) 75#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
76/* D-cache aliasing problem can't happen - cache is between MMU and ram */
40#define flush_dcache_page(page) do { } while (0) 77#define flush_dcache_page(page) do { } while (0)
41#define flush_dcache_mmap_lock(mapping) do { } while (0) 78#define flush_dcache_mmap_lock(mapping) do { } while (0)
42#define flush_dcache_mmap_unlock(mapping) do { } while (0) 79#define flush_dcache_mmap_unlock(mapping) do { } while (0)
43 80
44#define flush_icache_range(start, len) __invalidate_icache_range(start, len)
45#define flush_icache_page(vma, pg) do { } while (0)
46
47#ifndef CONFIG_MMU
48# define flush_icache_user_range(start, len) do { } while (0)
49#else
50# define flush_icache_user_range(vma, pg, adr, len) __invalidate_icache_all()
51
52# define flush_page_to_ram(page) do { } while (0)
53 81
54# define flush_icache() __invalidate_icache_all() 82#define flush_cache_dup_mm(mm) do { } while (0)
55# define flush_cache_sigtramp(vaddr) \ 83#define flush_cache_vmap(start, end) do { } while (0)
56 __invalidate_icache_range(vaddr, vaddr + 8) 84#define flush_cache_vunmap(start, end) do { } while (0)
57 85#define flush_cache_mm(mm) do { } while (0)
58# define flush_dcache_mmap_lock(mapping) do { } while (0) 86#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
59# define flush_dcache_mmap_unlock(mapping) do { } while (0)
60 87
61# define flush_cache_dup_mm(mm) do { } while (0) 88/* MS: kgdb code use this macro, wrong len with FLASH */
89#if 0
90#define flush_cache_range(vma, start, len) { \
91 flush_icache_range((unsigned) (start), (unsigned) (start) + (len)); \
92 flush_dcache_range((unsigned) (start), (unsigned) (start) + (len)); \
93}
62#endif 94#endif
63 95
64#define flush_cache_vmap(start, end) do { } while (0) 96#define flush_cache_range(vma, start, len) do { } while (0)
65#define flush_cache_vunmap(start, end) do { } while (0)
66
67struct page;
68struct mm_struct;
69struct vm_area_struct;
70
71/* see arch/microblaze/kernel/cache.c */
72extern void __invalidate_icache_all(void);
73extern void __invalidate_icache_range(unsigned long start, unsigned long end);
74extern void __invalidate_icache_page(struct vm_area_struct *vma,
75 struct page *page);
76extern void __invalidate_icache_user_range(struct vm_area_struct *vma,
77 struct page *page,
78 unsigned long adr, int len);
79extern void __invalidate_cache_sigtramp(unsigned long addr);
80
81extern void __invalidate_dcache_all(void);
82extern void __invalidate_dcache_range(unsigned long start, unsigned long end);
83extern void __invalidate_dcache_page(struct vm_area_struct *vma,
84 struct page *page);
85extern void __invalidate_dcache_user_range(struct vm_area_struct *vma,
86 struct page *page,
87 unsigned long adr, int len);
88
89extern inline void __invalidate_cache_all(void)
90{
91 __invalidate_icache_all();
92 __invalidate_dcache_all();
93}
94 97
95#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ 98#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
96do { memcpy((dst), (src), (len)); \ 99do { \
97 flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \ 100 memcpy((dst), (src), (len)); \
101 flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
98} while (0) 102} while (0)
99 103
100#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ 104#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
101 memcpy((dst), (src), (len)) 105do { \
106 memcpy((dst), (src), (len)); \
107} while (0)
102 108
103#endif /* _ASM_MICROBLAZE_CACHEFLUSH_H */ 109#endif /* _ASM_MICROBLAZE_CACHEFLUSH_H */
diff --git a/arch/microblaze/include/asm/cpuinfo.h b/arch/microblaze/include/asm/cpuinfo.h
index 52f28f6dc4eb..b4f5ca33aebf 100644
--- a/arch/microblaze/include/asm/cpuinfo.h
+++ b/arch/microblaze/include/asm/cpuinfo.h
@@ -43,7 +43,7 @@ struct cpuinfo {
43 u32 use_icache; 43 u32 use_icache;
44 u32 icache_tagbits; 44 u32 icache_tagbits;
45 u32 icache_write; 45 u32 icache_write;
46 u32 icache_line; 46 u32 icache_line_length;
47 u32 icache_size; 47 u32 icache_size;
48 unsigned long icache_base; 48 unsigned long icache_base;
49 unsigned long icache_high; 49 unsigned long icache_high;
@@ -51,8 +51,9 @@ struct cpuinfo {
51 u32 use_dcache; 51 u32 use_dcache;
52 u32 dcache_tagbits; 52 u32 dcache_tagbits;
53 u32 dcache_write; 53 u32 dcache_write;
54 u32 dcache_line; 54 u32 dcache_line_length;
55 u32 dcache_size; 55 u32 dcache_size;
56 u32 dcache_wb;
56 unsigned long dcache_base; 57 unsigned long dcache_base;
57 unsigned long dcache_high; 58 unsigned long dcache_high;
58 59
diff --git a/arch/microblaze/include/asm/device.h b/arch/microblaze/include/asm/device.h
index 30286db27c1c..78a038452c0f 100644
--- a/arch/microblaze/include/asm/device.h
+++ b/arch/microblaze/include/asm/device.h
@@ -19,6 +19,18 @@ struct dev_archdata {
19struct pdev_archdata { 19struct pdev_archdata {
20}; 20};
21 21
22static inline void dev_archdata_set_node(struct dev_archdata *ad,
23 struct device_node *np)
24{
25 ad->of_node = np;
26}
27
28static inline struct device_node *
29dev_archdata_get_node(const struct dev_archdata *ad)
30{
31 return ad->of_node;
32}
33
22#endif /* _ASM_MICROBLAZE_DEVICE_H */ 34#endif /* _ASM_MICROBLAZE_DEVICE_H */
23 35
24 36
diff --git a/arch/microblaze/include/asm/elf.h b/arch/microblaze/include/asm/elf.h
index f92fc0dda006..7d4acf2b278e 100644
--- a/arch/microblaze/include/asm/elf.h
+++ b/arch/microblaze/include/asm/elf.h
@@ -77,7 +77,6 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
77#define ELF_DATA ELFDATA2MSB 77#define ELF_DATA ELFDATA2MSB
78#endif 78#endif
79 79
80#define USE_ELF_CORE_DUMP
81#define ELF_EXEC_PAGESIZE 4096 80#define ELF_EXEC_PAGESIZE 4096
82 81
83 82
diff --git a/arch/microblaze/include/asm/ftrace.h b/arch/microblaze/include/asm/ftrace.h
index 8b137891791f..fd2fa2eca62f 100644
--- a/arch/microblaze/include/asm/ftrace.h
+++ b/arch/microblaze/include/asm/ftrace.h
@@ -1 +1,26 @@
1#ifndef _ASM_MICROBLAZE_FTRACE
2#define _ASM_MICROBLAZE_FTRACE
1 3
4#ifdef CONFIG_FUNCTION_TRACER
5
6#define MCOUNT_ADDR ((long)(_mcount))
7#define MCOUNT_INSN_SIZE 8 /* sizeof mcount call */
8
9#ifndef __ASSEMBLY__
10extern void _mcount(void);
11extern void ftrace_call_graph(void);
12#endif
13
14#ifdef CONFIG_DYNAMIC_FTRACE
15/* reloction of mcount call site is the same as the address */
16static inline unsigned long ftrace_call_adjust(unsigned long addr)
17{
18 return addr;
19}
20
21struct dyn_arch_ftrace {
22};
23#endif /* CONFIG_DYNAMIC_FTRACE */
24
25#endif /* CONFIG_FUNCTION_TRACER */
26#endif /* _ASM_MICROBLAZE_FTRACE */
diff --git a/arch/microblaze/include/asm/futex.h b/arch/microblaze/include/asm/futex.h
index 0b745828f42b..8dbb6e7a03a2 100644
--- a/arch/microblaze/include/asm/futex.h
+++ b/arch/microblaze/include/asm/futex.h
@@ -1 +1,126 @@
1#include <asm-generic/futex.h> 1#ifndef _ASM_MICROBLAZE_FUTEX_H
2#define _ASM_MICROBLAZE_FUTEX_H
3
4#ifdef __KERNEL__
5
6#include <linux/futex.h>
7#include <linux/uaccess.h>
8#include <asm/errno.h>
9
10#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
11({ \
12 __asm__ __volatile__ ( \
13 "1: lwx %0, %2, r0; " \
14 insn \
15 "2: swx %1, %2, r0; \
16 addic %1, r0, 0; \
17 bnei %1, 1b; \
18 3: \
19 .section .fixup,\"ax\"; \
20 4: brid 3b; \
21 addik %1, r0, %3; \
22 .previous; \
23 .section __ex_table,\"a\"; \
24 .word 1b,4b,2b,4b; \
25 .previous;" \
26 : "=&r" (oldval), "=&r" (ret) \
27 : "b" (uaddr), "i" (-EFAULT), "r" (oparg) \
28 ); \
29})
30
31static inline int
32futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
33{
34 int op = (encoded_op >> 28) & 7;
35 int cmp = (encoded_op >> 24) & 15;
36 int oparg = (encoded_op << 8) >> 20;
37 int cmparg = (encoded_op << 20) >> 20;
38 int oldval = 0, ret;
39 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
40 oparg = 1 << oparg;
41
42 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
43 return -EFAULT;
44
45 pagefault_disable();
46
47 switch (op) {
48 case FUTEX_OP_SET:
49 __futex_atomic_op("or %1,%4,%4;", ret, oldval, uaddr, oparg);
50 break;
51 case FUTEX_OP_ADD:
52 __futex_atomic_op("add %1,%0,%4;", ret, oldval, uaddr, oparg);
53 break;
54 case FUTEX_OP_OR:
55 __futex_atomic_op("or %1,%0,%4;", ret, oldval, uaddr, oparg);
56 break;
57 case FUTEX_OP_ANDN:
58 __futex_atomic_op("and %1,%0,%4;", ret, oldval, uaddr, oparg);
59 break;
60 case FUTEX_OP_XOR:
61 __futex_atomic_op("xor %1,%0,%4;", ret, oldval, uaddr, oparg);
62 break;
63 default:
64 ret = -ENOSYS;
65 }
66
67 pagefault_enable();
68
69 if (!ret) {
70 switch (cmp) {
71 case FUTEX_OP_CMP_EQ:
72 ret = (oldval == cmparg);
73 break;
74 case FUTEX_OP_CMP_NE:
75 ret = (oldval != cmparg);
76 break;
77 case FUTEX_OP_CMP_LT:
78 ret = (oldval < cmparg);
79 break;
80 case FUTEX_OP_CMP_GE:
81 ret = (oldval >= cmparg);
82 break;
83 case FUTEX_OP_CMP_LE:
84 ret = (oldval <= cmparg);
85 break;
86 case FUTEX_OP_CMP_GT:
87 ret = (oldval > cmparg);
88 break;
89 default:
90 ret = -ENOSYS;
91 }
92 }
93 return ret;
94}
95
96static inline int
97futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
98{
99 int prev, cmp;
100
101 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
102 return -EFAULT;
103
104 __asm__ __volatile__ ("1: lwx %0, %2, r0; \
105 cmp %1, %0, %3; \
106 beqi %1, 3f; \
107 2: swx %4, %2, r0; \
108 addic %1, r0, 0; \
109 bnei %1, 1b; \
110 3: \
111 .section .fixup,\"ax\"; \
112 4: brid 3b; \
113 addik %0, r0, %5; \
114 .previous; \
115 .section __ex_table,\"a\"; \
116 .word 1b,4b,2b,4b; \
117 .previous;" \
118 : "=&r" (prev), "=&r"(cmp) \
119 : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT));
120
121 return prev;
122}
123
124#endif /* __KERNEL__ */
125
126#endif
diff --git a/arch/microblaze/include/asm/irqflags.h b/arch/microblaze/include/asm/irqflags.h
index dea65645a4f8..2c38c6d80176 100644
--- a/arch/microblaze/include/asm/irqflags.h
+++ b/arch/microblaze/include/asm/irqflags.h
@@ -10,78 +10,73 @@
10#define _ASM_MICROBLAZE_IRQFLAGS_H 10#define _ASM_MICROBLAZE_IRQFLAGS_H
11 11
12#include <linux/irqflags.h> 12#include <linux/irqflags.h>
13#include <asm/registers.h>
13 14
14# if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 15# if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
15 16
16# define local_irq_save(flags) \ 17# define raw_local_irq_save(flags) \
17 do { \ 18 do { \
18 asm volatile ("# local_irq_save \n\t" \ 19 asm volatile (" msrclr %0, %1; \
19 "msrclr %0, %1 \n\t" \ 20 nop;" \
20 "nop \n\t" \
21 : "=r"(flags) \ 21 : "=r"(flags) \
22 : "i"(MSR_IE) \ 22 : "i"(MSR_IE) \
23 : "memory"); \ 23 : "memory"); \
24 } while (0) 24 } while (0)
25 25
26# define local_irq_disable() \ 26# define raw_local_irq_disable() \
27 do { \ 27 do { \
28 asm volatile ("# local_irq_disable \n\t" \ 28 asm volatile (" msrclr r0, %0; \
29 "msrclr r0, %0 \n\t" \ 29 nop;" \
30 "nop \n\t" \ 30 : \
31 : \ 31 : "i"(MSR_IE) \
32 : "i"(MSR_IE) \ 32 : "memory"); \
33 : "memory"); \
34 } while (0) 33 } while (0)
35 34
36# define local_irq_enable() \ 35# define raw_local_irq_enable() \
37 do { \ 36 do { \
38 asm volatile ("# local_irq_enable \n\t" \ 37 asm volatile (" msrset r0, %0; \
39 "msrset r0, %0 \n\t" \ 38 nop;" \
40 "nop \n\t" \ 39 : \
41 : \ 40 : "i"(MSR_IE) \
42 : "i"(MSR_IE) \ 41 : "memory"); \
43 : "memory"); \
44 } while (0) 42 } while (0)
45 43
46# else /* CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR == 0 */ 44# else /* CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR == 0 */
47 45
48# define local_irq_save(flags) \ 46# define raw_local_irq_save(flags) \
49 do { \ 47 do { \
50 register unsigned tmp; \ 48 register unsigned tmp; \
51 asm volatile ("# local_irq_save \n\t" \ 49 asm volatile (" mfs %0, rmsr; \
52 "mfs %0, rmsr \n\t" \ 50 nop; \
53 "nop \n\t" \ 51 andi %1, %0, %2; \
54 "andi %1, %0, %2 \n\t" \ 52 mts rmsr, %1; \
55 "mts rmsr, %1 \n\t" \ 53 nop;" \
56 "nop \n\t" \
57 : "=r"(flags), "=r" (tmp) \ 54 : "=r"(flags), "=r" (tmp) \
58 : "i"(~MSR_IE) \ 55 : "i"(~MSR_IE) \
59 : "memory"); \ 56 : "memory"); \
60 } while (0) 57 } while (0)
61 58
62# define local_irq_disable() \ 59# define raw_local_irq_disable() \
63 do { \ 60 do { \
64 register unsigned tmp; \ 61 register unsigned tmp; \
65 asm volatile ("# local_irq_disable \n\t" \ 62 asm volatile (" mfs %0, rmsr; \
66 "mfs %0, rmsr \n\t" \ 63 nop; \
67 "nop \n\t" \ 64 andi %0, %0, %1; \
68 "andi %0, %0, %1 \n\t" \ 65 mts rmsr, %0; \
69 "mts rmsr, %0 \n\t" \ 66 nop;" \
70 "nop \n\t" \
71 : "=r"(tmp) \ 67 : "=r"(tmp) \
72 : "i"(~MSR_IE) \ 68 : "i"(~MSR_IE) \
73 : "memory"); \ 69 : "memory"); \
74 } while (0) 70 } while (0)
75 71
76# define local_irq_enable() \ 72# define raw_local_irq_enable() \
77 do { \ 73 do { \
78 register unsigned tmp; \ 74 register unsigned tmp; \
79 asm volatile ("# local_irq_enable \n\t" \ 75 asm volatile (" mfs %0, rmsr; \
80 "mfs %0, rmsr \n\t" \ 76 nop; \
81 "nop \n\t" \ 77 ori %0, %0, %1; \
82 "ori %0, %0, %1 \n\t" \ 78 mts rmsr, %0; \
83 "mts rmsr, %0 \n\t" \ 79 nop;" \
84 "nop \n\t" \
85 : "=r"(tmp) \ 80 : "=r"(tmp) \
86 : "i"(MSR_IE) \ 81 : "i"(MSR_IE) \
87 : "memory"); \ 82 : "memory"); \
@@ -89,35 +84,28 @@
89 84
90# endif /* CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR */ 85# endif /* CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR */
91 86
92#define local_save_flags(flags) \ 87#define raw_local_irq_restore(flags) \
93 do { \ 88 do { \
94 asm volatile ("# local_save_flags \n\t" \ 89 asm volatile (" mts rmsr, %0; \
95 "mfs %0, rmsr \n\t" \ 90 nop;" \
96 "nop \n\t" \
97 : "=r"(flags) \
98 : \ 91 : \
92 : "r"(flags) \
99 : "memory"); \ 93 : "memory"); \
100 } while (0) 94 } while (0)
101 95
102#define local_irq_restore(flags) \ 96static inline unsigned long get_msr(void)
103 do { \
104 asm volatile ("# local_irq_restore \n\t"\
105 "mts rmsr, %0 \n\t" \
106 "nop \n\t" \
107 : \
108 : "r"(flags) \
109 : "memory"); \
110 } while (0)
111
112static inline int irqs_disabled(void)
113{ 97{
114 unsigned long flags; 98 unsigned long flags;
115 99 asm volatile (" mfs %0, rmsr; \
116 local_save_flags(flags); 100 nop;" \
117 return ((flags & MSR_IE) == 0); 101 : "=r"(flags) \
102 : \
103 : "memory"); \
104 return flags;
118} 105}
119 106
120#define raw_irqs_disabled irqs_disabled 107#define raw_local_save_flags(flags) ((flags) = get_msr())
121#define raw_irqs_disabled_flags(flags) ((flags) == 0) 108#define raw_irqs_disabled() ((get_msr() & MSR_IE) == 0)
109#define raw_irqs_disabled_flags(flags) ((flags & MSR_IE) == 0)
122 110
123#endif /* _ASM_MICROBLAZE_IRQFLAGS_H */ 111#endif /* _ASM_MICROBLAZE_IRQFLAGS_H */
diff --git a/arch/microblaze/include/asm/page.h b/arch/microblaze/include/asm/page.h
index 880c988c2237..9b66c0fa9a32 100644
--- a/arch/microblaze/include/asm/page.h
+++ b/arch/microblaze/include/asm/page.h
@@ -164,7 +164,8 @@ extern int page_is_ram(unsigned long pfn);
164# endif /* CONFIG_MMU */ 164# endif /* CONFIG_MMU */
165 165
166# ifndef CONFIG_MMU 166# ifndef CONFIG_MMU
167# define pfn_valid(pfn) ((pfn) >= min_low_pfn && (pfn) <= max_mapnr) 167# define pfn_valid(pfn) (((pfn) >= min_low_pfn) && \
168 ((pfn) <= (min_low_pfn + max_mapnr)))
168# define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT) 169# define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT)
169# else /* CONFIG_MMU */ 170# else /* CONFIG_MMU */
170# define ARCH_PFN_OFFSET (memory_start >> PAGE_SHIFT) 171# define ARCH_PFN_OFFSET (memory_start >> PAGE_SHIFT)
diff --git a/arch/microblaze/include/asm/pgalloc.h b/arch/microblaze/include/asm/pgalloc.h
index b0131da1387b..7547f5064560 100644
--- a/arch/microblaze/include/asm/pgalloc.h
+++ b/arch/microblaze/include/asm/pgalloc.h
@@ -106,9 +106,6 @@ extern inline void free_pgd_slow(pgd_t *pgd)
106 */ 106 */
107#define pmd_alloc_one_fast(mm, address) ({ BUG(); ((pmd_t *)1); }) 107#define pmd_alloc_one_fast(mm, address) ({ BUG(); ((pmd_t *)1); })
108#define pmd_alloc_one(mm, address) ({ BUG(); ((pmd_t *)2); }) 108#define pmd_alloc_one(mm, address) ({ BUG(); ((pmd_t *)2); })
109/* FIXME two definition - look below */
110#define pmd_free(mm, x) do { } while (0)
111#define pgd_populate(mm, pmd, pte) BUG()
112 109
113static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, 110static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
114 unsigned long address) 111 unsigned long address)
@@ -192,14 +189,14 @@ extern inline void pte_free(struct mm_struct *mm, struct page *ptepage)
192 * the pgd will always be present.. 189 * the pgd will always be present..
193 */ 190 */
194#define pmd_alloc_one(mm, address) ({ BUG(); ((pmd_t *)2); }) 191#define pmd_alloc_one(mm, address) ({ BUG(); ((pmd_t *)2); })
195/*#define pmd_free(mm, x) do { } while (0)*/ 192#define pmd_free(mm, x) do { } while (0)
196#define __pmd_free_tlb(tlb, x, addr) do { } while (0) 193#define __pmd_free_tlb(tlb, x, addr) pmd_free((tlb)->mm, x)
197#define pgd_populate(mm, pmd, pte) BUG() 194#define pgd_populate(mm, pmd, pte) BUG()
198 195
199extern int do_check_pgt_cache(int, int); 196extern int do_check_pgt_cache(int, int);
200 197
201#endif /* CONFIG_MMU */ 198#endif /* CONFIG_MMU */
202 199
203#define check_pgt_cache() do {} while (0) 200#define check_pgt_cache() do { } while (0)
204 201
205#endif /* _ASM_MICROBLAZE_PGALLOC_H */ 202#endif /* _ASM_MICROBLAZE_PGALLOC_H */
diff --git a/arch/microblaze/include/asm/ptrace.h b/arch/microblaze/include/asm/ptrace.h
index a917dc517736..d74dbfb92c04 100644
--- a/arch/microblaze/include/asm/ptrace.h
+++ b/arch/microblaze/include/asm/ptrace.h
@@ -54,6 +54,7 @@ struct pt_regs {
54 int pt_mode; 54 int pt_mode;
55}; 55};
56 56
57#ifdef __KERNEL__
57#define kernel_mode(regs) ((regs)->pt_mode) 58#define kernel_mode(regs) ((regs)->pt_mode)
58#define user_mode(regs) (!kernel_mode(regs)) 59#define user_mode(regs) (!kernel_mode(regs))
59 60
@@ -62,6 +63,19 @@ struct pt_regs {
62 63
63void show_regs(struct pt_regs *); 64void show_regs(struct pt_regs *);
64 65
66#else /* __KERNEL__ */
67
68/* pt_regs offsets used by gdbserver etc in ptrace syscalls */
69#define PT_GPR(n) ((n) * sizeof(microblaze_reg_t))
70#define PT_PC (32 * sizeof(microblaze_reg_t))
71#define PT_MSR (33 * sizeof(microblaze_reg_t))
72#define PT_EAR (34 * sizeof(microblaze_reg_t))
73#define PT_ESR (35 * sizeof(microblaze_reg_t))
74#define PT_FSR (36 * sizeof(microblaze_reg_t))
75#define PT_KERNEL_MODE (37 * sizeof(microblaze_reg_t))
76
77#endif /* __KERNEL */
78
65#endif /* __ASSEMBLY__ */ 79#endif /* __ASSEMBLY__ */
66 80
67#endif /* _ASM_MICROBLAZE_PTRACE_H */ 81#endif /* _ASM_MICROBLAZE_PTRACE_H */
diff --git a/arch/microblaze/include/asm/pvr.h b/arch/microblaze/include/asm/pvr.h
index 66f1b30dd097..e38abc7714b6 100644
--- a/arch/microblaze/include/asm/pvr.h
+++ b/arch/microblaze/include/asm/pvr.h
@@ -76,20 +76,23 @@ struct pvr_s {
76#define PVR3_FSL_LINKS_MASK 0x00000380 76#define PVR3_FSL_LINKS_MASK 0x00000380
77 77
78/* ICache config PVR masks */ 78/* ICache config PVR masks */
79#define PVR4_USE_ICACHE_MASK 0x80000000 79#define PVR4_USE_ICACHE_MASK 0x80000000 /* ICU */
80#define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 80#define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 /* ICTS */
81#define PVR4_ICACHE_USE_FSL_MASK 0x02000000 81#define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 /* ICW */
82#define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 82#define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 /* ICLL */
83#define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 83#define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 /* ICBS */
84#define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 84#define PVR4_ICACHE_ALWAYS_USED 0x00008000 /* IAU */
85#define PVR4_ICACHE_INTERFACE 0x00002000 /* ICI */
85 86
86/* DCache config PVR masks */ 87/* DCache config PVR masks */
87#define PVR5_USE_DCACHE_MASK 0x80000000 88#define PVR5_USE_DCACHE_MASK 0x80000000 /* DCU */
88#define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 89#define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 /* DCTS */
89#define PVR5_DCACHE_USE_FSL_MASK 0x02000000 90#define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 /* DCW */
90#define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 91#define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 /* DCLL */
91#define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 92#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 /* DCBS */
92#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 93#define PVR5_DCACHE_ALWAYS_USED 0x00008000 /* DAU */
94#define PVR5_DCACHE_USE_WRITEBACK 0x00004000 /* DWB */
95#define PVR5_DCACHE_INTERFACE 0x00002000 /* DCI */
93 96
94/* ICache base address PVR mask */ 97/* ICache base address PVR mask */
95#define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF 98#define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
@@ -178,11 +181,14 @@ struct pvr_s {
178 ((pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26) 181 ((pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
179#define PVR_DCACHE_USE_FSL(pvr) (pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK) 182#define PVR_DCACHE_USE_FSL(pvr) (pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK)
180#define PVR_DCACHE_ALLOW_WR(pvr) (pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK) 183#define PVR_DCACHE_ALLOW_WR(pvr) (pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK)
184/* FIXME two shifts on one line needs any comment */
181#define PVR_DCACHE_LINE_LEN(pvr) \ 185#define PVR_DCACHE_LINE_LEN(pvr) \
182 (1 << ((pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21)) 186 (1 << ((pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21))
183#define PVR_DCACHE_BYTE_SIZE(pvr) \ 187#define PVR_DCACHE_BYTE_SIZE(pvr) \
184 (1 << ((pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16)) 188 (1 << ((pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
185 189
190#define PVR_DCACHE_USE_WRITEBACK(pvr) \
191 ((pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14)
186 192
187#define PVR_ICACHE_BASEADDR(pvr) (pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK) 193#define PVR_ICACHE_BASEADDR(pvr) (pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK)
188#define PVR_ICACHE_HIGHADDR(pvr) (pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK) 194#define PVR_ICACHE_HIGHADDR(pvr) (pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK)
diff --git a/arch/microblaze/include/asm/setup.h b/arch/microblaze/include/asm/setup.h
index ed67c9ed15b8..7f31394985e0 100644
--- a/arch/microblaze/include/asm/setup.h
+++ b/arch/microblaze/include/asm/setup.h
@@ -35,6 +35,8 @@ extern void mmu_reset(void);
35extern void early_console_reg_tlb_alloc(unsigned int addr); 35extern void early_console_reg_tlb_alloc(unsigned int addr);
36# endif /* CONFIG_MMU */ 36# endif /* CONFIG_MMU */
37 37
38extern void of_platform_reset_gpio_probe(void);
39
38void time_init(void); 40void time_init(void);
39void init_IRQ(void); 41void init_IRQ(void);
40void machine_early_init(const char *cmdline, unsigned int ram, 42void machine_early_init(const char *cmdline, unsigned int ram,
diff --git a/arch/microblaze/include/asm/system.h b/arch/microblaze/include/asm/system.h
index b1ed61590660..157970688b2a 100644
--- a/arch/microblaze/include/asm/system.h
+++ b/arch/microblaze/include/asm/system.h
@@ -16,6 +16,8 @@
16#include <asm-generic/cmpxchg.h> 16#include <asm-generic/cmpxchg.h>
17#include <asm-generic/cmpxchg-local.h> 17#include <asm-generic/cmpxchg-local.h>
18 18
19#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
20
19struct task_struct; 21struct task_struct;
20struct thread_info; 22struct thread_info;
21 23
diff --git a/arch/microblaze/include/asm/uaccess.h b/arch/microblaze/include/asm/uaccess.h
index 5431b4631a7a..371bd6e56d9a 100644
--- a/arch/microblaze/include/asm/uaccess.h
+++ b/arch/microblaze/include/asm/uaccess.h
@@ -272,8 +272,9 @@ static inline int clear_user(char *to, int size)
272 return size; 272 return size;
273} 273}
274 274
275extern unsigned long __copy_tofrom_user(void __user *to, 275#define __copy_from_user(to, from, n) copy_from_user((to), (from), (n))
276 const void __user *from, unsigned long size); 276#define __copy_from_user_inatomic(to, from, n) \
277 copy_from_user((to), (from), (n))
277 278
278#define copy_to_user(to, from, n) \ 279#define copy_to_user(to, from, n) \
279 (access_ok(VERIFY_WRITE, (to), (n)) ? \ 280 (access_ok(VERIFY_WRITE, (to), (n)) ? \
@@ -290,10 +291,6 @@ extern unsigned long __copy_tofrom_user(void __user *to,
290 (void __user *)(from), (n)) \ 291 (void __user *)(from), (n)) \
291 : -EFAULT) 292 : -EFAULT)
292 293
293#define __copy_from_user(to, from, n) copy_from_user((to), (from), (n))
294#define __copy_from_user_inatomic(to, from, n) \
295 copy_from_user((to), (from), (n))
296
297extern int __strncpy_user(char *to, const char __user *from, int len); 294extern int __strncpy_user(char *to, const char __user *from, int len);
298extern int __strnlen_user(const char __user *sstr, int len); 295extern int __strnlen_user(const char __user *sstr, int len);
299 296
@@ -305,6 +302,9 @@ extern int __strnlen_user(const char __user *sstr, int len);
305 302
306#endif /* CONFIG_MMU */ 303#endif /* CONFIG_MMU */
307 304
305extern unsigned long __copy_tofrom_user(void __user *to,
306 const void __user *from, unsigned long size);
307
308/* 308/*
309 * The exception table consists of pairs of addresses: the first is the 309 * The exception table consists of pairs of addresses: the first is the
310 * address of an instruction that is allowed to fault, and the second is 310 * address of an instruction that is allowed to fault, and the second is
diff --git a/arch/microblaze/include/asm/unistd.h b/arch/microblaze/include/asm/unistd.h
index cb05a07e55e9..2b67e92a773c 100644
--- a/arch/microblaze/include/asm/unistd.h
+++ b/arch/microblaze/include/asm/unistd.h
@@ -377,13 +377,14 @@
377#define __NR_shutdown 359 /* new */ 377#define __NR_shutdown 359 /* new */
378#define __NR_sendmsg 360 /* new */ 378#define __NR_sendmsg 360 /* new */
379#define __NR_recvmsg 361 /* new */ 379#define __NR_recvmsg 361 /* new */
380#define __NR_accept04 362 /* new */ 380#define __NR_accept4 362 /* new */
381#define __NR_preadv 363 /* new */ 381#define __NR_preadv 363 /* new */
382#define __NR_pwritev 364 /* new */ 382#define __NR_pwritev 364 /* new */
383#define __NR_rt_tgsigqueueinfo 365 /* new */ 383#define __NR_rt_tgsigqueueinfo 365 /* new */
384#define __NR_perf_event_open 366 /* new */ 384#define __NR_perf_event_open 366 /* new */
385#define __NR_recvmmsg 367 /* new */
385 386
386#define __NR_syscalls 367 387#define __NR_syscalls 368
387 388
388#ifdef __KERNEL__ 389#ifdef __KERNEL__
389#ifndef __ASSEMBLY__ 390#ifndef __ASSEMBLY__
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 09:18:17 -0400