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authorJohn A. Williams <john.williams@petalogix.com>2011-05-24 04:57:11 -0400
committerMichal Simek <monstr@monstr.eu>2011-07-25 03:13:42 -0400
commit8904976e8ca45be3ec75acc71f5d855ef671a079 (patch)
tree9c76c35266329312ace36ab009d686d5e2cd77f8 /arch/microblaze/include/asm
parent5db34eb92f5699361de355dcd7958fdd2a9fb98a (diff)
microblaze: Unprivileged stream instruction awareness
Add cpuinfo support for the new MicroBlaze option permitting userspace (unprivileged) access to the streaming instructions (FSL / AXI-stream). Emit a noisy warning at bootup if this is enabled, because bad user code can potentially lockup the CPU. Signed-off-by: John A. Williams <john.williams@petalogix.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
Diffstat (limited to 'arch/microblaze/include/asm')
-rw-r--r--arch/microblaze/include/asm/cpuinfo.h1
-rw-r--r--arch/microblaze/include/asm/pvr.h3
2 files changed, 3 insertions, 1 deletions
diff --git a/arch/microblaze/include/asm/cpuinfo.h b/arch/microblaze/include/asm/cpuinfo.h
index d8f013347a9e..7d6831ac8a46 100644
--- a/arch/microblaze/include/asm/cpuinfo.h
+++ b/arch/microblaze/include/asm/cpuinfo.h
@@ -38,6 +38,7 @@ struct cpuinfo {
38 u32 use_exc; 38 u32 use_exc;
39 u32 ver_code; 39 u32 ver_code;
40 u32 mmu; 40 u32 mmu;
41 u32 mmu_privins;
41 u32 endian; 42 u32 endian;
42 43
43 /* CPU caches */ 44 /* CPU caches */
diff --git a/arch/microblaze/include/asm/pvr.h b/arch/microblaze/include/asm/pvr.h
index 56a80e45c4e2..4bbdb4c03b57 100644
--- a/arch/microblaze/include/asm/pvr.h
+++ b/arch/microblaze/include/asm/pvr.h
@@ -117,10 +117,10 @@ struct pvr_s {
117#define PVR11_MMU_DTLB_SIZE 0x07000000 117#define PVR11_MMU_DTLB_SIZE 0x07000000
118#define PVR11_MMU_TLB_ACCESS 0x00C00000 118#define PVR11_MMU_TLB_ACCESS 0x00C00000
119#define PVR11_MMU_ZONES 0x003C0000 119#define PVR11_MMU_ZONES 0x003C0000
120#define PVR11_MMU_PRIVINS 0x00010000
120/* MSR Reset value PVR mask */ 121/* MSR Reset value PVR mask */
121#define PVR11_MSR_RESET_VALUE_MASK 0x000007FF 122#define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
122 123
123
124/* PVR access macros */ 124/* PVR access macros */
125#define PVR_IS_FULL(_pvr) (_pvr.pvr[0] & PVR0_PVR_FULL_MASK) 125#define PVR_IS_FULL(_pvr) (_pvr.pvr[0] & PVR0_PVR_FULL_MASK)
126#define PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & PVR0_USE_BARREL_MASK) 126#define PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & PVR0_USE_BARREL_MASK)
@@ -216,6 +216,7 @@ struct pvr_s {
216#define PVR_MMU_DTLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE) 216#define PVR_MMU_DTLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE)
217#define PVR_MMU_TLB_ACCESS(_pvr) (_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS) 217#define PVR_MMU_TLB_ACCESS(_pvr) (_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS)
218#define PVR_MMU_ZONES(_pvr) (_pvr.pvr[11] & PVR11_MMU_ZONES) 218#define PVR_MMU_ZONES(_pvr) (_pvr.pvr[11] & PVR11_MMU_ZONES)
219#define PVR_MMU_PRIVINS(pvr) (pvr.pvr[11] & PVR11_MMU_PRIVINS)
219 220
220/* endian */ 221/* endian */
221#define PVR_ENDIAN(_pvr) (_pvr.pvr[0] & PVR0_ENDI) 222#define PVR_ENDIAN(_pvr) (_pvr.pvr[0] & PVR0_ENDI)