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authorMatt Waddel <Matt.Waddel@freescale.com>2008-12-20 09:16:38 -0500
committerGreg Ungerer <gerg@uclinux.org>2009-01-27 01:42:03 -0500
commitadd8240eedb586b9d885c324db7f98fc1a470f9f (patch)
treed29913cdf206040fd4e1ef9f542c2e01bb1baf1d /arch/m68knommu
parent05ae6fa31874eda2484da13c5dc4ddee8a47a0a4 (diff)
m68knommu: fix 5329 ColdFire periphal addressing
The 5329 ColdFire peripheral IO register addresses are not relative to the MBAR register. So fix the serial platform setup array and IRQ acking to use just the direct addresses. Signed-off-by: Matt Waddel <Matt.Waddel@freescale.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu')
-rw-r--r--arch/m68knommu/platform/532x/config.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/m68knommu/platform/532x/config.c b/arch/m68knommu/platform/532x/config.c
index 4f44b632045b..a347623d6ee6 100644
--- a/arch/m68knommu/platform/532x/config.c
+++ b/arch/m68knommu/platform/532x/config.c
@@ -41,15 +41,15 @@ extern unsigned int mcf_timerlevel;
41 41
42static struct mcf_platform_uart m532x_uart_platform[] = { 42static struct mcf_platform_uart m532x_uart_platform[] = {
43 { 43 {
44 .mapbase = MCF_MBAR + MCFUART_BASE1, 44 .mapbase = MCFUART_BASE1,
45 .irq = MCFINT_VECBASE + MCFINT_UART0, 45 .irq = MCFINT_VECBASE + MCFINT_UART0,
46 }, 46 },
47 { 47 {
48 .mapbase = MCF_MBAR + MCFUART_BASE2, 48 .mapbase = MCFUART_BASE2,
49 .irq = MCFINT_VECBASE + MCFINT_UART1, 49 .irq = MCFINT_VECBASE + MCFINT_UART1,
50 }, 50 },
51 { 51 {
52 .mapbase = MCF_MBAR + MCFUART_BASE3, 52 .mapbase = MCFUART_BASE3,
53 .irq = MCFINT_VECBASE + MCFINT_UART2, 53 .irq = MCFINT_VECBASE + MCFINT_UART2,
54 }, 54 },
55 { }, 55 { },
@@ -108,7 +108,7 @@ void mcf_settimericr(unsigned int timer, unsigned int level)
108 default: irq = 32; icr = MCFSIM_ICR_TIMER1; break; 108 default: irq = 32; icr = MCFSIM_ICR_TIMER1; break;
109 } 109 }
110 110
111 icrp = (volatile unsigned char *) (MCF_MBAR + icr); 111 icrp = (volatile unsigned char *) (icr);
112 *icrp = level; 112 *icrp = level;
113 mcf_enable_irq0(irq); 113 mcf_enable_irq0(irq);
114 } 114 }