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authorGreg Ungerer <gerg@uclinux.org>2009-05-19 00:52:40 -0400
committerGreg Ungerer <gerg@uclinux.org>2009-09-15 19:43:51 -0400
commit04b75b10dceadf937e3707ecc3dfccf6a076fd29 (patch)
tree87965d12b8f7eb622efd1d36bebd2a7b8a26452e /arch/m68knommu/platform/5407
parentf9311f26434cea3e926f56ca2aa3e5740e962c72 (diff)
m68knommu: simplify ColdFire "timers" clock initialization
The ColdFire "timers" clock setup can be simplified. There is really no need for the flexible per-platform setup code. The clock interrupt can be hard defined per CPU platform (in CPU include files). This makes the actual timer code simpler. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu/platform/5407')
-rw-r--r--arch/m68knommu/platform/5407/config.c39
1 files changed, 12 insertions, 27 deletions
diff --git a/arch/m68knommu/platform/5407/config.c b/arch/m68knommu/platform/5407/config.c
index 8aa94837bbc3..cc80029a4a00 100644
--- a/arch/m68knommu/platform/5407/config.c
+++ b/arch/m68knommu/platform/5407/config.c
@@ -20,12 +20,6 @@
20 20
21/***************************************************************************/ 21/***************************************************************************/
22 22
23extern unsigned int mcf_timervector;
24extern unsigned int mcf_profilevector;
25extern unsigned int mcf_timerlevel;
26
27/***************************************************************************/
28
29static struct mcf_platform_uart m5407_uart_platform[] = { 23static struct mcf_platform_uart m5407_uart_platform[] = {
30 { 24 {
31 .mapbase = MCF_MBAR + MCFUART_BASE1, 25 .mapbase = MCF_MBAR + MCFUART_BASE1,
@@ -59,6 +53,7 @@ static void __init m5407_uart_init_line(int line, int irq)
59 } else if (line == 1) { 53 } else if (line == 1) {
60 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 54 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
61 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR); 55 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
56 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
62 mcf_clrimr(MCFINTC_UART1); 57 mcf_clrimr(MCFINTC_UART1);
63 } 58 }
64} 59}
@@ -74,21 +69,17 @@ static void __init m5407_uarts_init(void)
74 69
75/***************************************************************************/ 70/***************************************************************************/
76 71
77void mcf_settimericr(unsigned int timer, unsigned int level) 72static void __init m5407_timers_init(void)
78{ 73{
79 volatile unsigned char *icrp; 74 /* Timer1 is always used as system timer */
80 unsigned int icr, imr; 75 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
81 76 MCF_MBAR + MCFSIM_TIMER1ICR);
82 if (timer <= 2) { 77
83 switch (timer) { 78#ifdef CONFIG_HIGHPROFILE
84 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break; 79 /* Timer2 is to be used as a high speed profile timer */
85 default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break; 80 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
86 } 81 MCF_MBAR + MCFSIM_TIMER2ICR);
87 82#endif
88 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
89 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
90 mcf_clrimr(imr);
91 }
92} 83}
93 84
94/***************************************************************************/ 85/***************************************************************************/
@@ -106,14 +97,8 @@ void m5407_cpu_reset(void)
106 97
107void __init config_BSP(char *commandp, int size) 98void __init config_BSP(char *commandp, int size)
108{ 99{
109#if defined(CONFIG_CLEOPATRA)
110 /* Different timer setup - to prevent device clash */
111 mcf_timervector = 30;
112 mcf_profilevector = 31;
113 mcf_timerlevel = 6;
114#endif
115
116 mach_reset = m5407_cpu_reset; 100 mach_reset = m5407_cpu_reset;
101 m5407_timers_init();
117} 102}
118 103
119/***************************************************************************/ 104/***************************************************************************/