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authorGreg Ungerer <gerg@uclinux.org>2010-11-02 22:50:30 -0400
committerGreg Ungerer <gerg@uclinux.org>2011-01-05 00:19:17 -0500
commit57015421d3f3deafb1f6ccf03a6fe0539763dbee (patch)
tree965daef9dd9f5ee351dec0f4dfa7037a50e94ecc /arch/m68k
parent733f31b764061d976a60c5ee454632d9562900ea (diff)
m68knommu: move UART addressing to part specific includes
The ColdFire UART base addresses varies between the different ColdFire family members. Instead of keeping the base addresses with the UART definitions keep them with the other addresses definitions for each ColdFire part. The motivation for this move is so that when we add new ColdFire part definitions, they are all in a single file (and we shouldn't normally need to modify the UART definitions in mcfuart.h at all). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k')
-rw-r--r--arch/m68k/include/asm/m5206sim.h10
-rw-r--r--arch/m68k/include/asm/m520xsim.h9
-rw-r--r--arch/m68k/include/asm/m523xsim.h7
-rw-r--r--arch/m68k/include/asm/m5249sim.h5
-rw-r--r--arch/m68k/include/asm/m5272sim.h3
-rw-r--r--arch/m68k/include/asm/m527xsim.h6
-rw-r--r--arch/m68k/include/asm/m528xsim.h7
-rw-r--r--arch/m68k/include/asm/m5307sim.h11
-rw-r--r--arch/m68k/include/asm/m532xsim.h7
-rw-r--r--arch/m68k/include/asm/m5407sim.h3
-rw-r--r--arch/m68k/include/asm/m54xxsim.h8
-rw-r--r--arch/m68k/include/asm/mcfuart.h43
12 files changed, 74 insertions, 45 deletions
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index b882a210ee6e..aa7ee48d5059 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -90,6 +90,14 @@
90#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */ 90#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
91#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */ 91#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
92 92
93#if defined(CONFIG_NETtel)
94#define MCFUART_BASE1 0x180 /* Base address of UART1 */
95#define MCFUART_BASE2 0x140 /* Base address of UART2 */
96#else
97#define MCFUART_BASE1 0x140 /* Base address of UART1 */
98#define MCFUART_BASE2 0x180 /* Base address of UART2 */
99#endif
100
93/* 101/*
94 * Define system peripheral IRQ usage. 102 * Define system peripheral IRQ usage.
95 */ 103 */
@@ -97,7 +105,7 @@
97#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 105#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
98 106
99/* 107/*
100 * Generic GPIO 108 * Generic GPIO
101 */ 109 */
102#define MCFGPIO_PIN_MAX 8 110#define MCFGPIO_PIN_MAX 8
103#define MCFGPIO_IRQ_VECBASE -1 111#define MCFGPIO_IRQ_VECBASE -1
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 85b39edf41a0..8cd8bce38594 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -100,6 +100,7 @@
100#define MCFGPIO_PCLRR_UART 0xFC0A402A 100#define MCFGPIO_PCLRR_UART 0xFC0A402A
101#define MCFGPIO_PCLRR_FECH 0xFC0A402B 101#define MCFGPIO_PCLRR_FECH 0xFC0A402B
102#define MCFGPIO_PCLRR_FECL 0xFC0A402C 102#define MCFGPIO_PCLRR_FECL 0xFC0A402C
103
103/* 104/*
104 * Generic GPIO support 105 * Generic GPIO support
105 */ 106 */
@@ -112,7 +113,6 @@
112#define MCFGPIO_PIN_MAX 80 113#define MCFGPIO_PIN_MAX 80
113#define MCFGPIO_IRQ_MAX 8 114#define MCFGPIO_IRQ_MAX 8
114#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 115#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
115/****************************************************************************/
116 116
117#define MCF_GPIO_PAR_UART (0xA4036) 117#define MCF_GPIO_PAR_UART (0xA4036)
118#define MCF_GPIO_PAR_FECI2C (0xA4033) 118#define MCF_GPIO_PAR_FECI2C (0xA4033)
@@ -129,6 +129,13 @@
129#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 129#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
130 130
131/* 131/*
132 * UART module.
133 */
134#define MCFUART_BASE1 0x60000 /* Base address of UART1 */
135#define MCFUART_BASE2 0x64000 /* Base address of UART2 */
136#define MCFUART_BASE3 0x68000 /* Base address of UART2 */
137
138/*
132 * Reset Controll Unit. 139 * Reset Controll Unit.
133 */ 140 */
134#define MCF_RCR 0xFC0A0000 141#define MCF_RCR 0xFC0A0000
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 9d597dcb29c0..4ec0f93a7ece 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -52,6 +52,13 @@
52#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 52#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
53#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 53#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
54 54
55/*
56 * UART module.
57 */
58#define MCFUART_BASE1 0x200 /* Base address of UART1 */
59#define MCFUART_BASE2 0x240 /* Base address of UART2 */
60#define MCFUART_BASE3 0x280 /* Base address of UART3 */
61
55#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 62#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
56#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) 63#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
57#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) 64#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index c107228728db..21d0bbfbc0c9 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -59,6 +59,11 @@
59#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ 59#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
60#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ 60#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
61 61
62/*
63 * UART module.
64 */
65#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
66#define MCFUART_BASE2 0x200 /* Base address of UART2 */
62 67
63/* 68/*
64 * Some symbol defines for the above... 69 * Some symbol defines for the above...
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index 8cea714dee46..974c448c098e 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -65,6 +65,9 @@
65#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ 65#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
66#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ 66#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
67 67
68#define MCFUART_BASE1 0x100 /* Base address of UART1 */
69#define MCFUART_BASE2 0x140 /* Base address of UART2 */
70
68#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ 71#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
69#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ 72#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
70#define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */ 73#define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 5223b71d3432..8a5a1ab57d01 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -58,6 +58,12 @@
58#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ 58#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */
59#endif 59#endif
60 60
61/*
62 * UART module.
63 */
64#define MCFUART_BASE1 0x200 /* Base address of UART1 */
65#define MCFUART_BASE2 0x240 /* Base address of UART2 */
66#define MCFUART_BASE3 0x280 /* Base address of UART3 */
61 67
62#ifdef CONFIG_M5271 68#ifdef CONFIG_M5271
63#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 69#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 4e35f970f662..47c851ef78d3 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -44,6 +44,13 @@
44#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ 44#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
45 45
46/* 46/*
47 * UART module.
48 */
49#define MCFUART_BASE1 0x200 /* Base address of UART1 */
50#define MCFUART_BASE2 0x240 /* Base address of UART2 */
51#define MCFUART_BASE3 0x280 /* Base address of UART3 */
52
53/*
47 * GPIO registers 54 * GPIO registers
48 */ 55 */
49#define MCFGPIO_PORTA (MCF_IPSBAR + 0x00100000) 56#define MCFGPIO_PORTA (MCF_IPSBAR + 0x00100000)
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 008f36bd66c3..7003d7268ae8 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -97,6 +97,17 @@
97#define MCFSIM_PADAT (MCF_MBAR + 0x248) 97#define MCFSIM_PADAT (MCF_MBAR + 0x248)
98 98
99/* 99/*
100 * UART module.
101 */
102#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
103#define MCFUART_BASE1 0x200 /* Base address of UART1 */
104#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
105#else
106#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
107#define MCFUART_BASE2 0x200 /* Base address of UART2 */
108#endif
109
110/*
100 * Generic GPIO support 111 * Generic GPIO support
101 */ 112 */
102#define MCFGPIO_PIN_MAX 16 113#define MCFGPIO_PIN_MAX 16
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index b8126d3253e1..45c119c072db 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -103,6 +103,13 @@
103#define ACR_CM_OFF_IMP (3<<5) 103#define ACR_CM_OFF_IMP (3<<5)
104#define ACR_WPROTECT (1<<2) 104#define ACR_WPROTECT (1<<2)
105 105
106/*
107 * UART module.
108 */
109#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */
110#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
111#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */
112
106/********************************************************************* 113/*********************************************************************
107 * 114 *
108 * Reset Controller Module 115 * Reset Controller Module
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index e07d4d8cf31f..ddfff88629fe 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -76,6 +76,9 @@
76#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ 76#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
77#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ 77#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
78 78
79#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
80#define MCFUART_BASE2 0x200 /* Base address of UART2 */
81
79#define MCFSIM_PADDR (MCF_MBAR + 0x244) 82#define MCFSIM_PADDR (MCF_MBAR + 0x244)
80#define MCFSIM_PADAT (MCF_MBAR + 0x248) 83#define MCFSIM_PADAT (MCF_MBAR + 0x248)
81 84
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index 6072248916ac..a08a7ae776b1 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -25,6 +25,14 @@
25#define MCFINTC_ICR0 0x40 /* Base ICR register */ 25#define MCFINTC_ICR0 0x40 /* Base ICR register */
26 26
27/* 27/*
28 * UART module.
29 */
30#define MCFUART_BASE1 0x8600 /* Base address of UART1 */
31#define MCFUART_BASE2 0x8700 /* Base address of UART2 */
32#define MCFUART_BASE3 0x8800 /* Base address of UART3 */
33#define MCFUART_BASE4 0x8900 /* Base address of UART4 */
34
35/*
28 * Define system peripheral IRQ usage. 36 * Define system peripheral IRQ usage.
29 */ 37 */
30#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */ 38#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h
index c67dacad7c1c..2abedff0a694 100644
--- a/arch/m68k/include/asm/mcfuart.h
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -12,49 +12,6 @@
12#define mcfuart_h 12#define mcfuart_h
13/****************************************************************************/ 13/****************************************************************************/
14 14
15/*
16 * Define the base address of the UARTS within the MBAR address
17 * space.
18 */
19#if defined(CONFIG_M5272)
20#define MCFUART_BASE1 0x100 /* Base address of UART1 */
21#define MCFUART_BASE2 0x140 /* Base address of UART2 */
22#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e)
23#if defined(CONFIG_NETtel)
24#define MCFUART_BASE1 0x180 /* Base address of UART1 */
25#define MCFUART_BASE2 0x140 /* Base address of UART2 */
26#else
27#define MCFUART_BASE1 0x140 /* Base address of UART1 */
28#define MCFUART_BASE2 0x180 /* Base address of UART2 */
29#endif
30#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
31#define MCFUART_BASE1 0x200 /* Base address of UART1 */
32#define MCFUART_BASE2 0x240 /* Base address of UART2 */
33#define MCFUART_BASE3 0x280 /* Base address of UART3 */
34#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
35#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
36#define MCFUART_BASE1 0x200 /* Base address of UART1 */
37#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
38#else
39#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
40#define MCFUART_BASE2 0x200 /* Base address of UART2 */
41#endif
42#elif defined(CONFIG_M520x)
43#define MCFUART_BASE1 0x60000 /* Base address of UART1 */
44#define MCFUART_BASE2 0x64000 /* Base address of UART2 */
45#define MCFUART_BASE3 0x68000 /* Base address of UART2 */
46#elif defined(CONFIG_M532x)
47#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */
48#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */
49#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */
50#elif defined(CONFIG_M54xx)
51#define MCFUART_BASE1 0x8600 /* on M54xx */
52#define MCFUART_BASE2 0x8700 /* on M54xx */
53#define MCFUART_BASE3 0x8800 /* on M54xx */
54#define MCFUART_BASE4 0x8900 /* on M54xx */
55#endif
56
57
58#include <linux/serial_core.h> 15#include <linux/serial_core.h>
59#include <linux/platform_device.h> 16#include <linux/platform_device.h>
60 17