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authorLinus Torvalds <torvalds@linux-foundation.org>2012-03-21 21:17:51 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-03-21 21:17:51 -0400
commitb57cb7231b2ce52d3dda14a7b417ae125fb2eb97 (patch)
treeb6b3af0b2866f76fe5db80af678f4b3d54cc9b81 /arch/m68k/include
parentad12ab259d9131a53aa11c7c4561d97f7cc900df (diff)
parentae909ea4ad2431e085e6cc96446fbc1c1ae88498 (diff)
Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
Pull m68knommu arch updates from Greg Ungerer: "Includes a cleanup of the non-MMU linker script (it now almost exclusively uses the well defined linker script support macros and definitions). Some more merging of MMU and non-MMU common files (specifically the arch process.c, ptrace and time.c). And a big cleanup of the massively duplicated ColdFire device definition code. Overall we remove about 2000 lines of code, and end up with a single set of platform device definitions for the serial ports, ethernet ports and QSPI ports common in most ColdFire SoCs. I expect you will get a merge conflict on arch/m68k/kernel/process.c, in cpu_idle(). It should be relatively strait forward to fixup." And cpu_idle() conflict resolution was indeed trivial (merging the nommu/mmu versions of process.c trivially conflicting with the conversion to use the schedule_preempt_disabled() helper function) * 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (57 commits) m68knommu: factor more common ColdFire cpu reset code m68knommu: make 528x CPU reset register addressing consistent m68knommu: make 527x CPU reset register addressing consistent m68knommu: make 523x CPU reset register addressing consistent m68knommu: factor some common ColdFire cpu reset code m68knommu: move old ColdFire timers init from CPU init to timers code m68knommu: clean up init code in ColdFire 532x startup m68knommu: clean up init code in ColdFire 528x startup m68knommu: clean up init code in ColdFire 523x startup m68knommu: merge common ColdFire QSPI platform setup code m68knommu: make 532x QSPI platform addressing consistent m68knommu: make 528x QSPI platform addressing consistent m68knommu: make 527x QSPI platform addressing consistent m68knommu: make 5249 QSPI platform addressing consistent m68knommu: make 523x QSPI platform addressing consistent m68knommu: make 520x QSPI platform addressing consistent m68knommu: merge common ColdFire FEC platform setup code m68knommu: make 532x FEC platform addressing consistent m68knommu: make 528x FEC platform addressing consistent m68knommu: make 527x FEC platform addressing consistent ...
Diffstat (limited to 'arch/m68k/include')
-rw-r--r--arch/m68k/include/asm/m5206sim.h10
-rw-r--r--arch/m68k/include/asm/m520xsim.h33
-rw-r--r--arch/m68k/include/asm/m523xsim.h42
-rw-r--r--arch/m68k/include/asm/m5249sim.h18
-rw-r--r--arch/m68k/include/asm/m5272sim.h17
-rw-r--r--arch/m68k/include/asm/m527xsim.h53
-rw-r--r--arch/m68k/include/asm/m528xsim.h40
-rw-r--r--arch/m68k/include/asm/m5307sim.h10
-rw-r--r--arch/m68k/include/asm/m532xsim.h35
-rw-r--r--arch/m68k/include/asm/m5407sim.h6
-rw-r--r--arch/m68k/include/asm/m54xxsim.h16
-rw-r--r--arch/m68k/include/asm/machdep.h5
-rw-r--r--arch/m68k/include/asm/mcfqspi.h11
-rw-r--r--arch/m68k/include/asm/mcfuart.h5
14 files changed, 232 insertions, 69 deletions
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 9015eadd5c00..69722366b084 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -100,11 +100,11 @@
100#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */ 100#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
101 101
102#if defined(CONFIG_NETtel) 102#if defined(CONFIG_NETtel)
103#define MCFUART_BASE1 0x180 /* Base address of UART1 */ 103#define MCFUART_BASE0 (MCF_MBAR + 0x180) /* Base address UART0 */
104#define MCFUART_BASE2 0x140 /* Base address of UART2 */ 104#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
105#else 105#else
106#define MCFUART_BASE1 0x140 /* Base address of UART1 */ 106#define MCFUART_BASE0 (MCF_MBAR + 0x140) /* Base address UART0 */
107#define MCFUART_BASE2 0x180 /* Base address of UART2 */ 107#define MCFUART_BASE1 (MCF_MBAR + 0x180) /* Base address UART1 */
108#endif 108#endif
109 109
110/* 110/*
@@ -112,6 +112,8 @@
112 */ 112 */
113#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 113#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
114#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 114#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
115#define MCF_IRQ_UART0 73 /* UART0 */
116#define MCF_IRQ_UART1 74 /* UART1 */
115 117
116/* 118/*
117 * Generic GPIO 119 * Generic GPIO
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index eda62de7e607..17f2aab9cf97 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -48,8 +48,21 @@
48#define MCFINT_UART1 27 /* Interrupt number for UART1 */ 48#define MCFINT_UART1 27 /* Interrupt number for UART1 */
49#define MCFINT_UART2 28 /* Interrupt number for UART2 */ 49#define MCFINT_UART2 28 /* Interrupt number for UART2 */
50#define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 50#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
51#define MCFINT_FECRX0 36 /* Interrupt number for FEC RX */
52#define MCFINT_FECTX0 40 /* Interrupt number for FEC RX */
53#define MCFINT_FECENTC0 42 /* Interrupt number for FEC RX */
51#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ 54#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
52 55
56#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
57#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
58#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
59
60#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
61#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
62#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
63
64#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
65
53/* 66/*
54 * SDRAM configuration registers. 67 * SDRAM configuration registers.
55 */ 68 */
@@ -144,15 +157,25 @@
144/* 157/*
145 * UART module. 158 * UART module.
146 */ 159 */
147#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */ 160#define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */
148#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */ 161#define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */
149#define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */ 162#define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */
150 163
151/* 164/*
152 * FEC module. 165 * FEC module.
153 */ 166 */
154#define MCFFEC_BASE 0xFC030000 /* Base of FEC ethernet */ 167#define MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */
155#define MCFFEC_SIZE 0x800 /* Register set size */ 168#define MCFFEC_SIZE0 0x800 /* Register set size */
169
170/*
171 * QSPI module.
172 */
173#define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */
174#define MCFQSPI_SIZE 0x40 /* Register set size */
175
176#define MCFQSPI_CS0 46
177#define MCFQSPI_CS1 47
178#define MCFQSPI_CS2 27
156 179
157/* 180/*
158 * Reset Control Unit. 181 * Reset Control Unit.
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 6235921eca4e..075062d4eecd 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -35,8 +35,23 @@
35 35
36#define MCFINT_VECBASE 64 /* Vector base number */ 36#define MCFINT_VECBASE 64 /* Vector base number */
37#define MCFINT_UART0 13 /* Interrupt number for UART0 */ 37#define MCFINT_UART0 13 /* Interrupt number for UART0 */
38#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ 38#define MCFINT_UART1 14 /* Interrupt number for UART1 */
39#define MCFINT_UART2 15 /* Interrupt number for UART2 */
39#define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 40#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
41#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
42#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
43#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
44#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
45
46#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
47#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
48#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
49
50#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
51#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
52#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
53
54#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
40 55
41/* 56/*
42 * SDRAM configuration registers. 57 * SDRAM configuration registers.
@@ -50,8 +65,8 @@
50/* 65/*
51 * Reset Control Unit (relative to IPSBAR). 66 * Reset Control Unit (relative to IPSBAR).
52 */ 67 */
53#define MCF_RCR 0x110000 68#define MCF_RCR (MCF_IPSBAR + 0x110000)
54#define MCF_RSR 0x110001 69#define MCF_RSR (MCF_IPSBAR + 0x110001)
55 70
56#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 71#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
57#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 72#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
@@ -59,15 +74,26 @@
59/* 74/*
60 * UART module. 75 * UART module.
61 */ 76 */
62#define MCFUART_BASE1 (MCF_IPSBAR + 0x200) 77#define MCFUART_BASE0 (MCF_IPSBAR + 0x200)
63#define MCFUART_BASE2 (MCF_IPSBAR + 0x240) 78#define MCFUART_BASE1 (MCF_IPSBAR + 0x240)
64#define MCFUART_BASE3 (MCF_IPSBAR + 0x280) 79#define MCFUART_BASE2 (MCF_IPSBAR + 0x280)
65 80
66/* 81/*
67 * FEC ethernet module. 82 * FEC ethernet module.
68 */ 83 */
69#define MCFFEC_BASE (MCF_IPSBAR + 0x1000) 84#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000)
70#define MCFFEC_SIZE 0x800 85#define MCFFEC_SIZE0 0x800
86
87/*
88 * QSPI module.
89 */
90#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
91#define MCFQSPI_SIZE 0x40
92
93#define MCFQSPI_CS0 91
94#define MCFQSPI_CS1 92
95#define MCFQSPI_CS2 103
96#define MCFQSPI_CS3 99
71 97
72/* 98/*
73 * GPIO module. 99 * GPIO module.
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 805714ca8d7d..7f0c2c3660fd 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -76,8 +76,19 @@
76/* 76/*
77 * UART module. 77 * UART module.
78 */ 78 */
79#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ 79#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
80#define MCFUART_BASE2 0x200 /* Base address of UART2 */ 80#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
81
82/*
83 * QSPI module.
84 */
85#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
86#define MCFQSPI_SIZE 0x40 /* Register set size */
87
88#define MCFQSPI_CS0 29
89#define MCFQSPI_CS1 24
90#define MCFQSPI_CS2 21
91#define MCFQSPI_CS3 22
81 92
82/* 93/*
83 * DMA unit base addresses. 94 * DMA unit base addresses.
@@ -108,6 +119,9 @@
108#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 119#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
109#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 120#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
110 121
122#define MCF_IRQ_UART0 73 /* UART0 */
123#define MCF_IRQ_UART1 74 /* UART1 */
124
111/* 125/*
112 * General purpose IO registers (in MBAR2). 126 * General purpose IO registers (in MBAR2).
113 */ 127 */
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index 759c2b07a994..a58f1760d858 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -68,8 +68,8 @@
68#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ 68#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
69#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ 69#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
70 70
71#define MCFUART_BASE1 0x100 /* Base address of UART1 */ 71#define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */
72#define MCFUART_BASE2 0x140 /* Base address of UART2 */ 72#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
73 73
74#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ 74#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
75#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ 75#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
@@ -88,6 +88,9 @@
88#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */ 88#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
89#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */ 89#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
90 90
91#define MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */
92#define MCFFEC_SIZE0 0x1d0
93
91/* 94/*
92 * Define system peripheral IRQ usage. 95 * Define system peripheral IRQ usage.
93 */ 96 */
@@ -101,8 +104,8 @@
101#define MCF_IRQ_TIMER2 70 /* Timer 2 */ 104#define MCF_IRQ_TIMER2 70 /* Timer 2 */
102#define MCF_IRQ_TIMER3 71 /* Timer 3 */ 105#define MCF_IRQ_TIMER3 71 /* Timer 3 */
103#define MCF_IRQ_TIMER4 72 /* Timer 4 */ 106#define MCF_IRQ_TIMER4 72 /* Timer 4 */
104#define MCF_IRQ_UART1 73 /* UART 1 */ 107#define MCF_IRQ_UART0 73 /* UART 0 */
105#define MCF_IRQ_UART2 74 /* UART 2 */ 108#define MCF_IRQ_UART1 74 /* UART 1 */
106#define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */ 109#define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
107#define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */ 110#define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
108#define MCF_IRQ_USB0 77 /* USB Endpoint 0 */ 111#define MCF_IRQ_USB0 77 /* USB Endpoint 0 */
@@ -114,9 +117,9 @@
114#define MCF_IRQ_USB6 83 /* USB Endpoint 6 */ 117#define MCF_IRQ_USB6 83 /* USB Endpoint 6 */
115#define MCF_IRQ_USB7 84 /* USB Endpoint 7 */ 118#define MCF_IRQ_USB7 84 /* USB Endpoint 7 */
116#define MCF_IRQ_DMA 85 /* DMA Controller */ 119#define MCF_IRQ_DMA 85 /* DMA Controller */
117#define MCF_IRQ_ERX 86 /* Ethernet Receiver */ 120#define MCF_IRQ_FECRX0 86 /* Ethernet Receiver */
118#define MCF_IRQ_ETX 87 /* Ethernet Transmitter */ 121#define MCF_IRQ_FECTX0 87 /* Ethernet Transmitter */
119#define MCF_IRQ_ENTC 88 /* Ethernet Non-Time Critical */ 122#define MCF_IRQ_FECENTC0 88 /* Ethernet Non-Time Critical */
120#define MCF_IRQ_QSPI 89 /* Queued Serial Interface */ 123#define MCF_IRQ_QSPI 89 /* Queued Serial Interface */
121#define MCF_IRQ_EINT5 90 /* External Interrupt 5 */ 124#define MCF_IRQ_EINT5 90 /* External Interrupt 5 */
122#define MCF_IRQ_EINT6 91 /* External Interrupt 6 */ 125#define MCF_IRQ_EINT6 91 /* External Interrupt 6 */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 758810ef91ec..83db8106f50a 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -38,8 +38,29 @@
38#define MCFINT_UART1 14 /* Interrupt number for UART1 */ 38#define MCFINT_UART1 14 /* Interrupt number for UART1 */
39#define MCFINT_UART2 15 /* Interrupt number for UART2 */ 39#define MCFINT_UART2 15 /* Interrupt number for UART2 */
40#define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 40#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
41#define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */
42#define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */
43#define MCFINT_FECENTC0 29 /* Interrupt number for FEC0 */
41#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ 44#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
42 45
46#define MCFINT2_VECBASE 128 /* Vector base number 2 */
47#define MCFINT2_FECRX1 23 /* Interrupt number for FEC1 */
48#define MCFINT2_FECTX1 27 /* Interrupt number for FEC1 */
49#define MCFINT2_FECENTC1 29 /* Interrupt number for FEC1 */
50
51#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
52#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
53#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
54
55#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
56#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
57#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
58#define MCF_IRQ_FECRX1 (MCFINT2_VECBASE + MCFINT2_FECRX1)
59#define MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1)
60#define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1)
61
62#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
63
43/* 64/*
44 * SDRAM configuration registers. 65 * SDRAM configuration registers.
45 */ 66 */
@@ -72,9 +93,9 @@
72/* 93/*
73 * UART module. 94 * UART module.
74 */ 95 */
75#define MCFUART_BASE1 (MCF_IPSBAR + 0x200) 96#define MCFUART_BASE0 (MCF_IPSBAR + 0x200)
76#define MCFUART_BASE2 (MCF_IPSBAR + 0x240) 97#define MCFUART_BASE1 (MCF_IPSBAR + 0x240)
77#define MCFUART_BASE3 (MCF_IPSBAR + 0x280) 98#define MCFUART_BASE2 (MCF_IPSBAR + 0x280)
78 99
79/* 100/*
80 * FEC ethernet module. 101 * FEC ethernet module.
@@ -84,6 +105,28 @@
84#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800) 105#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800)
85#define MCFFEC_SIZE1 0x800 106#define MCFFEC_SIZE1 0x800
86 107
108/*
109 * QSPI module.
110 */
111#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
112#define MCFQSPI_SIZE 0x40
113
114#ifdef CONFIG_M5271
115#define MCFQSPI_CS0 91
116#define MCFQSPI_CS1 92
117#define MCFQSPI_CS2 99
118#define MCFQSPI_CS3 103
119#endif
120#ifdef CONFIG_M5275
121#define MCFQSPI_CS0 59
122#define MCFQSPI_CS1 60
123#define MCFQSPI_CS2 61
124#define MCFQSPI_CS3 62
125#endif
126
127/*
128 * GPIO module.
129 */
87#ifdef CONFIG_M5271 130#ifdef CONFIG_M5271
88#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 131#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
89#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) 132#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
@@ -285,8 +328,8 @@
285/* 328/*
286 * Reset Control Unit (relative to IPSBAR). 329 * Reset Control Unit (relative to IPSBAR).
287 */ 330 */
288#define MCF_RCR 0x110000 331#define MCF_RCR (MCF_IPSBAR + 0x110000)
289#define MCF_RSR 0x110001 332#define MCF_RSR (MCF_IPSBAR + 0x110001)
290 333
291#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 334#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
292#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 335#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index d798bd5df56c..569476fba18c 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -35,9 +35,24 @@
35 35
36#define MCFINT_VECBASE 64 /* Vector base number */ 36#define MCFINT_VECBASE 64 /* Vector base number */
37#define MCFINT_UART0 13 /* Interrupt number for UART0 */ 37#define MCFINT_UART0 13 /* Interrupt number for UART0 */
38#define MCFINT_UART1 14 /* Interrupt number for UART1 */
39#define MCFINT_UART2 15 /* Interrupt number for UART2 */
38#define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 40#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
41#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
42#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
43#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
39#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ 44#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
40 45
46#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
47#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
48#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
49
50#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
51#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
52#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
53
54#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
55
41/* 56/*
42 * SDRAM configuration registers. 57 * SDRAM configuration registers.
43 */ 58 */
@@ -58,15 +73,26 @@
58/* 73/*
59 * UART module. 74 * UART module.
60 */ 75 */
61#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000200) 76#define MCFUART_BASE0 (MCF_IPSBAR + 0x00000200)
62#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000240) 77#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000240)
63#define MCFUART_BASE3 (MCF_IPSBAR + 0x00000280) 78#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000280)
64 79
65/* 80/*
66 * FEC ethernet module. 81 * FEC ethernet module.
67 */ 82 */
68#define MCFFEC_BASE (MCF_IPSBAR + 0x00001000) 83#define MCFFEC_BASE0 (MCF_IPSBAR + 0x00001000)
69#define MCFFEC_SIZE 0x800 84#define MCFFEC_SIZE0 0x800
85
86/*
87 * QSPI module.
88 */
89#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340)
90#define MCFQSPI_SIZE 0x40
91
92#define MCFQSPI_CS0 147
93#define MCFQSPI_CS1 148
94#define MCFQSPI_CS2 149
95#define MCFQSPI_CS3 150
70 96
71/* 97/*
72 * GPIO registers 98 * GPIO registers
@@ -246,8 +272,8 @@
246/* 272/*
247 * Reset Control Unit (relative to IPSBAR). 273 * Reset Control Unit (relative to IPSBAR).
248 */ 274 */
249#define MCF_RCR 0x110000 275#define MCF_RCR (MCF_IPSBAR + 0x110000)
250#define MCF_RSR 0x110001 276#define MCF_RSR (MCF_IPSBAR + 0x110001)
251 277
252#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 278#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
253#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 279#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 8f8609fcc9b8..3bc3adaa7ee0 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -117,11 +117,11 @@
117 * UART module. 117 * UART module.
118 */ 118 */
119#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) 119#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
120#define MCFUART_BASE1 0x200 /* Base address of UART1 */ 120#define MCFUART_BASE0 (MCF_MBAR + 0x200) /* Base address UART0 */
121#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ 121#define MCFUART_BASE1 (MCF_MBAR + 0x1c0) /* Base address UART1 */
122#else 122#else
123#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ 123#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
124#define MCFUART_BASE2 0x200 /* Base address of UART2 */ 124#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
125#endif 125#endif
126 126
127/* 127/*
@@ -176,6 +176,8 @@
176 */ 176 */
177#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 177#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
178#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 178#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
179#define MCF_IRQ_UART0 73 /* UART0 */
180#define MCF_IRQ_UART1 74 /* UART1 */
179 181
180/****************************************************************************/ 182/****************************************************************************/
181#endif /* m5307sim_h */ 183#endif /* m5307sim_h */
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index ba4cc784f574..29b66e21413a 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -24,6 +24,19 @@
24#define MCFINT_UART1 27 /* Interrupt number for UART1 */ 24#define MCFINT_UART1 27 /* Interrupt number for UART1 */
25#define MCFINT_UART2 28 /* Interrupt number for UART2 */ 25#define MCFINT_UART2 28 /* Interrupt number for UART2 */
26#define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 26#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
27#define MCFINT_FECRX0 36 /* Interrupt number for FEC */
28#define MCFINT_FECTX0 40 /* Interrupt number for FEC */
29#define MCFINT_FECENTC0 42 /* Interrupt number for FEC */
30
31#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
32#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
33#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
34
35#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
36#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
37#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
38
39#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
27 40
28#define MCF_WTM_WCR MCF_REG16(0xFC098000) 41#define MCF_WTM_WCR MCF_REG16(0xFC098000)
29 42
@@ -82,9 +95,25 @@
82/* 95/*
83 * UART module. 96 * UART module.
84 */ 97 */
85#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */ 98#define MCFUART_BASE0 0xFC060000 /* Base address of UART1 */
86#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */ 99#define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */
87#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */ 100#define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */
101
102/*
103 * FEC module.
104 */
105#define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */
106#define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */
107
108/*
109 * QSPI module.
110 */
111#define MCFQSPI_BASE 0xFC058000 /* Base address of QSPI */
112#define MCFQSPI_SIZE 0x40 /* Size of QSPI region */
113
114#define MCFQSPI_CS0 84
115#define MCFQSPI_CS1 85
116#define MCFQSPI_CS2 86
88 117
89/* 118/*
90 * Timer module. 119 * Timer module.
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 51e00b00b8a6..79f58dd6a83d 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -85,8 +85,8 @@
85#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ 85#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
86#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ 86#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
87 87
88#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ 88#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
89#define MCFUART_BASE2 0x200 /* Base address of UART2 */ 89#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
90 90
91#define MCFSIM_PADDR (MCF_MBAR + 0x244) 91#define MCFSIM_PADDR (MCF_MBAR + 0x244)
92#define MCFSIM_PADAT (MCF_MBAR + 0x248) 92#define MCFSIM_PADAT (MCF_MBAR + 0x248)
@@ -139,6 +139,8 @@
139 */ 139 */
140#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 140#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
141#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 141#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
142#define MCF_IRQ_UART0 73 /* UART0 */
143#define MCF_IRQ_UART1 74 /* UART1 */
142 144
143/****************************************************************************/ 145/****************************************************************************/
144#endif /* m5407sim_h */ 146#endif /* m5407sim_h */
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index 1ed8bfb02772..ae56b8848a9d 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -31,16 +31,20 @@
31/* 31/*
32 * UART module. 32 * UART module.
33 */ 33 */
34#define MCFUART_BASE1 0x8600 /* Base address of UART1 */ 34#define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */
35#define MCFUART_BASE2 0x8700 /* Base address of UART2 */ 35#define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */
36#define MCFUART_BASE3 0x8800 /* Base address of UART3 */ 36#define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */
37#define MCFUART_BASE4 0x8900 /* Base address of UART4 */ 37#define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */
38 38
39/* 39/*
40 * Define system peripheral IRQ usage. 40 * Define system peripheral IRQ usage.
41 */ 41 */
42#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */ 42#define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */
43#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */ 43#define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */
44#define MCF_IRQ_UART0 (MCFINT_VECBASE + 35)
45#define MCF_IRQ_UART1 (MCFINT_VECBASE + 34)
46#define MCF_IRQ_UART2 (MCFINT_VECBASE + 33)
47#define MCF_IRQ_UART3 (MCFINT_VECBASE + 32)
44 48
45/* 49/*
46 * Generic GPIO support 50 * Generic GPIO support
diff --git a/arch/m68k/include/asm/machdep.h b/arch/m68k/include/asm/machdep.h
index 789f3b2de0e9..825c1c813196 100644
--- a/arch/m68k/include/asm/machdep.h
+++ b/arch/m68k/include/asm/machdep.h
@@ -22,8 +22,6 @@ extern unsigned int (*mach_get_ss)(void);
22extern int (*mach_get_rtc_pll)(struct rtc_pll_info *); 22extern int (*mach_get_rtc_pll)(struct rtc_pll_info *);
23extern int (*mach_set_rtc_pll)(struct rtc_pll_info *); 23extern int (*mach_set_rtc_pll)(struct rtc_pll_info *);
24extern int (*mach_set_clock_mmss)(unsigned long); 24extern int (*mach_set_clock_mmss)(unsigned long);
25extern void (*mach_gettod)(int *year, int *mon, int *day, int *hour,
26 int *min, int *sec);
27extern void (*mach_reset)( void ); 25extern void (*mach_reset)( void );
28extern void (*mach_halt)( void ); 26extern void (*mach_halt)( void );
29extern void (*mach_power_off)( void ); 27extern void (*mach_power_off)( void );
@@ -35,9 +33,8 @@ extern void (*mach_l2_flush) (int);
35extern void (*mach_beep) (unsigned int, unsigned int); 33extern void (*mach_beep) (unsigned int, unsigned int);
36 34
37/* Hardware clock functions */ 35/* Hardware clock functions */
38extern void hw_timer_init(void); 36extern void hw_timer_init(irq_handler_t handler);
39extern unsigned long hw_timer_offset(void); 37extern unsigned long hw_timer_offset(void);
40extern irqreturn_t arch_timer_interrupt(int irq, void *dummy);
41 38
42extern void config_BSP(char *command, int len); 39extern void config_BSP(char *command, int len);
43 40
diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h
index 7fe631972f1f..7b51416ccae2 100644
--- a/arch/m68k/include/asm/mcfqspi.h
+++ b/arch/m68k/include/asm/mcfqspi.h
@@ -21,17 +21,6 @@
21#ifndef mcfqspi_h 21#ifndef mcfqspi_h
22#define mcfqspi_h 22#define mcfqspi_h
23 23
24#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
25#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340)
26#elif defined(CONFIG_M5249)
27#define MCFQSPI_IOBASE (MCF_MBAR + 0x300)
28#elif defined(CONFIG_M520x)
29#define MCFQSPI_IOBASE 0xFC05C000
30#elif defined(CONFIG_M532x)
31#define MCFQSPI_IOBASE 0xFC058000
32#endif
33#define MCFQSPI_IOSIZE 0x40
34
35/** 24/**
36 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver 25 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
37 * @setup: setup the control; allocate gpio's, etc. May be NULL. 26 * @setup: setup the control; allocate gpio's, etc. May be NULL.
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h
index 2abedff0a694..2d3bc774b3c5 100644
--- a/arch/m68k/include/asm/mcfuart.h
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -41,7 +41,10 @@ struct mcf_platform_uart {
41#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ 41#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
42#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ 42#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
43#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ 43#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
44#else 44#endif
45#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
46 defined(CONFIG_M5249) || defined(CONFIG_M5307) || \
47 defined(CONFIG_M5407)
45#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ 48#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
46#endif 49#endif
47#define MCFUART_UIPR 0x34 /* Input Port (r) */ 50#define MCFUART_UIPR 0x34 /* Input Port (r) */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-24 03:13:35 -0500