m68knommu: create optimal separate instruction and data cache for ColdFire

Create separate functions to deal with instruction and data cache flushing.
This way we can optimize them for the vairous cache types and arrangements
used across the ColdFire family.

For example the unified caches in the version 3 cores means we don't
need to flush the instruction cache. For the version 2 cores that do
not do data cacheing (or where we choose instruction cache only) we
don't need to do any data flushing.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

1 files changed, 26 insertions, 1 deletions

diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h
index d8b8dd68368f..cd952b0a8bd3 100644
--- a/arch/m68k/include/asm/m53xxacr.h
+++ b/arch/m68k/include/asm/m53xxacr.h
@@ -49,12 +49,29 @@
 #define ACR_WPROTECT    0x00000004      /* Write protect region */
 
 /*
+ * Define the cache type and arrangement (needed for pushes).
+ */
+#if defined(CONFIG_M5307)
+#define CACHE_SIZE      0x2000          /* 8k of unified cache */
+#define ICACHE_SIZE     CACHE_SIZE
+#define DCACHE_SIZE     CACHE_SIZE
+#elif defined(CONFIG_M532x)
+#define CACHE_SIZE      0x4000          /* 32k of unified cache */
+#define ICACHE_SIZE     CACHE_SIZE
+#define DCACHE_SIZE     CACHE_SIZE
+#endif
+
+#define CACHE_LINE_SIZE 16              /* 16 byte line size */
+#define CACHE_WAYS      4               /* 4 ways - set associative */
+
+/*
  * Set the cache controller settings we will use. This default in the
  * CACR is cache inhibited, we use the ACR register to set cacheing
  * enabled on the regions we want (eg RAM).
  */
 #if defined(CONFIG_CACHE_COPYBACK)
 #define CACHE_TYPE      ACR_CM_CB
+#define CACHE_PUSH
 #else
 #define CACHE_TYPE      ACR_CM_WT
 #endif
@@ -65,7 +82,15 @@
 #define CACHE_MODE      (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP)
 #endif
 
-#define CACHE_INIT      CACR_CINVA
+/*
+ * Unified cache means we will never need to flush for coherency of
+ * instruction fetch. We will need to flush to maintain memory/DMA
+ * coherency though in all cases. And for copyback caches we will need
+ * to push cached data as well.
+ */
+#define CACHE_INIT        CACR_CINVA
+#define CACHE_INVALIDATE  CACR_CINVA
+#define CACHE_INVALIDATED CACR_CINVA
 
 #define ACR0_MODE       ((CONFIG_RAMBASE & 0xff000000) + \
                          (0x000f0000) + \