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authorLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-30 21:57:33 -0400
committerLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-31 10:26:23 -0400
commit25985edcedea6396277003854657b5f3cb31a628 (patch)
treef026e810210a2ee7290caeb737c23cb6472b7c38 /arch/m68k/include/asm/m5307sim.h
parent6aba74f2791287ec407e0f92487a725a25908067 (diff)
Fix common misspellings
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
Diffstat (limited to 'arch/m68k/include/asm/m5307sim.h')
-rw-r--r--arch/m68k/include/asm/m5307sim.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 4c94c01f36c4..8f8609fcc9b8 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -29,7 +29,7 @@
29#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ 29#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
30#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ 30#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
31#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ 31#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
32#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/ 32#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/
33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ 33#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ 34#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ 35#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */