diff options
author | Ingo Molnar <mingo@kernel.org> | 2012-03-26 11:18:44 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@kernel.org> | 2012-03-26 11:19:03 -0400 |
commit | 7fd52392c56361a40f0c630a82b36b95ca31eac6 (patch) | |
tree | 14091de24c6b28ea4cae9826f98aeedb7be091f5 /arch/m68k/include/asm/m5249sim.h | |
parent | b01c3a0010aabadf745f3e7fdb9cab682e0a28a2 (diff) | |
parent | e22057c8599373e5caef0bc42bdb95d2a361ab0d (diff) |
Merge branch 'linus' into perf/urgent
Merge reason: we need to fix a non-trivial merge conflict.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/m68k/include/asm/m5249sim.h')
-rw-r--r-- | arch/m68k/include/asm/m5249sim.h | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index 805714ca8d7d..7f0c2c3660fd 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h | |||
@@ -76,8 +76,19 @@ | |||
76 | /* | 76 | /* |
77 | * UART module. | 77 | * UART module. |
78 | */ | 78 | */ |
79 | #define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ | 79 | #define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ |
80 | #define MCFUART_BASE2 0x200 /* Base address of UART2 */ | 80 | #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ |
81 | |||
82 | /* | ||
83 | * QSPI module. | ||
84 | */ | ||
85 | #define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */ | ||
86 | #define MCFQSPI_SIZE 0x40 /* Register set size */ | ||
87 | |||
88 | #define MCFQSPI_CS0 29 | ||
89 | #define MCFQSPI_CS1 24 | ||
90 | #define MCFQSPI_CS2 21 | ||
91 | #define MCFQSPI_CS3 22 | ||
81 | 92 | ||
82 | /* | 93 | /* |
83 | * DMA unit base addresses. | 94 | * DMA unit base addresses. |
@@ -108,6 +119,9 @@ | |||
108 | #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ | 119 | #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ |
109 | #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ | 120 | #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ |
110 | 121 | ||
122 | #define MCF_IRQ_UART0 73 /* UART0 */ | ||
123 | #define MCF_IRQ_UART1 74 /* UART1 */ | ||
124 | |||
111 | /* | 125 | /* |
112 | * General purpose IO registers (in MBAR2). | 126 | * General purpose IO registers (in MBAR2). |
113 | */ | 127 | */ |