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authorLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-30 21:57:33 -0400
committerLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-31 10:26:23 -0400
commit25985edcedea6396277003854657b5f3cb31a628 (patch)
treef026e810210a2ee7290caeb737c23cb6472b7c38 /arch/m68k/ifpsp060/src/fpsp.S
parent6aba74f2791287ec407e0f92487a725a25908067 (diff)
Fix common misspellings
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
Diffstat (limited to 'arch/m68k/ifpsp060/src/fpsp.S')
-rw-r--r--arch/m68k/ifpsp060/src/fpsp.S10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/m68k/ifpsp060/src/fpsp.S b/arch/m68k/ifpsp060/src/fpsp.S
index 26e85e2b7a5e..78cb60f5bb4d 100644
--- a/arch/m68k/ifpsp060/src/fpsp.S
+++ b/arch/m68k/ifpsp060/src/fpsp.S
@@ -11813,7 +11813,7 @@ fmul_unfl_ena:
11813 bne.b fmul_unfl_ena_sd # no, sgl or dbl 11813 bne.b fmul_unfl_ena_sd # no, sgl or dbl
11814 11814
11815# if the rnd mode is anything but RZ, then we have to re-do the above 11815# if the rnd mode is anything but RZ, then we have to re-do the above
11816# multiplication becuase we used RZ for all. 11816# multiplication because we used RZ for all.
11817 fmov.l L_SCR3(%a6),%fpcr # set FPCR 11817 fmov.l L_SCR3(%a6),%fpcr # set FPCR
11818 11818
11819fmul_unfl_ena_cont: 11819fmul_unfl_ena_cont:
@@ -18095,7 +18095,7 @@ fscc_mem_op:
18095 18095
18096 rts 18096 rts
18097 18097
18098# addresing mode is post-increment. write the result byte. if the write 18098# addressing mode is post-increment. write the result byte. if the write
18099# fails then don't update the address register. if write passes then 18099# fails then don't update the address register. if write passes then
18100# call inc_areg() to update the address register. 18100# call inc_areg() to update the address register.
18101fscc_mem_inc: 18101fscc_mem_inc:
@@ -20876,7 +20876,7 @@ dst_get_dupper:
20876 swap %d0 # d0 now in upper word 20876 swap %d0 # d0 now in upper word
20877 lsl.l &0x4,%d0 # d0 in proper place for dbl prec exp 20877 lsl.l &0x4,%d0 # d0 in proper place for dbl prec exp
20878 tst.b FTEMP_EX(%a0) # test sign 20878 tst.b FTEMP_EX(%a0) # test sign
20879 bpl.b dst_get_dman # if postive, go process mantissa 20879 bpl.b dst_get_dman # if positive, go process mantissa
20880 bset &0x1f,%d0 # if negative, set sign 20880 bset &0x1f,%d0 # if negative, set sign
20881dst_get_dman: 20881dst_get_dman:
20882 mov.l FTEMP_HI(%a0),%d1 # get ms mantissa 20882 mov.l FTEMP_HI(%a0),%d1 # get ms mantissa
@@ -22943,7 +22943,7 @@ tbl_ovfl_result:
22943# FP_SRC(a6) = packed operand now as a binary FP number # 22943# FP_SRC(a6) = packed operand now as a binary FP number #
22944# # 22944# #
22945# ALGORITHM *********************************************************** # 22945# ALGORITHM *********************************************************** #
22946# Get the correct <ea> whihc is the value on the exception stack # 22946# Get the correct <ea> which is the value on the exception stack #
22947# frame w/ maybe a correction factor if the <ea> is -(an) or (an)+. # 22947# frame w/ maybe a correction factor if the <ea> is -(an) or (an)+. #
22948# Then, fetch the operand from memory. If the fetch fails, exit # 22948# Then, fetch the operand from memory. If the fetch fails, exit #
22949# through facc_in_x(). # 22949# through facc_in_x(). #
@@ -24096,7 +24096,7 @@ do_fint12:
24096# A6. This test occurs only on the first pass. If the 24096# A6. This test occurs only on the first pass. If the
24097# result is exactly 10^LEN, decrement ILOG and divide 24097# result is exactly 10^LEN, decrement ILOG and divide
24098# the mantissa by 10. The calculation of 10^LEN cannot 24098# the mantissa by 10. The calculation of 10^LEN cannot
24099# be inexact, since all powers of ten upto 10^27 are exact 24099# be inexact, since all powers of ten up to 10^27 are exact
24100# in extended precision, so the use of a previous power-of-ten 24100# in extended precision, so the use of a previous power-of-ten
24101# table will introduce no error. 24101# table will introduce no error.
24102# 24102#