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authorThomas Gleixner <tglx@linutronix.de>2011-01-19 11:41:51 -0500
committerThomas Gleixner <tglx@linutronix.de>2011-01-21 05:55:27 -0500
commit63b549b6552c7869c25a1c60783aa86a3380e06c (patch)
treea064077922d71f1cba1578b2e086b809a9929e25 /arch/m32r
parent364a9ba07b0341c7e16809d810a19e06b6e64b05 (diff)
m32r: Convert m32700ut pld irq chip
Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Hirokazu Takata <takata@linux-m32r.org> Cc: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/m32r')
-rw-r--r--arch/m32r/platforms/m32700ut/setup.c48
1 files changed, 20 insertions, 28 deletions
diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c
index 812cea993585..99d92411e84f 100644
--- a/arch/m32r/platforms/m32700ut/setup.c
+++ b/arch/m32r/platforms/m32700ut/setup.c
@@ -90,7 +90,6 @@ static void disable_m32700ut_pld_irq(unsigned int irq)
90 unsigned int pldirq; 90 unsigned int pldirq;
91 91
92 pldirq = irq2pldirq(irq); 92 pldirq = irq2pldirq(irq);
93// disable_m32700ut_irq(M32R_IRQ_INT1);
94 port = pldirq2port(pldirq); 93 port = pldirq2port(pldirq);
95 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7; 94 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
96 outw(data, port); 95 outw(data, port);
@@ -102,50 +101,38 @@ static void enable_m32700ut_pld_irq(unsigned int irq)
102 unsigned int pldirq; 101 unsigned int pldirq;
103 102
104 pldirq = irq2pldirq(irq); 103 pldirq = irq2pldirq(irq);
105// enable_m32700ut_irq(M32R_IRQ_INT1);
106 port = pldirq2port(pldirq); 104 port = pldirq2port(pldirq);
107 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6; 105 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
108 outw(data, port); 106 outw(data, port);
109} 107}
110 108
111static void mask_and_ack_m32700ut_pld(unsigned int irq) 109static void mask_m32700ut_pld(struct irq_data *data)
112{ 110{
113 disable_m32700ut_pld_irq(irq); 111 disable_m32700ut_pld_irq(data->irq);
114// mask_and_ack_m32700ut(M32R_IRQ_INT1);
115} 112}
116 113
117static void end_m32700ut_pld_irq(unsigned int irq) 114static void unmask_m32700ut_pld(struct irq_data *data)
118{ 115{
119 enable_m32700ut_pld_irq(irq); 116 enable_m32700ut_pld_irq(data->irq);
120 enable_m32700ut_irq(M32R_IRQ_INT1); 117 enable_m32700ut_irq(M32R_IRQ_INT1);
121} 118}
122 119
123static unsigned int startup_m32700ut_pld_irq(unsigned int irq) 120static void shutdown_m32700ut_pld_irq(struct irq_data *data)
124{
125 enable_m32700ut_pld_irq(irq);
126 return (0);
127}
128
129static void shutdown_m32700ut_pld_irq(unsigned int irq)
130{ 121{
131 unsigned long port; 122 unsigned long port;
132 unsigned int pldirq; 123 unsigned int pldirq;
133 124
134 pldirq = irq2pldirq(irq); 125 pldirq = irq2pldirq(data->irq);
135// shutdown_m32700ut_irq(M32R_IRQ_INT1);
136 port = pldirq2port(pldirq); 126 port = pldirq2port(pldirq);
137 outw(PLD_ICUCR_ILEVEL7, port); 127 outw(PLD_ICUCR_ILEVEL7, port);
138} 128}
139 129
140static struct irq_chip m32700ut_pld_irq_type = 130static struct irq_chip m32700ut_pld_irq_type =
141{ 131{
142 .name = "M32700UT-PLD-IRQ", 132 .name = "M32700UT-PLD-IRQ",
143 .startup = startup_m32700ut_pld_irq, 133 .irq_shutdown = shutdown_m32700ut_pld_irq,
144 .shutdown = shutdown_m32700ut_pld_irq, 134 .irq_mask = mask_m32700ut_pld,
145 .enable = enable_m32700ut_pld_irq, 135 .irq_unmask = unmask_m32700ut_pld,
146 .disable = disable_m32700ut_pld_irq,
147 .ack = mask_and_ack_m32700ut_pld,
148 .end = end_m32700ut_pld_irq
149}; 136};
150 137
151/* 138/*
@@ -333,28 +320,33 @@ void __init init_IRQ(void)
333 320
334#ifdef CONFIG_SERIAL_M32R_PLDSIO 321#ifdef CONFIG_SERIAL_M32R_PLDSIO
335 /* INT#1: SIO0 Receive on PLD */ 322 /* INT#1: SIO0 Receive on PLD */
336 set_irq_chip(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type); 323 set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
324 handle_level_irq);
337 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 325 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
338 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV); 326 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
339 327
340 /* INT#1: SIO0 Send on PLD */ 328 /* INT#1: SIO0 Send on PLD */
341 set_irq_chip(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type); 329 set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
330 handle_level_irq);
342 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 331 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
343 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND); 332 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
344#endif /* CONFIG_SERIAL_M32R_PLDSIO */ 333#endif /* CONFIG_SERIAL_M32R_PLDSIO */
345 334
346 /* INT#1: CFC IREQ on PLD */ 335 /* INT#1: CFC IREQ on PLD */
347 set_irq_chip(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type); 336 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
337 handle_level_irq);
348 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ 338 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
349 disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ); 339 disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
350 340
351 /* INT#1: CFC Insert on PLD */ 341 /* INT#1: CFC Insert on PLD */
352 set_irq_chip(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type); 342 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
343 handle_level_irq);
353 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ 344 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
354 disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT); 345 disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
355 346
356 /* INT#1: CFC Eject on PLD */ 347 /* INT#1: CFC Eject on PLD */
357 set_irq_chip(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type); 348 set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
349 handle_level_irq);
358 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ 350 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
359 disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT); 351 disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
360 352