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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /arch/m32r
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'arch/m32r')
-rw-r--r--arch/m32r/Kconfig24
-rw-r--r--arch/m32r/Kconfig.debug9
-rw-r--r--arch/m32r/configs/m32700ut.smp_defconfig2
-rw-r--r--arch/m32r/configs/m32700ut.up_defconfig2
-rw-r--r--arch/m32r/configs/mappi.nommu_defconfig2
-rw-r--r--arch/m32r/configs/mappi.smp_defconfig2
-rw-r--r--arch/m32r/configs/mappi.up_defconfig2
-rw-r--r--arch/m32r/configs/mappi2.opsp_defconfig2
-rw-r--r--arch/m32r/configs/mappi2.vdec2_defconfig2
-rw-r--r--arch/m32r/configs/mappi3.smp_defconfig2
-rw-r--r--arch/m32r/configs/oaks32r_defconfig2
-rw-r--r--arch/m32r/configs/opsput_defconfig2
-rw-r--r--arch/m32r/configs/usrv_defconfig2
-rw-r--r--arch/m32r/include/asm/bitops.h3
-rw-r--r--arch/m32r/include/asm/ioctls.h83
-rw-r--r--arch/m32r/include/asm/irqflags.h104
-rw-r--r--arch/m32r/include/asm/m32104ut/m32104ut_pld.h2
-rw-r--r--arch/m32r/include/asm/m32700ut/m32700ut_pld.h2
-rw-r--r--arch/m32r/include/asm/mmzone.h8
-rw-r--r--arch/m32r/include/asm/opsput/opsput_pld.h2
-rw-r--r--arch/m32r/include/asm/pgtable-2level.h2
-rw-r--r--arch/m32r/include/asm/pgtable.h2
-rw-r--r--arch/m32r/include/asm/smp.h6
-rw-r--r--arch/m32r/include/asm/system.h66
-rw-r--r--arch/m32r/include/asm/thread_info.h13
-rw-r--r--arch/m32r/include/asm/types.h9
-rw-r--r--arch/m32r/include/asm/unistd.h3
-rw-r--r--arch/m32r/kernel/irq.c45
-rw-r--r--arch/m32r/kernel/ptrace.c11
-rw-r--r--arch/m32r/kernel/smp.c68
-rw-r--r--arch/m32r/kernel/smpboot.c48
-rw-r--r--arch/m32r/kernel/syscall_table.S1
-rw-r--r--arch/m32r/kernel/time.c5
-rw-r--r--arch/m32r/kernel/vmlinux.lds.S3
-rw-r--r--arch/m32r/mm/discontig.c1
-rw-r--r--arch/m32r/mm/fault.c4
-rw-r--r--arch/m32r/mm/init.c2
-rw-r--r--arch/m32r/platforms/m32104ut/setup.c58
-rw-r--r--arch/m32r/platforms/m32700ut/setup.c214
-rw-r--r--arch/m32r/platforms/mappi/setup.c78
-rw-r--r--arch/m32r/platforms/mappi2/setup.c89
-rw-r--r--arch/m32r/platforms/mappi3/setup.c92
-rw-r--r--arch/m32r/platforms/oaks32r/setup.c65
-rw-r--r--arch/m32r/platforms/opsput/setup.c220
-rw-r--r--arch/m32r/platforms/usrv/setup.c115
45 files changed, 520 insertions, 959 deletions
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
index 836abbbc9c04..85b44e858225 100644
--- a/arch/m32r/Kconfig
+++ b/arch/m32r/Kconfig
@@ -1,10 +1,3 @@
1#
2# For a description of the syntax of this configuration file,
3# see Documentation/kbuild/kconfig-language.txt.
4#
5
6mainmenu "Linux/M32R Kernel Configuration"
7
8config M32R 1config M32R
9 bool 2 bool
10 default y 3 default y
@@ -14,6 +7,9 @@ config M32R
14 select HAVE_KERNEL_GZIP 7 select HAVE_KERNEL_GZIP
15 select HAVE_KERNEL_BZIP2 8 select HAVE_KERNEL_BZIP2
16 select HAVE_KERNEL_LZMA 9 select HAVE_KERNEL_LZMA
10 select HAVE_GENERIC_HARDIRQS
11 select GENERIC_IRQ_PROBE
12 select GENERIC_IRQ_SHOW
17 13
18config SBUS 14config SBUS
19 bool 15 bool
@@ -26,14 +22,6 @@ config ZONE_DMA
26 bool 22 bool
27 default y 23 default y
28 24
29config GENERIC_HARDIRQS
30 bool
31 default y
32
33config GENERIC_IRQ_PROBE
34 bool
35 default y
36
37config NO_IOPORT 25config NO_IOPORT
38 def_bool y 26 def_bool y
39 27
@@ -268,10 +256,6 @@ config ARCH_HAS_ILOG2_U64
268 bool 256 bool
269 default n 257 default n
270 258
271config GENERIC_FIND_NEXT_BIT
272 bool
273 default y
274
275config GENERIC_HWEIGHT 259config GENERIC_HWEIGHT
276 bool 260 bool
277 default y 261 default y
@@ -315,7 +299,7 @@ config SMP
315 Management" code will be disabled if you say Y here. 299 Management" code will be disabled if you say Y here.
316 300
317 See also the SMP-HOWTO available at 301 See also the SMP-HOWTO available at
318 <http://www.linuxdoc.org/docs.html#howto>. 302 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
319 303
320 If you don't know what to do here, say N. 304 If you don't know what to do here, say N.
321 305
diff --git a/arch/m32r/Kconfig.debug b/arch/m32r/Kconfig.debug
index 2e1019ddbb22..bb1afc1a31cc 100644
--- a/arch/m32r/Kconfig.debug
+++ b/arch/m32r/Kconfig.debug
@@ -9,15 +9,6 @@ config DEBUG_STACKOVERFLOW
9 This option will cause messages to be printed if free stack space 9 This option will cause messages to be printed if free stack space
10 drops below a certain limit. 10 drops below a certain limit.
11 11
12config DEBUG_STACK_USAGE
13 bool "Stack utilization instrumentation"
14 depends on DEBUG_KERNEL
15 help
16 Enables the display of the minimum amount of free stack which each
17 task has ever had available in the sysrq-T and sysrq-P debug output.
18
19 This option will slow down process creation somewhat.
20
21config DEBUG_PAGEALLOC 12config DEBUG_PAGEALLOC
22 bool "Debug page memory allocations" 13 bool "Debug page memory allocations"
23 depends on DEBUG_KERNEL && BROKEN 14 depends on DEBUG_KERNEL && BROKEN
diff --git a/arch/m32r/configs/m32700ut.smp_defconfig b/arch/m32r/configs/m32700ut.smp_defconfig
index 816c3ecaa2aa..a3d727ed6a16 100644
--- a/arch/m32r/configs/m32700ut.smp_defconfig
+++ b/arch/m32r/configs/m32700ut.smp_defconfig
@@ -5,7 +5,7 @@ CONFIG_IKCONFIG=y
5CONFIG_IKCONFIG_PROC=y 5CONFIG_IKCONFIG_PROC=y
6CONFIG_LOG_BUF_SHIFT=15 6CONFIG_LOG_BUF_SHIFT=15
7# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 7# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
8CONFIG_EMBEDDED=y 8CONFIG_EXPERT=y
9# CONFIG_KALLSYMS is not set 9# CONFIG_KALLSYMS is not set
10# CONFIG_FUTEX is not set 10# CONFIG_FUTEX is not set
11# CONFIG_EPOLL is not set 11# CONFIG_EPOLL is not set
diff --git a/arch/m32r/configs/m32700ut.up_defconfig b/arch/m32r/configs/m32700ut.up_defconfig
index 84785686640a..b8334163099d 100644
--- a/arch/m32r/configs/m32700ut.up_defconfig
+++ b/arch/m32r/configs/m32700ut.up_defconfig
@@ -5,7 +5,7 @@ CONFIG_IKCONFIG=y
5CONFIG_IKCONFIG_PROC=y 5CONFIG_IKCONFIG_PROC=y
6CONFIG_LOG_BUF_SHIFT=14 6CONFIG_LOG_BUF_SHIFT=14
7# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 7# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
8CONFIG_EMBEDDED=y 8CONFIG_EXPERT=y
9# CONFIG_KALLSYMS is not set 9# CONFIG_KALLSYMS is not set
10# CONFIG_FUTEX is not set 10# CONFIG_FUTEX is not set
11# CONFIG_EPOLL is not set 11# CONFIG_EPOLL is not set
diff --git a/arch/m32r/configs/mappi.nommu_defconfig b/arch/m32r/configs/mappi.nommu_defconfig
index 354a964d084d..7c90ce2fc42b 100644
--- a/arch/m32r/configs/mappi.nommu_defconfig
+++ b/arch/m32r/configs/mappi.nommu_defconfig
@@ -3,7 +3,7 @@ CONFIG_BSD_PROCESS_ACCT=y
3CONFIG_IKCONFIG=y 3CONFIG_IKCONFIG=y
4CONFIG_LOG_BUF_SHIFT=14 4CONFIG_LOG_BUF_SHIFT=14
5# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 5# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
6CONFIG_EMBEDDED=y 6CONFIG_EXPERT=y
7# CONFIG_KALLSYMS is not set 7# CONFIG_KALLSYMS is not set
8# CONFIG_FUTEX is not set 8# CONFIG_FUTEX is not set
9# CONFIG_EPOLL is not set 9# CONFIG_EPOLL is not set
diff --git a/arch/m32r/configs/mappi.smp_defconfig b/arch/m32r/configs/mappi.smp_defconfig
index 9022307bd073..367d07cebcd3 100644
--- a/arch/m32r/configs/mappi.smp_defconfig
+++ b/arch/m32r/configs/mappi.smp_defconfig
@@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=15 5CONFIG_LOG_BUF_SHIFT=15
6CONFIG_BLK_DEV_INITRD=y 6CONFIG_BLK_DEV_INITRD=y
7# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 7# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
8CONFIG_EMBEDDED=y 8CONFIG_EXPERT=y
9# CONFIG_KALLSYMS is not set 9# CONFIG_KALLSYMS is not set
10# CONFIG_FUTEX is not set 10# CONFIG_FUTEX is not set
11# CONFIG_EPOLL is not set 11# CONFIG_EPOLL is not set
diff --git a/arch/m32r/configs/mappi.up_defconfig b/arch/m32r/configs/mappi.up_defconfig
index 3726068721a5..cb11384386ce 100644
--- a/arch/m32r/configs/mappi.up_defconfig
+++ b/arch/m32r/configs/mappi.up_defconfig
@@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=14 5CONFIG_LOG_BUF_SHIFT=14
6CONFIG_BLK_DEV_INITRD=y 6CONFIG_BLK_DEV_INITRD=y
7# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 7# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
8CONFIG_EMBEDDED=y 8CONFIG_EXPERT=y
9# CONFIG_KALLSYMS is not set 9# CONFIG_KALLSYMS is not set
10# CONFIG_FUTEX is not set 10# CONFIG_FUTEX is not set
11# CONFIG_EPOLL is not set 11# CONFIG_EPOLL is not set
diff --git a/arch/m32r/configs/mappi2.opsp_defconfig b/arch/m32r/configs/mappi2.opsp_defconfig
index 6136fad048e4..3bff779259b4 100644
--- a/arch/m32r/configs/mappi2.opsp_defconfig
+++ b/arch/m32r/configs/mappi2.opsp_defconfig
@@ -4,7 +4,7 @@ CONFIG_BSD_PROCESS_ACCT=y
4CONFIG_IKCONFIG=y 4CONFIG_IKCONFIG=y
5CONFIG_LOG_BUF_SHIFT=14 5CONFIG_LOG_BUF_SHIFT=14
6# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 6# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
7CONFIG_EMBEDDED=y 7CONFIG_EXPERT=y
8# CONFIG_KALLSYMS is not set 8# CONFIG_KALLSYMS is not set
9# CONFIG_FUTEX is not set 9# CONFIG_FUTEX is not set
10# CONFIG_EPOLL is not set 10# CONFIG_EPOLL is not set
diff --git a/arch/m32r/configs/mappi2.vdec2_defconfig b/arch/m32r/configs/mappi2.vdec2_defconfig
index dce1fc7d67ed..75246c9c1af8 100644
--- a/arch/m32r/configs/mappi2.vdec2_defconfig
+++ b/arch/m32r/configs/mappi2.vdec2_defconfig
@@ -4,7 +4,7 @@ CONFIG_BSD_PROCESS_ACCT=y
4CONFIG_IKCONFIG=y 4CONFIG_IKCONFIG=y
5CONFIG_LOG_BUF_SHIFT=14 5CONFIG_LOG_BUF_SHIFT=14
6# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 6# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
7CONFIG_EMBEDDED=y 7CONFIG_EXPERT=y
8# CONFIG_KALLSYMS is not set 8# CONFIG_KALLSYMS is not set
9# CONFIG_FUTEX is not set 9# CONFIG_FUTEX is not set
10# CONFIG_EPOLL is not set 10# CONFIG_EPOLL is not set
diff --git a/arch/m32r/configs/mappi3.smp_defconfig b/arch/m32r/configs/mappi3.smp_defconfig
index b204e2ecd0f1..27cefd41ac1f 100644
--- a/arch/m32r/configs/mappi3.smp_defconfig
+++ b/arch/m32r/configs/mappi3.smp_defconfig
@@ -5,7 +5,7 @@ CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=15 5CONFIG_LOG_BUF_SHIFT=15
6CONFIG_BLK_DEV_INITRD=y 6CONFIG_BLK_DEV_INITRD=y
7# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 7# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
8CONFIG_EMBEDDED=y 8CONFIG_EXPERT=y
9# CONFIG_KALLSYMS is not set 9# CONFIG_KALLSYMS is not set
10# CONFIG_FUTEX is not set 10# CONFIG_FUTEX is not set
11# CONFIG_EPOLL is not set 11# CONFIG_EPOLL is not set
diff --git a/arch/m32r/configs/oaks32r_defconfig b/arch/m32r/configs/oaks32r_defconfig
index 5aa4ea9ebb10..5087a510ca4f 100644
--- a/arch/m32r/configs/oaks32r_defconfig
+++ b/arch/m32r/configs/oaks32r_defconfig
@@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y
2CONFIG_BSD_PROCESS_ACCT=y 2CONFIG_BSD_PROCESS_ACCT=y
3CONFIG_LOG_BUF_SHIFT=14 3CONFIG_LOG_BUF_SHIFT=14
4# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 4# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
5CONFIG_EMBEDDED=y 5CONFIG_EXPERT=y
6# CONFIG_KALLSYMS is not set 6# CONFIG_KALLSYMS is not set
7# CONFIG_FUTEX is not set 7# CONFIG_FUTEX is not set
8# CONFIG_EPOLL is not set 8# CONFIG_EPOLL is not set
diff --git a/arch/m32r/configs/opsput_defconfig b/arch/m32r/configs/opsput_defconfig
index 8494c6a276e8..50c6f525db20 100644
--- a/arch/m32r/configs/opsput_defconfig
+++ b/arch/m32r/configs/opsput_defconfig
@@ -4,7 +4,7 @@ CONFIG_BSD_PROCESS_ACCT=y
4CONFIG_IKCONFIG=y 4CONFIG_IKCONFIG=y
5CONFIG_LOG_BUF_SHIFT=14 5CONFIG_LOG_BUF_SHIFT=14
6# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 6# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
7CONFIG_EMBEDDED=y 7CONFIG_EXPERT=y
8# CONFIG_KALLSYMS is not set 8# CONFIG_KALLSYMS is not set
9# CONFIG_FUTEX is not set 9# CONFIG_FUTEX is not set
10# CONFIG_EPOLL is not set 10# CONFIG_EPOLL is not set
diff --git a/arch/m32r/configs/usrv_defconfig b/arch/m32r/configs/usrv_defconfig
index 1df293bc2ab9..a3cfaaedab60 100644
--- a/arch/m32r/configs/usrv_defconfig
+++ b/arch/m32r/configs/usrv_defconfig
@@ -5,7 +5,7 @@ CONFIG_BSD_PROCESS_ACCT=y
5CONFIG_LOG_BUF_SHIFT=15 5CONFIG_LOG_BUF_SHIFT=15
6CONFIG_BLK_DEV_INITRD=y 6CONFIG_BLK_DEV_INITRD=y
7# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 7# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
8CONFIG_EMBEDDED=y 8CONFIG_EXPERT=y
9CONFIG_KALLSYMS_EXTRA_PASS=y 9CONFIG_KALLSYMS_EXTRA_PASS=y
10CONFIG_SLAB=y 10CONFIG_SLAB=y
11CONFIG_MODULES=y 11CONFIG_MODULES=y
diff --git a/arch/m32r/include/asm/bitops.h b/arch/m32r/include/asm/bitops.h
index aaddf0d57603..6300f22cdbdb 100644
--- a/arch/m32r/include/asm/bitops.h
+++ b/arch/m32r/include/asm/bitops.h
@@ -266,9 +266,8 @@ static __inline__ int test_and_change_bit(int nr, volatile void * addr)
266 266
267#ifdef __KERNEL__ 267#ifdef __KERNEL__
268 268
269#include <asm-generic/bitops/ext2-non-atomic.h> 269#include <asm-generic/bitops/le.h>
270#include <asm-generic/bitops/ext2-atomic.h> 270#include <asm-generic/bitops/ext2-atomic.h>
271#include <asm-generic/bitops/minix.h>
272 271
273#endif /* __KERNEL__ */ 272#endif /* __KERNEL__ */
274 273
diff --git a/arch/m32r/include/asm/ioctls.h b/arch/m32r/include/asm/ioctls.h
index 66288063a4c0..349bf87bfbd0 100644
--- a/arch/m32r/include/asm/ioctls.h
+++ b/arch/m32r/include/asm/ioctls.h
@@ -1,87 +1,6 @@
1#ifndef __ARCH_M32R_IOCTLS_H__ 1#ifndef __ARCH_M32R_IOCTLS_H__
2#define __ARCH_M32R_IOCTLS_H__ 2#define __ARCH_M32R_IOCTLS_H__
3 3
4#include <asm/ioctl.h> 4#include <asm-generic/ioctls.h>
5
6/* 0x54 is just a magic number to make these relatively unique ('T') */
7
8#define TCGETS 0x5401
9#define TCSETS 0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */
10#define TCSETSW 0x5403
11#define TCSETSF 0x5404
12#define TCGETA 0x5405
13#define TCSETA 0x5406
14#define TCSETAW 0x5407
15#define TCSETAF 0x5408
16#define TCSBRK 0x5409
17#define TCXONC 0x540A
18#define TCFLSH 0x540B
19#define TIOCEXCL 0x540C
20#define TIOCNXCL 0x540D
21#define TIOCSCTTY 0x540E
22#define TIOCGPGRP 0x540F
23#define TIOCSPGRP 0x5410
24#define TIOCOUTQ 0x5411
25#define TIOCSTI 0x5412
26#define TIOCGWINSZ 0x5413
27#define TIOCSWINSZ 0x5414
28#define TIOCMGET 0x5415
29#define TIOCMBIS 0x5416
30#define TIOCMBIC 0x5417
31#define TIOCMSET 0x5418
32#define TIOCGSOFTCAR 0x5419
33#define TIOCSSOFTCAR 0x541A
34#define FIONREAD 0x541B
35#define TIOCINQ FIONREAD
36#define TIOCLINUX 0x541C
37#define TIOCCONS 0x541D
38#define TIOCGSERIAL 0x541E
39#define TIOCSSERIAL 0x541F
40#define TIOCPKT 0x5420
41#define FIONBIO 0x5421
42#define TIOCNOTTY 0x5422
43#define TIOCSETD 0x5423
44#define TIOCGETD 0x5424
45#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */
46/* #define TIOCTTYGSTRUCT 0x5426 - Former debugging-only ioctl */
47#define TIOCSBRK 0x5427 /* BSD compatibility */
48#define TIOCCBRK 0x5428 /* BSD compatibility */
49#define TIOCGSID 0x5429 /* Return the session ID of FD */
50#define TCGETS2 _IOR('T',0x2A, struct termios2)
51#define TCSETS2 _IOW('T',0x2B, struct termios2)
52#define TCSETSW2 _IOW('T',0x2C, struct termios2)
53#define TCSETSF2 _IOW('T',0x2D, struct termios2)
54#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
55#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
56#define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */
57
58#define FIONCLEX 0x5450
59#define FIOCLEX 0x5451
60#define FIOASYNC 0x5452
61#define TIOCSERCONFIG 0x5453
62#define TIOCSERGWILD 0x5454
63#define TIOCSERSWILD 0x5455
64#define TIOCGLCKTRMIOS 0x5456
65#define TIOCSLCKTRMIOS 0x5457
66#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
67#define TIOCSERGETLSR 0x5459 /* Get line status register */
68#define TIOCSERGETMULTI 0x545A /* Get multiport config */
69#define TIOCSERSETMULTI 0x545B /* Set multiport config */
70
71#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */
72#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
73#define FIOQSIZE 0x5460
74
75/* Used for packet mode */
76#define TIOCPKT_DATA 0
77#define TIOCPKT_FLUSHREAD 1
78#define TIOCPKT_FLUSHWRITE 2
79#define TIOCPKT_STOP 4
80#define TIOCPKT_START 8
81#define TIOCPKT_NOSTOP 16
82#define TIOCPKT_DOSTOP 32
83#define TIOCPKT_IOCTL 64
84
85#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
86 5
87#endif /* __ARCH_M32R_IOCTLS_H__ */ 6#endif /* __ARCH_M32R_IOCTLS_H__ */
diff --git a/arch/m32r/include/asm/irqflags.h b/arch/m32r/include/asm/irqflags.h
new file mode 100644
index 000000000000..1f92d29982ae
--- /dev/null
+++ b/arch/m32r/include/asm/irqflags.h
@@ -0,0 +1,104 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
7 * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
8 */
9
10#ifndef _ASM_M32R_IRQFLAGS_H
11#define _ASM_M32R_IRQFLAGS_H
12
13#include <linux/types.h>
14
15static inline unsigned long arch_local_save_flags(void)
16{
17 unsigned long flags;
18 asm volatile("mvfc %0,psw" : "=r"(flags));
19 return flags;
20}
21
22static inline void arch_local_irq_disable(void)
23{
24#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
25 asm volatile (
26 "clrpsw #0x40 -> nop"
27 : : : "memory");
28#else
29 unsigned long tmpreg0, tmpreg1;
30 asm volatile (
31 "ld24 %0, #0 ; Use 32-bit insn. \n\t"
32 "mvfc %1, psw ; No interrupt can be accepted here. \n\t"
33 "mvtc %0, psw \n\t"
34 "and3 %0, %1, #0xffbf \n\t"
35 "mvtc %0, psw \n\t"
36 : "=&r" (tmpreg0), "=&r" (tmpreg1)
37 :
38 : "cbit", "memory");
39#endif
40}
41
42static inline void arch_local_irq_enable(void)
43{
44#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
45 asm volatile (
46 "setpsw #0x40 -> nop"
47 : : : "memory");
48#else
49 unsigned long tmpreg;
50 asm volatile (
51 "mvfc %0, psw; \n\t"
52 "or3 %0, %0, #0x0040; \n\t"
53 "mvtc %0, psw; \n\t"
54 : "=&r" (tmpreg)
55 :
56 : "cbit", "memory");
57#endif
58}
59
60static inline unsigned long arch_local_irq_save(void)
61{
62 unsigned long flags;
63
64#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
65 asm volatile (
66 "mvfc %0, psw; \n\t"
67 "clrpsw #0x40 -> nop; \n\t"
68 : "=r" (flags)
69 :
70 : "memory");
71#else
72 unsigned long tmpreg;
73 asm volatile (
74 "ld24 %1, #0 \n\t"
75 "mvfc %0, psw \n\t"
76 "mvtc %1, psw \n\t"
77 "and3 %1, %0, #0xffbf \n\t"
78 "mvtc %1, psw \n\t"
79 : "=r" (flags), "=&r" (tmpreg)
80 :
81 : "cbit", "memory");
82#endif
83 return flags;
84}
85
86static inline void arch_local_irq_restore(unsigned long flags)
87{
88 asm volatile("mvtc %0,psw"
89 :
90 : "r" (flags)
91 : "cbit", "memory");
92}
93
94static inline bool arch_irqs_disabled_flags(unsigned long flags)
95{
96 return !(flags & 0x40);
97}
98
99static inline bool arch_irqs_disabled(void)
100{
101 return arch_irqs_disabled_flags(arch_local_save_flags());
102}
103
104#endif /* _ASM_M32R_IRQFLAGS_H */
diff --git a/arch/m32r/include/asm/m32104ut/m32104ut_pld.h b/arch/m32r/include/asm/m32104ut/m32104ut_pld.h
index 2dc89d68b6d9..1feae9709f24 100644
--- a/arch/m32r/include/asm/m32104ut/m32104ut_pld.h
+++ b/arch/m32r/include/asm/m32104ut/m32104ut_pld.h
@@ -4,7 +4,7 @@
4/* 4/*
5 * include/asm-m32r/m32104ut/m32104ut_pld.h 5 * include/asm-m32r/m32104ut/m32104ut_pld.h
6 * 6 *
7 * Definitions for Programable Logic Device(PLD) on M32104UT board. 7 * Definitions for Programmable Logic Device(PLD) on M32104UT board.
8 * Based on m32700ut_pld.h 8 * Based on m32700ut_pld.h
9 * 9 *
10 * Copyright (c) 2002 Takeo Takahashi 10 * Copyright (c) 2002 Takeo Takahashi
diff --git a/arch/m32r/include/asm/m32700ut/m32700ut_pld.h b/arch/m32r/include/asm/m32700ut/m32700ut_pld.h
index 57623beb44cb..35294670b187 100644
--- a/arch/m32r/include/asm/m32700ut/m32700ut_pld.h
+++ b/arch/m32r/include/asm/m32700ut/m32700ut_pld.h
@@ -4,7 +4,7 @@
4/* 4/*
5 * include/asm-m32r/m32700ut/m32700ut_pld.h 5 * include/asm-m32r/m32700ut/m32700ut_pld.h
6 * 6 *
7 * Definitions for Programable Logic Device(PLD) on M32700UT board. 7 * Definitions for Programmable Logic Device(PLD) on M32700UT board.
8 * 8 *
9 * Copyright (c) 2002 Takeo Takahashi 9 * Copyright (c) 2002 Takeo Takahashi
10 * 10 *
diff --git a/arch/m32r/include/asm/mmzone.h b/arch/m32r/include/asm/mmzone.h
index 9f3b5accda88..115ced33febd 100644
--- a/arch/m32r/include/asm/mmzone.h
+++ b/arch/m32r/include/asm/mmzone.h
@@ -14,12 +14,6 @@ extern struct pglist_data *node_data[];
14#define NODE_DATA(nid) (node_data[nid]) 14#define NODE_DATA(nid) (node_data[nid])
15 15
16#define node_localnr(pfn, nid) ((pfn) - NODE_DATA(nid)->node_start_pfn) 16#define node_localnr(pfn, nid) ((pfn) - NODE_DATA(nid)->node_start_pfn)
17#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn)
18#define node_end_pfn(nid) \
19({ \
20 pg_data_t *__pgdat = NODE_DATA(nid); \
21 __pgdat->node_start_pfn + __pgdat->node_spanned_pages - 1; \
22})
23 17
24#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) 18#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
25/* 19/*
@@ -44,7 +38,7 @@ static __inline__ int pfn_to_nid(unsigned long pfn)
44 int node; 38 int node;
45 39
46 for (node = 0 ; node < MAX_NUMNODES ; node++) 40 for (node = 0 ; node < MAX_NUMNODES ; node++)
47 if (pfn >= node_start_pfn(node) && pfn <= node_end_pfn(node)) 41 if (pfn >= node_start_pfn(node) && pfn < node_end_pfn(node))
48 break; 42 break;
49 43
50 return node; 44 return node;
diff --git a/arch/m32r/include/asm/opsput/opsput_pld.h b/arch/m32r/include/asm/opsput/opsput_pld.h
index 3f11ea1aac2d..6901401fe9eb 100644
--- a/arch/m32r/include/asm/opsput/opsput_pld.h
+++ b/arch/m32r/include/asm/opsput/opsput_pld.h
@@ -4,7 +4,7 @@
4/* 4/*
5 * include/asm-m32r/opsput/opsput_pld.h 5 * include/asm-m32r/opsput/opsput_pld.h
6 * 6 *
7 * Definitions for Programable Logic Device(PLD) on OPSPUT board. 7 * Definitions for Programmable Logic Device(PLD) on OPSPUT board.
8 * 8 *
9 * Copyright (c) 2002 Takeo Takahashi 9 * Copyright (c) 2002 Takeo Takahashi
10 * 10 *
diff --git a/arch/m32r/include/asm/pgtable-2level.h b/arch/m32r/include/asm/pgtable-2level.h
index bca3475f9595..9cdaf7350ef6 100644
--- a/arch/m32r/include/asm/pgtable-2level.h
+++ b/arch/m32r/include/asm/pgtable-2level.h
@@ -44,7 +44,7 @@ static inline int pgd_present(pgd_t pgd) { return 1; }
44#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) 44#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
45 45
46/* 46/*
47 * (pmds are folded into pgds so this doesnt get actually called, 47 * (pmds are folded into pgds so this doesn't get actually called,
48 * but the define is needed for a generic inline function.) 48 * but the define is needed for a generic inline function.)
49 */ 49 */
50#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) 50#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
diff --git a/arch/m32r/include/asm/pgtable.h b/arch/m32r/include/asm/pgtable.h
index e6359c566b50..8a28cfea2729 100644
--- a/arch/m32r/include/asm/pgtable.h
+++ b/arch/m32r/include/asm/pgtable.h
@@ -332,9 +332,7 @@ static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
332 ((pte_t *)pmd_page_vaddr(*(dir)) + pte_index(address)) 332 ((pte_t *)pmd_page_vaddr(*(dir)) + pte_index(address))
333#define pte_offset_map(dir, address) \ 333#define pte_offset_map(dir, address) \
334 ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address)) 334 ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
335#define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
336#define pte_unmap(pte) do { } while (0) 335#define pte_unmap(pte) do { } while (0)
337#define pte_unmap_nested(pte) do { } while (0)
338 336
339/* Encode and de-code a swap entry */ 337/* Encode and de-code a swap entry */
340#define __swp_type(x) (((x).val >> 2) & 0x1f) 338#define __swp_type(x) (((x).val >> 2) & 0x1f)
diff --git a/arch/m32r/include/asm/smp.h b/arch/m32r/include/asm/smp.h
index e67ded1aab91..cf7829a61551 100644
--- a/arch/m32r/include/asm/smp.h
+++ b/arch/m32r/include/asm/smp.h
@@ -81,11 +81,11 @@ static __inline__ int cpu_number_map(int cpu)
81 81
82static __inline__ unsigned int num_booting_cpus(void) 82static __inline__ unsigned int num_booting_cpus(void)
83{ 83{
84 return cpus_weight(cpu_callout_map); 84 return cpumask_weight(&cpu_callout_map);
85} 85}
86 86
87extern void smp_send_timer(void); 87extern void smp_send_timer(void);
88extern unsigned long send_IPI_mask_phys(cpumask_t, int, int); 88extern unsigned long send_IPI_mask_phys(const cpumask_t*, int, int);
89 89
90extern void arch_send_call_function_single_ipi(int cpu); 90extern void arch_send_call_function_single_ipi(int cpu);
91extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); 91extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
@@ -94,8 +94,6 @@ extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
94 94
95#define NO_PROC_ID (0xff) /* No processor magic marker */ 95#define NO_PROC_ID (0xff) /* No processor magic marker */
96 96
97#define PROC_CHANGE_PENALTY (15) /* Schedule penalty */
98
99/* 97/*
100 * M32R-mp IPI 98 * M32R-mp IPI
101 */ 99 */
diff --git a/arch/m32r/include/asm/system.h b/arch/m32r/include/asm/system.h
index c980f5ba8de7..13c46794ccb1 100644
--- a/arch/m32r/include/asm/system.h
+++ b/arch/m32r/include/asm/system.h
@@ -11,6 +11,7 @@
11 */ 11 */
12 12
13#include <linux/compiler.h> 13#include <linux/compiler.h>
14#include <linux/irqflags.h>
14#include <asm/assembler.h> 15#include <asm/assembler.h>
15 16
16#ifdef __KERNEL__ 17#ifdef __KERNEL__
@@ -54,71 +55,6 @@
54 ); \ 55 ); \
55} while(0) 56} while(0)
56 57
57/* Interrupt Control */
58#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
59#define local_irq_enable() \
60 __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory")
61#define local_irq_disable() \
62 __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory")
63#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
64static inline void local_irq_enable(void)
65{
66 unsigned long tmpreg;
67 __asm__ __volatile__(
68 "mvfc %0, psw; \n\t"
69 "or3 %0, %0, #0x0040; \n\t"
70 "mvtc %0, psw; \n\t"
71 : "=&r" (tmpreg) : : "cbit", "memory");
72}
73
74static inline void local_irq_disable(void)
75{
76 unsigned long tmpreg0, tmpreg1;
77 __asm__ __volatile__(
78 "ld24 %0, #0 ; Use 32-bit insn. \n\t"
79 "mvfc %1, psw ; No interrupt can be accepted here. \n\t"
80 "mvtc %0, psw \n\t"
81 "and3 %0, %1, #0xffbf \n\t"
82 "mvtc %0, psw \n\t"
83 : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory");
84}
85#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
86
87#define local_save_flags(x) \
88 __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */)
89
90#define local_irq_restore(x) \
91 __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \
92 : "r" (x) : "cbit", "memory")
93
94#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
95#define local_irq_save(x) \
96 __asm__ __volatile__( \
97 "mvfc %0, psw; \n\t" \
98 "clrpsw #0x40 -> nop; \n\t" \
99 : "=r" (x) : /* no input */ : "memory")
100#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
101#define local_irq_save(x) \
102 ({ \
103 unsigned long tmpreg; \
104 __asm__ __volatile__( \
105 "ld24 %1, #0 \n\t" \
106 "mvfc %0, psw \n\t" \
107 "mvtc %1, psw \n\t" \
108 "and3 %1, %0, #0xffbf \n\t" \
109 "mvtc %1, psw \n\t" \
110 : "=r" (x), "=&r" (tmpreg) \
111 : : "cbit", "memory"); \
112 })
113#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
114
115#define irqs_disabled() \
116 ({ \
117 unsigned long flags; \
118 local_save_flags(flags); \
119 !(flags & 0x40); \
120 })
121
122#define nop() __asm__ __volatile__ ("nop" : : ) 58#define nop() __asm__ __volatile__ ("nop" : : )
123 59
124#define xchg(ptr, x) \ 60#define xchg(ptr, x) \
diff --git a/arch/m32r/include/asm/thread_info.h b/arch/m32r/include/asm/thread_info.h
index 71faff5bcc27..0227dba44068 100644
--- a/arch/m32r/include/asm/thread_info.h
+++ b/arch/m32r/include/asm/thread_info.h
@@ -96,16 +96,11 @@ static inline struct thread_info *current_thread_info(void)
96 96
97/* thread information allocation */ 97/* thread information allocation */
98#ifdef CONFIG_DEBUG_STACK_USAGE 98#ifdef CONFIG_DEBUG_STACK_USAGE
99#define alloc_thread_info(tsk) \ 99#define alloc_thread_info_node(tsk, node) \
100 ({ \ 100 kzalloc_node(THREAD_SIZE, GFP_KERNEL, node)
101 struct thread_info *ret; \
102 \
103 ret = kzalloc(THREAD_SIZE, GFP_KERNEL); \
104 \
105 ret; \
106 })
107#else 101#else
108#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) 102#define alloc_thread_info_node(tsk, node) \
103 kmalloc_node(THREAD_SIZE, GFP_KERNEL, node)
109#endif 104#endif
110 105
111#define free_thread_info(info) kfree(info) 106#define free_thread_info(info) kfree(info)
diff --git a/arch/m32r/include/asm/types.h b/arch/m32r/include/asm/types.h
index bc9f7fff0ac3..bd0035597b3b 100644
--- a/arch/m32r/include/asm/types.h
+++ b/arch/m32r/include/asm/types.h
@@ -16,15 +16,6 @@ typedef unsigned short umode_t;
16 16
17#define BITS_PER_LONG 32 17#define BITS_PER_LONG 32
18 18
19#ifndef __ASSEMBLY__
20
21/* DMA addresses are 32-bits wide. */
22
23typedef u32 dma_addr_t;
24typedef u64 dma64_addr_t;
25
26#endif /* __ASSEMBLY__ */
27
28#endif /* __KERNEL__ */ 19#endif /* __KERNEL__ */
29 20
30#endif /* _ASM_M32R_TYPES_H */ 21#endif /* _ASM_M32R_TYPES_H */
diff --git a/arch/m32r/include/asm/unistd.h b/arch/m32r/include/asm/unistd.h
index c70545689da8..3e1db561aacc 100644
--- a/arch/m32r/include/asm/unistd.h
+++ b/arch/m32r/include/asm/unistd.h
@@ -330,10 +330,11 @@
330/* #define __NR_timerfd 322 removed */ 330/* #define __NR_timerfd 322 removed */
331#define __NR_eventfd 323 331#define __NR_eventfd 323
332#define __NR_fallocate 324 332#define __NR_fallocate 324
333#define __NR_setns 325
333 334
334#ifdef __KERNEL__ 335#ifdef __KERNEL__
335 336
336#define NR_syscalls 325 337#define NR_syscalls 326
337 338
338#define __ARCH_WANT_IPC_PARSE_VERSION 339#define __ARCH_WANT_IPC_PARSE_VERSION
339#define __ARCH_WANT_STAT64 340#define __ARCH_WANT_STAT64
diff --git a/arch/m32r/kernel/irq.c b/arch/m32r/kernel/irq.c
index 3c71f776872c..c7272b894283 100644
--- a/arch/m32r/kernel/irq.c
+++ b/arch/m32r/kernel/irq.c
@@ -18,53 +18,10 @@
18 18
19#include <linux/kernel_stat.h> 19#include <linux/kernel_stat.h>
20#include <linux/interrupt.h> 20#include <linux/interrupt.h>
21#include <linux/seq_file.h>
22#include <linux/module.h> 21#include <linux/module.h>
23#include <asm/uaccess.h> 22#include <asm/uaccess.h>
24 23
25/* 24/*
26 * Generic, controller-independent functions:
27 */
28
29int show_interrupts(struct seq_file *p, void *v)
30{
31 int i = *(loff_t *) v, j;
32 struct irqaction * action;
33 unsigned long flags;
34
35 if (i == 0) {
36 seq_printf(p, " ");
37 for_each_online_cpu(j)
38 seq_printf(p, "CPU%d ",j);
39 seq_putc(p, '\n');
40 }
41
42 if (i < NR_IRQS) {
43 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
44 action = irq_desc[i].action;
45 if (!action)
46 goto skip;
47 seq_printf(p, "%3d: ",i);
48#ifndef CONFIG_SMP
49 seq_printf(p, "%10u ", kstat_irqs(i));
50#else
51 for_each_online_cpu(j)
52 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
53#endif
54 seq_printf(p, " %14s", irq_desc[i].chip->typename);
55 seq_printf(p, " %s", action->name);
56
57 for (action=action->next; action; action = action->next)
58 seq_printf(p, ", %s", action->name);
59
60 seq_putc(p, '\n');
61skip:
62 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
63 }
64 return 0;
65}
66
67/*
68 * do_IRQ handles all normal device IRQs (the special 25 * do_IRQ handles all normal device IRQs (the special
69 * SMP cross-CPU interrupts have their own specific 26 * SMP cross-CPU interrupts have their own specific
70 * handlers). 27 * handlers).
@@ -78,7 +35,7 @@ asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs)
78#ifdef CONFIG_DEBUG_STACKOVERFLOW 35#ifdef CONFIG_DEBUG_STACKOVERFLOW
79 /* FIXME M32R */ 36 /* FIXME M32R */
80#endif 37#endif
81 __do_IRQ(irq); 38 generic_handle_irq(irq);
82 irq_exit(); 39 irq_exit();
83 set_irq_regs(old_regs); 40 set_irq_regs(old_regs);
84 41
diff --git a/arch/m32r/kernel/ptrace.c b/arch/m32r/kernel/ptrace.c
index 0021ade4cba8..20743754f2b2 100644
--- a/arch/m32r/kernel/ptrace.c
+++ b/arch/m32r/kernel/ptrace.c
@@ -622,9 +622,11 @@ void ptrace_disable(struct task_struct *child)
622} 622}
623 623
624long 624long
625arch_ptrace(struct task_struct *child, long request, long addr, long data) 625arch_ptrace(struct task_struct *child, long request,
626 unsigned long addr, unsigned long data)
626{ 627{
627 int ret; 628 int ret;
629 unsigned long __user *datap = (unsigned long __user *) data;
628 630
629 switch (request) { 631 switch (request) {
630 /* 632 /*
@@ -639,8 +641,7 @@ arch_ptrace(struct task_struct *child, long request, long addr, long data)
639 * read the word at location addr in the USER area. 641 * read the word at location addr in the USER area.
640 */ 642 */
641 case PTRACE_PEEKUSR: 643 case PTRACE_PEEKUSR:
642 ret = ptrace_read_user(child, addr, 644 ret = ptrace_read_user(child, addr, datap);
643 (unsigned long __user *)data);
644 break; 645 break;
645 646
646 /* 647 /*
@@ -661,11 +662,11 @@ arch_ptrace(struct task_struct *child, long request, long addr, long data)
661 break; 662 break;
662 663
663 case PTRACE_GETREGS: 664 case PTRACE_GETREGS:
664 ret = ptrace_getregs(child, (void __user *)data); 665 ret = ptrace_getregs(child, datap);
665 break; 666 break;
666 667
667 case PTRACE_SETREGS: 668 case PTRACE_SETREGS:
668 ret = ptrace_setregs(child, (void __user *)data); 669 ret = ptrace_setregs(child, datap);
669 break; 670 break;
670 671
671 default: 672 default:
diff --git a/arch/m32r/kernel/smp.c b/arch/m32r/kernel/smp.c
index 31cef20b2996..092d40a6708e 100644
--- a/arch/m32r/kernel/smp.c
+++ b/arch/m32r/kernel/smp.c
@@ -30,6 +30,7 @@
30#include <asm/io.h> 30#include <asm/io.h>
31#include <asm/mmu_context.h> 31#include <asm/mmu_context.h>
32#include <asm/m32r.h> 32#include <asm/m32r.h>
33#include <asm/tlbflush.h>
33 34
34/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ 35/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
35/* Data structures and variables */ 36/* Data structures and variables */
@@ -61,33 +62,22 @@ extern spinlock_t ipi_lock[];
61/* Function Prototypes */ 62/* Function Prototypes */
62/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ 63/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
63 64
64void smp_send_reschedule(int);
65void smp_reschedule_interrupt(void); 65void smp_reschedule_interrupt(void);
66
67void smp_flush_cache_all(void);
68void smp_flush_cache_all_interrupt(void); 66void smp_flush_cache_all_interrupt(void);
69 67
70void smp_flush_tlb_all(void);
71static void flush_tlb_all_ipi(void *); 68static void flush_tlb_all_ipi(void *);
72
73void smp_flush_tlb_mm(struct mm_struct *);
74void smp_flush_tlb_range(struct vm_area_struct *, unsigned long, \
75 unsigned long);
76void smp_flush_tlb_page(struct vm_area_struct *, unsigned long);
77static void flush_tlb_others(cpumask_t, struct mm_struct *, 69static void flush_tlb_others(cpumask_t, struct mm_struct *,
78 struct vm_area_struct *, unsigned long); 70 struct vm_area_struct *, unsigned long);
71
79void smp_invalidate_interrupt(void); 72void smp_invalidate_interrupt(void);
80 73
81void smp_send_stop(void);
82static void stop_this_cpu(void *); 74static void stop_this_cpu(void *);
83 75
84void smp_send_timer(void);
85void smp_ipi_timer_interrupt(struct pt_regs *); 76void smp_ipi_timer_interrupt(struct pt_regs *);
86void smp_local_timer_interrupt(void); 77void smp_local_timer_interrupt(void);
87 78
88static void send_IPI_allbutself(int, int); 79static void send_IPI_allbutself(int, int);
89static void send_IPI_mask(const struct cpumask *, int, int); 80static void send_IPI_mask(const struct cpumask *, int, int);
90unsigned long send_IPI_mask_phys(cpumask_t, int, int);
91 81
92/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ 82/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
93/* Rescheduling request Routines */ 83/* Rescheduling request Routines */
@@ -122,8 +112,6 @@ void smp_send_reschedule(int cpu_id)
122 * 112 *
123 * Description: This routine executes on CPU which received 113 * Description: This routine executes on CPU which received
124 * 'RESCHEDULE_IPI'. 114 * 'RESCHEDULE_IPI'.
125 * Rescheduling is processed at the exit of interrupt
126 * operation.
127 * 115 *
128 * Born on Date: 2002.02.05 116 * Born on Date: 2002.02.05
129 * 117 *
@@ -138,7 +126,7 @@ void smp_send_reschedule(int cpu_id)
138 *==========================================================================*/ 126 *==========================================================================*/
139void smp_reschedule_interrupt(void) 127void smp_reschedule_interrupt(void)
140{ 128{
141 /* nothing to do */ 129 scheduler_ipi();
142} 130}
143 131
144/*==========================================================================* 132/*==========================================================================*
@@ -164,10 +152,10 @@ void smp_flush_cache_all(void)
164 unsigned long *mask; 152 unsigned long *mask;
165 153
166 preempt_disable(); 154 preempt_disable();
167 cpumask = cpu_online_map; 155 cpumask_copy(&cpumask, cpu_online_mask);
168 cpu_clear(smp_processor_id(), cpumask); 156 cpumask_clear_cpu(smp_processor_id(), &cpumask);
169 spin_lock(&flushcache_lock); 157 spin_lock(&flushcache_lock);
170 mask=cpus_addr(cpumask); 158 mask=cpumask_bits(&cpumask);
171 atomic_set_mask(*mask, (atomic_t *)&flushcache_cpumask); 159 atomic_set_mask(*mask, (atomic_t *)&flushcache_cpumask);
172 send_IPI_mask(&cpumask, INVALIDATE_CACHE_IPI, 0); 160 send_IPI_mask(&cpumask, INVALIDATE_CACHE_IPI, 0);
173 _flush_cache_copyback_all(); 161 _flush_cache_copyback_all();
@@ -265,8 +253,8 @@ void smp_flush_tlb_mm(struct mm_struct *mm)
265 preempt_disable(); 253 preempt_disable();
266 cpu_id = smp_processor_id(); 254 cpu_id = smp_processor_id();
267 mmc = &mm->context[cpu_id]; 255 mmc = &mm->context[cpu_id];
268 cpu_mask = *mm_cpumask(mm); 256 cpumask_copy(&cpu_mask, mm_cpumask(mm));
269 cpu_clear(cpu_id, cpu_mask); 257 cpumask_clear_cpu(cpu_id, &cpu_mask);
270 258
271 if (*mmc != NO_CONTEXT) { 259 if (*mmc != NO_CONTEXT) {
272 local_irq_save(flags); 260 local_irq_save(flags);
@@ -277,7 +265,7 @@ void smp_flush_tlb_mm(struct mm_struct *mm)
277 cpumask_clear_cpu(cpu_id, mm_cpumask(mm)); 265 cpumask_clear_cpu(cpu_id, mm_cpumask(mm));
278 local_irq_restore(flags); 266 local_irq_restore(flags);
279 } 267 }
280 if (!cpus_empty(cpu_mask)) 268 if (!cpumask_empty(&cpu_mask))
281 flush_tlb_others(cpu_mask, mm, NULL, FLUSH_ALL); 269 flush_tlb_others(cpu_mask, mm, NULL, FLUSH_ALL);
282 270
283 preempt_enable(); 271 preempt_enable();
@@ -335,8 +323,8 @@ void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
335 preempt_disable(); 323 preempt_disable();
336 cpu_id = smp_processor_id(); 324 cpu_id = smp_processor_id();
337 mmc = &mm->context[cpu_id]; 325 mmc = &mm->context[cpu_id];
338 cpu_mask = *mm_cpumask(mm); 326 cpumask_copy(&cpu_mask, mm_cpumask(mm));
339 cpu_clear(cpu_id, cpu_mask); 327 cpumask_clear_cpu(cpu_id, &cpu_mask);
340 328
341#ifdef DEBUG_SMP 329#ifdef DEBUG_SMP
342 if (!mm) 330 if (!mm)
@@ -350,7 +338,7 @@ void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
350 __flush_tlb_page(va); 338 __flush_tlb_page(va);
351 local_irq_restore(flags); 339 local_irq_restore(flags);
352 } 340 }
353 if (!cpus_empty(cpu_mask)) 341 if (!cpumask_empty(&cpu_mask))
354 flush_tlb_others(cpu_mask, mm, vma, va); 342 flush_tlb_others(cpu_mask, mm, vma, va);
355 343
356 preempt_enable(); 344 preempt_enable();
@@ -397,14 +385,14 @@ static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
397 * - current CPU must not be in mask 385 * - current CPU must not be in mask
398 * - mask must exist :) 386 * - mask must exist :)
399 */ 387 */
400 BUG_ON(cpus_empty(cpumask)); 388 BUG_ON(cpumask_empty(&cpumask));
401 389
402 BUG_ON(cpu_isset(smp_processor_id(), cpumask)); 390 BUG_ON(cpumask_test_cpu(smp_processor_id(), &cpumask));
403 BUG_ON(!mm); 391 BUG_ON(!mm);
404 392
405 /* If a CPU which we ran on has gone down, OK. */ 393 /* If a CPU which we ran on has gone down, OK. */
406 cpus_and(cpumask, cpumask, cpu_online_map); 394 cpumask_and(&cpumask, &cpumask, cpu_online_mask);
407 if (cpus_empty(cpumask)) 395 if (cpumask_empty(&cpumask))
408 return; 396 return;
409 397
410 /* 398 /*
@@ -418,7 +406,7 @@ static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
418 flush_mm = mm; 406 flush_mm = mm;
419 flush_vma = vma; 407 flush_vma = vma;
420 flush_va = va; 408 flush_va = va;
421 mask=cpus_addr(cpumask); 409 mask=cpumask_bits(&cpumask);
422 atomic_set_mask(*mask, (atomic_t *)&flush_cpumask); 410 atomic_set_mask(*mask, (atomic_t *)&flush_cpumask);
423 411
424 /* 412 /*
@@ -427,7 +415,7 @@ static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
427 */ 415 */
428 send_IPI_mask(&cpumask, INVALIDATE_TLB_IPI, 0); 416 send_IPI_mask(&cpumask, INVALIDATE_TLB_IPI, 0);
429 417
430 while (!cpus_empty(flush_cpumask)) { 418 while (!cpumask_empty((cpumask_t*)&flush_cpumask)) {
431 /* nothing. lockup detection does not belong here */ 419 /* nothing. lockup detection does not belong here */
432 mb(); 420 mb();
433 } 421 }
@@ -462,7 +450,7 @@ void smp_invalidate_interrupt(void)
462 int cpu_id = smp_processor_id(); 450 int cpu_id = smp_processor_id();
463 unsigned long *mmc = &flush_mm->context[cpu_id]; 451 unsigned long *mmc = &flush_mm->context[cpu_id];
464 452
465 if (!cpu_isset(cpu_id, flush_cpumask)) 453 if (!cpumask_test_cpu(cpu_id, &flush_cpumask))
466 return; 454 return;
467 455
468 if (flush_va == FLUSH_ALL) { 456 if (flush_va == FLUSH_ALL) {
@@ -480,7 +468,7 @@ void smp_invalidate_interrupt(void)
480 __flush_tlb_page(va); 468 __flush_tlb_page(va);
481 } 469 }
482 } 470 }
483 cpu_clear(cpu_id, flush_cpumask); 471 cpumask_clear_cpu(cpu_id, (cpumask_t*)&flush_cpumask);
484} 472}
485 473
486/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ 474/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
@@ -532,7 +520,7 @@ static void stop_this_cpu(void *dummy)
532 /* 520 /*
533 * Remove this CPU: 521 * Remove this CPU:
534 */ 522 */
535 cpu_clear(cpu_id, cpu_online_map); 523 set_cpu_online(cpu_id, false);
536 524
537 /* 525 /*
538 * PSW IE = 1; 526 * PSW IE = 1;
@@ -727,8 +715,8 @@ static void send_IPI_allbutself(int ipi_num, int try)
727{ 715{
728 cpumask_t cpumask; 716 cpumask_t cpumask;
729 717
730 cpumask = cpu_online_map; 718 cpumask_copy(&cpumask, cpu_online_mask);
731 cpu_clear(smp_processor_id(), cpumask); 719 cpumask_clear_cpu(smp_processor_id(), &cpumask);
732 720
733 send_IPI_mask(&cpumask, ipi_num, try); 721 send_IPI_mask(&cpumask, ipi_num, try);
734} 722}
@@ -765,13 +753,13 @@ static void send_IPI_mask(const struct cpumask *cpumask, int ipi_num, int try)
765 cpumask_and(&tmp, cpumask, cpu_online_mask); 753 cpumask_and(&tmp, cpumask, cpu_online_mask);
766 BUG_ON(!cpumask_equal(cpumask, &tmp)); 754 BUG_ON(!cpumask_equal(cpumask, &tmp));
767 755
768 physid_mask = CPU_MASK_NONE; 756 cpumask_clear(&physid_mask);
769 for_each_cpu(cpu_id, cpumask) { 757 for_each_cpu(cpu_id, cpumask) {
770 if ((phys_id = cpu_to_physid(cpu_id)) != -1) 758 if ((phys_id = cpu_to_physid(cpu_id)) != -1)
771 cpu_set(phys_id, physid_mask); 759 cpumask_set_cpu(phys_id, &physid_mask);
772 } 760 }
773 761
774 send_IPI_mask_phys(physid_mask, ipi_num, try); 762 send_IPI_mask_phys(&physid_mask, ipi_num, try);
775} 763}
776 764
777/*==========================================================================* 765/*==========================================================================*
@@ -794,14 +782,14 @@ static void send_IPI_mask(const struct cpumask *cpumask, int ipi_num, int try)
794 * ---------- --- -------------------------------------------------------- 782 * ---------- --- --------------------------------------------------------
795 * 783 *
796 *==========================================================================*/ 784 *==========================================================================*/
797unsigned long send_IPI_mask_phys(cpumask_t physid_mask, int ipi_num, 785unsigned long send_IPI_mask_phys(const cpumask_t *physid_mask, int ipi_num,
798 int try) 786 int try)
799{ 787{
800 spinlock_t *ipilock; 788 spinlock_t *ipilock;
801 volatile unsigned long *ipicr_addr; 789 volatile unsigned long *ipicr_addr;
802 unsigned long ipicr_val; 790 unsigned long ipicr_val;
803 unsigned long my_physid_mask; 791 unsigned long my_physid_mask;
804 unsigned long mask = cpus_addr(physid_mask)[0]; 792 unsigned long mask = cpumask_bits(physid_mask)[0];
805 793
806 794
807 if (mask & ~physids_coerce(phys_cpu_present_map)) 795 if (mask & ~physids_coerce(phys_cpu_present_map))
diff --git a/arch/m32r/kernel/smpboot.c b/arch/m32r/kernel/smpboot.c
index e034844cfc0d..cfdbe5d15002 100644
--- a/arch/m32r/kernel/smpboot.c
+++ b/arch/m32r/kernel/smpboot.c
@@ -135,9 +135,9 @@ void __devinit smp_prepare_boot_cpu(void)
135{ 135{
136 bsp_phys_id = hard_smp_processor_id(); 136 bsp_phys_id = hard_smp_processor_id();
137 physid_set(bsp_phys_id, phys_cpu_present_map); 137 physid_set(bsp_phys_id, phys_cpu_present_map);
138 cpu_set(0, cpu_online_map); /* BSP's cpu_id == 0 */ 138 set_cpu_online(0, true); /* BSP's cpu_id == 0 */
139 cpu_set(0, cpu_callout_map); 139 cpumask_set_cpu(0, &cpu_callout_map);
140 cpu_set(0, cpu_callin_map); 140 cpumask_set_cpu(0, &cpu_callin_map);
141 141
142 /* 142 /*
143 * Initialize the logical to physical CPU number mapping 143 * Initialize the logical to physical CPU number mapping
@@ -178,7 +178,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
178 for (phys_id = 0 ; phys_id < nr_cpu ; phys_id++) 178 for (phys_id = 0 ; phys_id < nr_cpu ; phys_id++)
179 physid_set(phys_id, phys_cpu_present_map); 179 physid_set(phys_id, phys_cpu_present_map);
180#ifndef CONFIG_HOTPLUG_CPU 180#ifndef CONFIG_HOTPLUG_CPU
181 init_cpu_present(&cpu_possible_map); 181 init_cpu_present(cpu_possible_mask);
182#endif 182#endif
183 183
184 show_mp_info(nr_cpu); 184 show_mp_info(nr_cpu);
@@ -294,10 +294,10 @@ static void __init do_boot_cpu(int phys_id)
294 send_status = 0; 294 send_status = 0;
295 boot_status = 0; 295 boot_status = 0;
296 296
297 cpu_set(phys_id, cpu_bootout_map); 297 cpumask_set_cpu(phys_id, &cpu_bootout_map);
298 298
299 /* Send Startup IPI */ 299 /* Send Startup IPI */
300 send_IPI_mask_phys(cpumask_of_cpu(phys_id), CPU_BOOT_IPI, 0); 300 send_IPI_mask_phys(cpumask_of(phys_id), CPU_BOOT_IPI, 0);
301 301
302 Dprintk("Waiting for send to finish...\n"); 302 Dprintk("Waiting for send to finish...\n");
303 timeout = 0; 303 timeout = 0;
@@ -306,7 +306,7 @@ static void __init do_boot_cpu(int phys_id)
306 do { 306 do {
307 Dprintk("+"); 307 Dprintk("+");
308 udelay(1000); 308 udelay(1000);
309 send_status = !cpu_isset(phys_id, cpu_bootin_map); 309 send_status = !cpumask_test_cpu(phys_id, &cpu_bootin_map);
310 } while (send_status && (timeout++ < 100)); 310 } while (send_status && (timeout++ < 100));
311 311
312 Dprintk("After Startup.\n"); 312 Dprintk("After Startup.\n");
@@ -316,19 +316,19 @@ static void __init do_boot_cpu(int phys_id)
316 * allow APs to start initializing. 316 * allow APs to start initializing.
317 */ 317 */
318 Dprintk("Before Callout %d.\n", cpu_id); 318 Dprintk("Before Callout %d.\n", cpu_id);
319 cpu_set(cpu_id, cpu_callout_map); 319 cpumask_set_cpu(cpu_id, &cpu_callout_map);
320 Dprintk("After Callout %d.\n", cpu_id); 320 Dprintk("After Callout %d.\n", cpu_id);
321 321
322 /* 322 /*
323 * Wait 5s total for a response 323 * Wait 5s total for a response
324 */ 324 */
325 for (timeout = 0; timeout < 5000; timeout++) { 325 for (timeout = 0; timeout < 5000; timeout++) {
326 if (cpu_isset(cpu_id, cpu_callin_map)) 326 if (cpumask_test_cpu(cpu_id, &cpu_callin_map))
327 break; /* It has booted */ 327 break; /* It has booted */
328 udelay(1000); 328 udelay(1000);
329 } 329 }
330 330
331 if (cpu_isset(cpu_id, cpu_callin_map)) { 331 if (cpumask_test_cpu(cpu_id, &cpu_callin_map)) {
332 /* number CPUs logically, starting from 1 (BSP is 0) */ 332 /* number CPUs logically, starting from 1 (BSP is 0) */
333 Dprintk("OK.\n"); 333 Dprintk("OK.\n");
334 } else { 334 } else {
@@ -340,9 +340,9 @@ static void __init do_boot_cpu(int phys_id)
340 340
341 if (send_status || boot_status) { 341 if (send_status || boot_status) {
342 unmap_cpu_to_physid(cpu_id, phys_id); 342 unmap_cpu_to_physid(cpu_id, phys_id);
343 cpu_clear(cpu_id, cpu_callout_map); 343 cpumask_clear_cpu(cpu_id, &cpu_callout_map);
344 cpu_clear(cpu_id, cpu_callin_map); 344 cpumask_clear_cpu(cpu_id, &cpu_callin_map);
345 cpu_clear(cpu_id, cpu_initialized); 345 cpumask_clear_cpu(cpu_id, &cpu_initialized);
346 cpucount--; 346 cpucount--;
347 } 347 }
348} 348}
@@ -351,17 +351,17 @@ int __cpuinit __cpu_up(unsigned int cpu_id)
351{ 351{
352 int timeout; 352 int timeout;
353 353
354 cpu_set(cpu_id, smp_commenced_mask); 354 cpumask_set_cpu(cpu_id, &smp_commenced_mask);
355 355
356 /* 356 /*
357 * Wait 5s total for a response 357 * Wait 5s total for a response
358 */ 358 */
359 for (timeout = 0; timeout < 5000; timeout++) { 359 for (timeout = 0; timeout < 5000; timeout++) {
360 if (cpu_isset(cpu_id, cpu_online_map)) 360 if (cpu_online(cpu_id))
361 break; 361 break;
362 udelay(1000); 362 udelay(1000);
363 } 363 }
364 if (!cpu_isset(cpu_id, cpu_online_map)) 364 if (!cpu_online(cpu_id))
365 BUG(); 365 BUG();
366 366
367 return 0; 367 return 0;
@@ -373,11 +373,11 @@ void __init smp_cpus_done(unsigned int max_cpus)
373 unsigned long bogosum = 0; 373 unsigned long bogosum = 0;
374 374
375 for (timeout = 0; timeout < 5000; timeout++) { 375 for (timeout = 0; timeout < 5000; timeout++) {
376 if (cpus_equal(cpu_callin_map, cpu_online_map)) 376 if (cpumask_equal(&cpu_callin_map, cpu_online_mask))
377 break; 377 break;
378 udelay(1000); 378 udelay(1000);
379 } 379 }
380 if (!cpus_equal(cpu_callin_map, cpu_online_map)) 380 if (!cpumask_equal(&cpu_callin_map, cpu_online_mask))
381 BUG(); 381 BUG();
382 382
383 for (cpu_id = 0 ; cpu_id < num_online_cpus() ; cpu_id++) 383 for (cpu_id = 0 ; cpu_id < num_online_cpus() ; cpu_id++)
@@ -388,7 +388,7 @@ void __init smp_cpus_done(unsigned int max_cpus)
388 */ 388 */
389 Dprintk("Before bogomips.\n"); 389 Dprintk("Before bogomips.\n");
390 if (cpucount) { 390 if (cpucount) {
391 for_each_cpu_mask(cpu_id, cpu_online_map) 391 for_each_cpu(cpu_id,cpu_online_mask)
392 bogosum += cpu_data[cpu_id].loops_per_jiffy; 392 bogosum += cpu_data[cpu_id].loops_per_jiffy;
393 393
394 printk(KERN_INFO "Total of %d processors activated " \ 394 printk(KERN_INFO "Total of %d processors activated " \
@@ -425,7 +425,7 @@ int __init start_secondary(void *unused)
425 cpu_init(); 425 cpu_init();
426 preempt_disable(); 426 preempt_disable();
427 smp_callin(); 427 smp_callin();
428 while (!cpu_isset(smp_processor_id(), smp_commenced_mask)) 428 while (!cpumask_test_cpu(smp_processor_id(), &smp_commenced_mask))
429 cpu_relax(); 429 cpu_relax();
430 430
431 smp_online(); 431 smp_online();
@@ -463,7 +463,7 @@ static void __init smp_callin(void)
463 int cpu_id = smp_processor_id(); 463 int cpu_id = smp_processor_id();
464 unsigned long timeout; 464 unsigned long timeout;
465 465
466 if (cpu_isset(cpu_id, cpu_callin_map)) { 466 if (cpumask_test_cpu(cpu_id, &cpu_callin_map)) {
467 printk("huh, phys CPU#%d, CPU#%d already present??\n", 467 printk("huh, phys CPU#%d, CPU#%d already present??\n",
468 phys_id, cpu_id); 468 phys_id, cpu_id);
469 BUG(); 469 BUG();
@@ -474,7 +474,7 @@ static void __init smp_callin(void)
474 timeout = jiffies + (2 * HZ); 474 timeout = jiffies + (2 * HZ);
475 while (time_before(jiffies, timeout)) { 475 while (time_before(jiffies, timeout)) {
476 /* Has the boot CPU finished it's STARTUP sequence ? */ 476 /* Has the boot CPU finished it's STARTUP sequence ? */
477 if (cpu_isset(cpu_id, cpu_callout_map)) 477 if (cpumask_test_cpu(cpu_id, &cpu_callout_map))
478 break; 478 break;
479 cpu_relax(); 479 cpu_relax();
480 } 480 }
@@ -486,7 +486,7 @@ static void __init smp_callin(void)
486 } 486 }
487 487
488 /* Allow the master to continue. */ 488 /* Allow the master to continue. */
489 cpu_set(cpu_id, cpu_callin_map); 489 cpumask_set_cpu(cpu_id, &cpu_callin_map);
490} 490}
491 491
492static void __init smp_online(void) 492static void __init smp_online(void)
@@ -503,7 +503,7 @@ static void __init smp_online(void)
503 /* Save our processor parameters */ 503 /* Save our processor parameters */
504 smp_store_cpu_info(cpu_id); 504 smp_store_cpu_info(cpu_id);
505 505
506 cpu_set(cpu_id, cpu_online_map); 506 set_cpu_online(cpu_id, true);
507} 507}
508 508
509/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/ 509/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
diff --git a/arch/m32r/kernel/syscall_table.S b/arch/m32r/kernel/syscall_table.S
index 60536e271233..528f2e6ad064 100644
--- a/arch/m32r/kernel/syscall_table.S
+++ b/arch/m32r/kernel/syscall_table.S
@@ -324,3 +324,4 @@ ENTRY(sys_call_table)
324 .long sys_ni_syscall 324 .long sys_ni_syscall
325 .long sys_eventfd 325 .long sys_eventfd
326 .long sys_fallocate 326 .long sys_fallocate
327 .long sys_setns /* 325 */
diff --git a/arch/m32r/kernel/time.c b/arch/m32r/kernel/time.c
index bda86820bffd..84dd04048db9 100644
--- a/arch/m32r/kernel/time.c
+++ b/arch/m32r/kernel/time.c
@@ -107,15 +107,14 @@ u32 arch_gettimeoffset(void)
107 107
108/* 108/*
109 * timer_interrupt() needs to keep up the real-time clock, 109 * timer_interrupt() needs to keep up the real-time clock,
110 * as well as call the "do_timer()" routine every clocktick 110 * as well as call the "xtime_update()" routine every clocktick
111 */ 111 */
112static irqreturn_t timer_interrupt(int irq, void *dev_id) 112static irqreturn_t timer_interrupt(int irq, void *dev_id)
113{ 113{
114#ifndef CONFIG_SMP 114#ifndef CONFIG_SMP
115 profile_tick(CPU_PROFILING); 115 profile_tick(CPU_PROFILING);
116#endif 116#endif
117 /* XXX FIXME. Uh, the xtime_lock should be held here, no? */ 117 xtime_update(1);
118 do_timer(1);
119 118
120#ifndef CONFIG_SMP 119#ifndef CONFIG_SMP
121 update_process_times(user_mode(get_irq_regs())); 120 update_process_times(user_mode(get_irq_regs()));
diff --git a/arch/m32r/kernel/vmlinux.lds.S b/arch/m32r/kernel/vmlinux.lds.S
index 7da94eaa082b..018e4a711d79 100644
--- a/arch/m32r/kernel/vmlinux.lds.S
+++ b/arch/m32r/kernel/vmlinux.lds.S
@@ -44,6 +44,7 @@ SECTIONS
44 EXCEPTION_TABLE(16) 44 EXCEPTION_TABLE(16)
45 NOTES 45 NOTES
46 46
47 _sdata = .; /* Start of data section */
47 RODATA 48 RODATA
48 RW_DATA_SECTION(32, PAGE_SIZE, THREAD_SIZE) 49 RW_DATA_SECTION(32, PAGE_SIZE, THREAD_SIZE)
49 _edata = .; /* End of data section */ 50 _edata = .; /* End of data section */
@@ -53,7 +54,7 @@ SECTIONS
53 __init_begin = .; 54 __init_begin = .;
54 INIT_TEXT_SECTION(PAGE_SIZE) 55 INIT_TEXT_SECTION(PAGE_SIZE)
55 INIT_DATA_SECTION(16) 56 INIT_DATA_SECTION(16)
56 PERCPU(PAGE_SIZE) 57 PERCPU_SECTION(32)
57 . = ALIGN(PAGE_SIZE); 58 . = ALIGN(PAGE_SIZE);
58 __init_end = .; 59 __init_end = .;
59 /* freed after init ends here */ 60 /* freed after init ends here */
diff --git a/arch/m32r/mm/discontig.c b/arch/m32r/mm/discontig.c
index 5d2858f6eede..2c468e8b5853 100644
--- a/arch/m32r/mm/discontig.c
+++ b/arch/m32r/mm/discontig.c
@@ -149,6 +149,7 @@ unsigned long __init zone_sizes_init(void)
149 zholes_size[ZONE_DMA] = mp->holes; 149 zholes_size[ZONE_DMA] = mp->holes;
150 holes += zholes_size[ZONE_DMA]; 150 holes += zholes_size[ZONE_DMA];
151 151
152 node_set_state(nid, N_NORMAL_MEMORY);
152 free_area_init_node(nid, zones_size, start_pfn, zholes_size); 153 free_area_init_node(nid, zones_size, start_pfn, zholes_size);
153 } 154 }
154 155
diff --git a/arch/m32r/mm/fault.c b/arch/m32r/mm/fault.c
index b8ec002aef8e..2c9aeb453847 100644
--- a/arch/m32r/mm/fault.c
+++ b/arch/m32r/mm/fault.c
@@ -120,7 +120,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code,
120 120
121 /* When running in the kernel we expect faults to occur only to 121 /* When running in the kernel we expect faults to occur only to
122 * addresses in user space. All other faults represent errors in the 122 * addresses in user space. All other faults represent errors in the
123 * kernel and should generate an OOPS. Unfortunatly, in the case of an 123 * kernel and should generate an OOPS. Unfortunately, in the case of an
124 * erroneous fault occurring in a code path which already holds mmap_sem 124 * erroneous fault occurring in a code path which already holds mmap_sem
125 * we will deadlock attempting to validate the fault against the 125 * we will deadlock attempting to validate the fault against the
126 * address space. Luckily the kernel only validly references user 126 * address space. Luckily the kernel only validly references user
@@ -128,7 +128,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code,
128 * exceptions table. 128 * exceptions table.
129 * 129 *
130 * As the vast majority of faults will be valid we will only perform 130 * As the vast majority of faults will be valid we will only perform
131 * the source reference check when there is a possibilty of a deadlock. 131 * the source reference check when there is a possibility of a deadlock.
132 * Attempt to lock the address space, if we cannot we then validate the 132 * Attempt to lock the address space, if we cannot we then validate the
133 * source. If this is invalid we can skip the address space check, 133 * source. If this is invalid we can skip the address space check,
134 * thus avoiding the deadlock. 134 * thus avoiding the deadlock.
diff --git a/arch/m32r/mm/init.c b/arch/m32r/mm/init.c
index 73e2205ebf5a..78b660e903da 100644
--- a/arch/m32r/mm/init.c
+++ b/arch/m32r/mm/init.c
@@ -35,8 +35,6 @@ extern char __init_begin, __init_end;
35 35
36pgd_t swapper_pg_dir[1024]; 36pgd_t swapper_pg_dir[1024];
37 37
38DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
39
40/* 38/*
41 * Cache of MMU context last used. 39 * Cache of MMU context last used.
42 */ 40 */
diff --git a/arch/m32r/platforms/m32104ut/setup.c b/arch/m32r/platforms/m32104ut/setup.c
index 922fdfdadeaa..34671d32cefc 100644
--- a/arch/m32r/platforms/m32104ut/setup.c
+++ b/arch/m32r/platforms/m32104ut/setup.c
@@ -39,39 +39,30 @@ static void enable_m32104ut_irq(unsigned int irq)
39 outl(data, port); 39 outl(data, port);
40} 40}
41 41
42static void mask_and_ack_m32104ut(unsigned int irq) 42static void mask_m32104ut_irq(struct irq_data *data)
43{ 43{
44 disable_m32104ut_irq(irq); 44 disable_m32104ut_irq(data->irq);
45} 45}
46 46
47static void end_m32104ut_irq(unsigned int irq) 47static void unmask_m32104ut_irq(struct irq_data *data)
48{ 48{
49 enable_m32104ut_irq(irq); 49 enable_m32104ut_irq(data->irq);
50} 50}
51 51
52static unsigned int startup_m32104ut_irq(unsigned int irq) 52static void shutdown_m32104ut_irq(struct irq_data *data)
53{ 53{
54 enable_m32104ut_irq(irq); 54 unsigned int irq = data->irq;
55 return (0); 55 unsigned long port = irq2port(irq);
56}
57
58static void shutdown_m32104ut_irq(unsigned int irq)
59{
60 unsigned long port;
61 56
62 port = irq2port(irq);
63 outl(M32R_ICUCR_ILEVEL7, port); 57 outl(M32R_ICUCR_ILEVEL7, port);
64} 58}
65 59
66static struct irq_chip m32104ut_irq_type = 60static struct irq_chip m32104ut_irq_type =
67{ 61{
68 .typename = "M32104UT-IRQ", 62 .name = "M32104UT-IRQ",
69 .startup = startup_m32104ut_irq, 63 .irq_shutdown = shutdown_m32104ut_irq,
70 .shutdown = shutdown_m32104ut_irq, 64 .irq_unmask = unmask_m32104ut_irq,
71 .enable = enable_m32104ut_irq, 65 .irq_mask = mask_m32104ut_irq,
72 .disable = disable_m32104ut_irq,
73 .ack = mask_and_ack_m32104ut,
74 .end = end_m32104ut_irq
75}; 66};
76 67
77void __init init_IRQ(void) 68void __init init_IRQ(void)
@@ -85,36 +76,29 @@ void __init init_IRQ(void)
85 76
86#if defined(CONFIG_SMC91X) 77#if defined(CONFIG_SMC91X)
87 /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ 78 /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/
88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 79 irq_set_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type,
89 irq_desc[M32R_IRQ_INT0].chip = &m32104ut_irq_type; 80 handle_level_irq);
90 irq_desc[M32R_IRQ_INT0].action = 0; 81 /* "H" level sense */
91 irq_desc[M32R_IRQ_INT0].depth = 1; 82 cu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11;
92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */
93 disable_m32104ut_irq(M32R_IRQ_INT0); 83 disable_m32104ut_irq(M32R_IRQ_INT0);
94#endif /* CONFIG_SMC91X */ 84#endif /* CONFIG_SMC91X */
95 85
96 /* MFT2 : system timer */ 86 /* MFT2 : system timer */
97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 87 irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type,
98 irq_desc[M32R_IRQ_MFT2].chip = &m32104ut_irq_type; 88 handle_level_irq);
99 irq_desc[M32R_IRQ_MFT2].action = 0;
100 irq_desc[M32R_IRQ_MFT2].depth = 1;
101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 89 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
102 disable_m32104ut_irq(M32R_IRQ_MFT2); 90 disable_m32104ut_irq(M32R_IRQ_MFT2);
103 91
104#ifdef CONFIG_SERIAL_M32R_SIO 92#ifdef CONFIG_SERIAL_M32R_SIO
105 /* SIO0_R : uart receive data */ 93 /* SIO0_R : uart receive data */
106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 94 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type,
107 irq_desc[M32R_IRQ_SIO0_R].chip = &m32104ut_irq_type; 95 handle_level_irq);
108 irq_desc[M32R_IRQ_SIO0_R].action = 0;
109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
110 icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; 96 icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN;
111 disable_m32104ut_irq(M32R_IRQ_SIO0_R); 97 disable_m32104ut_irq(M32R_IRQ_SIO0_R);
112 98
113 /* SIO0_S : uart send data */ 99 /* SIO0_S : uart send data */
114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 100 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type,
115 irq_desc[M32R_IRQ_SIO0_S].chip = &m32104ut_irq_type; 101 handle_level_irq);
116 irq_desc[M32R_IRQ_SIO0_S].action = 0;
117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
118 icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; 102 icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN;
119 disable_m32104ut_irq(M32R_IRQ_SIO0_S); 103 disable_m32104ut_irq(M32R_IRQ_SIO0_S);
120#endif /* CONFIG_SERIAL_M32R_SIO */ 104#endif /* CONFIG_SERIAL_M32R_SIO */
diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c
index 9c1bc7487c1e..1053e1cb7401 100644
--- a/arch/m32r/platforms/m32700ut/setup.c
+++ b/arch/m32r/platforms/m32700ut/setup.c
@@ -45,39 +45,30 @@ static void enable_m32700ut_irq(unsigned int irq)
45 outl(data, port); 45 outl(data, port);
46} 46}
47 47
48static void mask_and_ack_m32700ut(unsigned int irq) 48static void mask_m32700ut(struct irq_data *data)
49{ 49{
50 disable_m32700ut_irq(irq); 50 disable_m32700ut_irq(data->irq);
51} 51}
52 52
53static void end_m32700ut_irq(unsigned int irq) 53static void unmask_m32700ut(struct irq_data *data)
54{ 54{
55 enable_m32700ut_irq(irq); 55 enable_m32700ut_irq(data->irq);
56} 56}
57 57
58static unsigned int startup_m32700ut_irq(unsigned int irq) 58static void shutdown_m32700ut(struct irq_data *data)
59{
60 enable_m32700ut_irq(irq);
61 return (0);
62}
63
64static void shutdown_m32700ut_irq(unsigned int irq)
65{ 59{
66 unsigned long port; 60 unsigned long port;
67 61
68 port = irq2port(irq); 62 port = irq2port(data->irq);
69 outl(M32R_ICUCR_ILEVEL7, port); 63 outl(M32R_ICUCR_ILEVEL7, port);
70} 64}
71 65
72static struct irq_chip m32700ut_irq_type = 66static struct irq_chip m32700ut_irq_type =
73{ 67{
74 .typename = "M32700UT-IRQ", 68 .name = "M32700UT-IRQ",
75 .startup = startup_m32700ut_irq, 69 .irq_shutdown = shutdown_m32700ut,
76 .shutdown = shutdown_m32700ut_irq, 70 .irq_mask = mask_m32700ut,
77 .enable = enable_m32700ut_irq, 71 .irq_unmask = unmask_m32700ut
78 .disable = disable_m32700ut_irq,
79 .ack = mask_and_ack_m32700ut,
80 .end = end_m32700ut_irq
81}; 72};
82 73
83/* 74/*
@@ -99,7 +90,6 @@ static void disable_m32700ut_pld_irq(unsigned int irq)
99 unsigned int pldirq; 90 unsigned int pldirq;
100 91
101 pldirq = irq2pldirq(irq); 92 pldirq = irq2pldirq(irq);
102// disable_m32700ut_irq(M32R_IRQ_INT1);
103 port = pldirq2port(pldirq); 93 port = pldirq2port(pldirq);
104 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7; 94 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
105 outw(data, port); 95 outw(data, port);
@@ -111,50 +101,38 @@ static void enable_m32700ut_pld_irq(unsigned int irq)
111 unsigned int pldirq; 101 unsigned int pldirq;
112 102
113 pldirq = irq2pldirq(irq); 103 pldirq = irq2pldirq(irq);
114// enable_m32700ut_irq(M32R_IRQ_INT1);
115 port = pldirq2port(pldirq); 104 port = pldirq2port(pldirq);
116 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6; 105 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
117 outw(data, port); 106 outw(data, port);
118} 107}
119 108
120static void mask_and_ack_m32700ut_pld(unsigned int irq) 109static void mask_m32700ut_pld(struct irq_data *data)
121{
122 disable_m32700ut_pld_irq(irq);
123// mask_and_ack_m32700ut(M32R_IRQ_INT1);
124}
125
126static void end_m32700ut_pld_irq(unsigned int irq)
127{ 110{
128 enable_m32700ut_pld_irq(irq); 111 disable_m32700ut_pld_irq(data->irq);
129 end_m32700ut_irq(M32R_IRQ_INT1);
130} 112}
131 113
132static unsigned int startup_m32700ut_pld_irq(unsigned int irq) 114static void unmask_m32700ut_pld(struct irq_data *data)
133{ 115{
134 enable_m32700ut_pld_irq(irq); 116 enable_m32700ut_pld_irq(data->irq);
135 return (0); 117 enable_m32700ut_irq(M32R_IRQ_INT1);
136} 118}
137 119
138static void shutdown_m32700ut_pld_irq(unsigned int irq) 120static void shutdown_m32700ut_pld_irq(struct irq_data *data)
139{ 121{
140 unsigned long port; 122 unsigned long port;
141 unsigned int pldirq; 123 unsigned int pldirq;
142 124
143 pldirq = irq2pldirq(irq); 125 pldirq = irq2pldirq(data->irq);
144// shutdown_m32700ut_irq(M32R_IRQ_INT1);
145 port = pldirq2port(pldirq); 126 port = pldirq2port(pldirq);
146 outw(PLD_ICUCR_ILEVEL7, port); 127 outw(PLD_ICUCR_ILEVEL7, port);
147} 128}
148 129
149static struct irq_chip m32700ut_pld_irq_type = 130static struct irq_chip m32700ut_pld_irq_type =
150{ 131{
151 .typename = "M32700UT-PLD-IRQ", 132 .name = "M32700UT-PLD-IRQ",
152 .startup = startup_m32700ut_pld_irq, 133 .irq_shutdown = shutdown_m32700ut_pld_irq,
153 .shutdown = shutdown_m32700ut_pld_irq, 134 .irq_mask = mask_m32700ut_pld,
154 .enable = enable_m32700ut_pld_irq, 135 .irq_unmask = unmask_m32700ut_pld,
155 .disable = disable_m32700ut_pld_irq,
156 .ack = mask_and_ack_m32700ut_pld,
157 .end = end_m32700ut_pld_irq
158}; 136};
159 137
160/* 138/*
@@ -188,42 +166,33 @@ static void enable_m32700ut_lanpld_irq(unsigned int irq)
188 outw(data, port); 166 outw(data, port);
189} 167}
190 168
191static void mask_and_ack_m32700ut_lanpld(unsigned int irq) 169static void mask_m32700ut_lanpld(struct irq_data *data)
192{ 170{
193 disable_m32700ut_lanpld_irq(irq); 171 disable_m32700ut_lanpld_irq(data->irq);
194} 172}
195 173
196static void end_m32700ut_lanpld_irq(unsigned int irq) 174static void unmask_m32700ut_lanpld(struct irq_data *data)
197{ 175{
198 enable_m32700ut_lanpld_irq(irq); 176 enable_m32700ut_lanpld_irq(data->irq);
199 end_m32700ut_irq(M32R_IRQ_INT0); 177 enable_m32700ut_irq(M32R_IRQ_INT0);
200}
201
202static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
203{
204 enable_m32700ut_lanpld_irq(irq);
205 return (0);
206} 178}
207 179
208static void shutdown_m32700ut_lanpld_irq(unsigned int irq) 180static void shutdown_m32700ut_lanpld(struct irq_data *data)
209{ 181{
210 unsigned long port; 182 unsigned long port;
211 unsigned int pldirq; 183 unsigned int pldirq;
212 184
213 pldirq = irq2lanpldirq(irq); 185 pldirq = irq2lanpldirq(data->irq);
214 port = lanpldirq2port(pldirq); 186 port = lanpldirq2port(pldirq);
215 outw(PLD_ICUCR_ILEVEL7, port); 187 outw(PLD_ICUCR_ILEVEL7, port);
216} 188}
217 189
218static struct irq_chip m32700ut_lanpld_irq_type = 190static struct irq_chip m32700ut_lanpld_irq_type =
219{ 191{
220 .typename = "M32700UT-PLD-LAN-IRQ", 192 .name = "M32700UT-PLD-LAN-IRQ",
221 .startup = startup_m32700ut_lanpld_irq, 193 .irq_shutdown = shutdown_m32700ut_lanpld,
222 .shutdown = shutdown_m32700ut_lanpld_irq, 194 .irq_mask = mask_m32700ut_lanpld,
223 .enable = enable_m32700ut_lanpld_irq, 195 .irq_unmask = unmask_m32700ut_lanpld,
224 .disable = disable_m32700ut_lanpld_irq,
225 .ack = mask_and_ack_m32700ut_lanpld,
226 .end = end_m32700ut_lanpld_irq
227}; 196};
228 197
229/* 198/*
@@ -257,143 +226,110 @@ static void enable_m32700ut_lcdpld_irq(unsigned int irq)
257 outw(data, port); 226 outw(data, port);
258} 227}
259 228
260static void mask_and_ack_m32700ut_lcdpld(unsigned int irq) 229static void mask_m32700ut_lcdpld(struct irq_data *data)
261{ 230{
262 disable_m32700ut_lcdpld_irq(irq); 231 disable_m32700ut_lcdpld_irq(data->irq);
263} 232}
264 233
265static void end_m32700ut_lcdpld_irq(unsigned int irq) 234static void unmask_m32700ut_lcdpld(struct irq_data *data)
266{ 235{
267 enable_m32700ut_lcdpld_irq(irq); 236 enable_m32700ut_lcdpld_irq(data->irq);
268 end_m32700ut_irq(M32R_IRQ_INT2); 237 enable_m32700ut_irq(M32R_IRQ_INT2);
269}
270
271static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
272{
273 enable_m32700ut_lcdpld_irq(irq);
274 return (0);
275} 238}
276 239
277static void shutdown_m32700ut_lcdpld_irq(unsigned int irq) 240static void shutdown_m32700ut_lcdpld(struct irq_data *data)
278{ 241{
279 unsigned long port; 242 unsigned long port;
280 unsigned int pldirq; 243 unsigned int pldirq;
281 244
282 pldirq = irq2lcdpldirq(irq); 245 pldirq = irq2lcdpldirq(data->irq);
283 port = lcdpldirq2port(pldirq); 246 port = lcdpldirq2port(pldirq);
284 outw(PLD_ICUCR_ILEVEL7, port); 247 outw(PLD_ICUCR_ILEVEL7, port);
285} 248}
286 249
287static struct irq_chip m32700ut_lcdpld_irq_type = 250static struct irq_chip m32700ut_lcdpld_irq_type =
288{ 251{
289 .typename = "M32700UT-PLD-LCD-IRQ", 252 .name = "M32700UT-PLD-LCD-IRQ",
290 .startup = startup_m32700ut_lcdpld_irq, 253 .irq_shutdown = shutdown_m32700ut_lcdpld,
291 .shutdown = shutdown_m32700ut_lcdpld_irq, 254 .irq_mask = mask_m32700ut_lcdpld,
292 .enable = enable_m32700ut_lcdpld_irq, 255 .irq_unmask = unmask_m32700ut_lcdpld,
293 .disable = disable_m32700ut_lcdpld_irq,
294 .ack = mask_and_ack_m32700ut_lcdpld,
295 .end = end_m32700ut_lcdpld_irq
296}; 256};
297 257
298void __init init_IRQ(void) 258void __init init_IRQ(void)
299{ 259{
300#if defined(CONFIG_SMC91X) 260#if defined(CONFIG_SMC91X)
301 /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/ 261 /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
302 irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED; 262 irq_set_chip_and_handler(M32700UT_LAN_IRQ_LAN,
303 irq_desc[M32700UT_LAN_IRQ_LAN].chip = &m32700ut_lanpld_irq_type; 263 &m32700ut_lanpld_irq_type, handle_level_irq);
304 irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;
305 irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
306 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ 264 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
307 disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN); 265 disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
308#endif /* CONFIG_SMC91X */ 266#endif /* CONFIG_SMC91X */
309 267
310 /* MFT2 : system timer */ 268 /* MFT2 : system timer */
311 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 269 irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
312 irq_desc[M32R_IRQ_MFT2].chip = &m32700ut_irq_type; 270 handle_level_irq);
313 irq_desc[M32R_IRQ_MFT2].action = 0;
314 irq_desc[M32R_IRQ_MFT2].depth = 1;
315 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 271 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
316 disable_m32700ut_irq(M32R_IRQ_MFT2); 272 disable_m32700ut_irq(M32R_IRQ_MFT2);
317 273
318 /* SIO0 : receive */ 274 /* SIO0 : receive */
319 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 275 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
320 irq_desc[M32R_IRQ_SIO0_R].chip = &m32700ut_irq_type; 276 handle_level_irq);
321 irq_desc[M32R_IRQ_SIO0_R].action = 0;
322 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
323 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 277 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
324 disable_m32700ut_irq(M32R_IRQ_SIO0_R); 278 disable_m32700ut_irq(M32R_IRQ_SIO0_R);
325 279
326 /* SIO0 : send */ 280 /* SIO0 : send */
327 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 281 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
328 irq_desc[M32R_IRQ_SIO0_S].chip = &m32700ut_irq_type; 282 handle_level_irq);
329 irq_desc[M32R_IRQ_SIO0_S].action = 0;
330 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
331 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 283 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
332 disable_m32700ut_irq(M32R_IRQ_SIO0_S); 284 disable_m32700ut_irq(M32R_IRQ_SIO0_S);
333 285
334 /* SIO1 : receive */ 286 /* SIO1 : receive */
335 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 287 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
336 irq_desc[M32R_IRQ_SIO1_R].chip = &m32700ut_irq_type; 288 handle_level_irq);
337 irq_desc[M32R_IRQ_SIO1_R].action = 0;
338 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
339 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 289 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
340 disable_m32700ut_irq(M32R_IRQ_SIO1_R); 290 disable_m32700ut_irq(M32R_IRQ_SIO1_R);
341 291
342 /* SIO1 : send */ 292 /* SIO1 : send */
343 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 293 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
344 irq_desc[M32R_IRQ_SIO1_S].chip = &m32700ut_irq_type; 294 handle_level_irq);
345 irq_desc[M32R_IRQ_SIO1_S].action = 0;
346 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
347 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 295 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
348 disable_m32700ut_irq(M32R_IRQ_SIO1_S); 296 disable_m32700ut_irq(M32R_IRQ_SIO1_S);
349 297
350 /* DMA1 : */ 298 /* DMA1 : */
351 irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; 299 irq_set_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
352 irq_desc[M32R_IRQ_DMA1].chip = &m32700ut_irq_type; 300 handle_level_irq);
353 irq_desc[M32R_IRQ_DMA1].action = 0;
354 irq_desc[M32R_IRQ_DMA1].depth = 1;
355 icu_data[M32R_IRQ_DMA1].icucr = 0; 301 icu_data[M32R_IRQ_DMA1].icucr = 0;
356 disable_m32700ut_irq(M32R_IRQ_DMA1); 302 disable_m32700ut_irq(M32R_IRQ_DMA1);
357 303
358#ifdef CONFIG_SERIAL_M32R_PLDSIO 304#ifdef CONFIG_SERIAL_M32R_PLDSIO
359 /* INT#1: SIO0 Receive on PLD */ 305 /* INT#1: SIO0 Receive on PLD */
360 irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; 306 irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
361 irq_desc[PLD_IRQ_SIO0_RCV].chip = &m32700ut_pld_irq_type; 307 handle_level_irq);
362 irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
363 irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
364 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 308 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
365 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV); 309 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
366 310
367 /* INT#1: SIO0 Send on PLD */ 311 /* INT#1: SIO0 Send on PLD */
368 irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; 312 irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
369 irq_desc[PLD_IRQ_SIO0_SND].chip = &m32700ut_pld_irq_type; 313 handle_level_irq);
370 irq_desc[PLD_IRQ_SIO0_SND].action = 0;
371 irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
372 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 314 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
373 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND); 315 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
374#endif /* CONFIG_SERIAL_M32R_PLDSIO */ 316#endif /* CONFIG_SERIAL_M32R_PLDSIO */
375 317
376 /* INT#1: CFC IREQ on PLD */ 318 /* INT#1: CFC IREQ on PLD */
377 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 319 irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
378 irq_desc[PLD_IRQ_CFIREQ].chip = &m32700ut_pld_irq_type; 320 handle_level_irq);
379 irq_desc[PLD_IRQ_CFIREQ].action = 0;
380 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
381 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ 321 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
382 disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ); 322 disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
383 323
384 /* INT#1: CFC Insert on PLD */ 324 /* INT#1: CFC Insert on PLD */
385 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 325 irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
386 irq_desc[PLD_IRQ_CFC_INSERT].chip = &m32700ut_pld_irq_type; 326 handle_level_irq);
387 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
388 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
389 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ 327 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
390 disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT); 328 disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
391 329
392 /* INT#1: CFC Eject on PLD */ 330 /* INT#1: CFC Eject on PLD */
393 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; 331 irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
394 irq_desc[PLD_IRQ_CFC_EJECT].chip = &m32700ut_pld_irq_type; 332 handle_level_irq);
395 irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
396 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
397 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ 333 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
398 disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT); 334 disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
399 335
@@ -413,13 +349,11 @@ void __init init_IRQ(void)
413 349
414#if defined(CONFIG_USB) 350#if defined(CONFIG_USB)
415 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ 351 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
352 irq_set_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1,
353 &m32700ut_lcdpld_irq_type, handle_level_irq);
416 354
417 irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; 355 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
418 irq_desc[M32700UT_LCD_IRQ_USB_INT1].chip = &m32700ut_lcdpld_irq_type; 356 disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
419 irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;
420 irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;
421 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
422 disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
423#endif 357#endif
424 /* 358 /*
425 * INT2# is used for BAT, USB, AUDIO 359 * INT2# is used for BAT, USB, AUDIO
@@ -432,10 +366,8 @@ void __init init_IRQ(void)
432 /* 366 /*
433 * INT3# is used for AR 367 * INT3# is used for AR
434 */ 368 */
435 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; 369 irq_set_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
436 irq_desc[M32R_IRQ_INT3].chip = &m32700ut_irq_type; 370 handle_level_irq);
437 irq_desc[M32R_IRQ_INT3].action = 0;
438 irq_desc[M32R_IRQ_INT3].depth = 1;
439 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 371 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
440 disable_m32700ut_irq(M32R_IRQ_INT3); 372 disable_m32700ut_irq(M32R_IRQ_INT3);
441#endif /* CONFIG_VIDEO_M32R_AR */ 373#endif /* CONFIG_VIDEO_M32R_AR */
diff --git a/arch/m32r/platforms/mappi/setup.c b/arch/m32r/platforms/mappi/setup.c
index fb4b17799b66..35130ac3f8d1 100644
--- a/arch/m32r/platforms/mappi/setup.c
+++ b/arch/m32r/platforms/mappi/setup.c
@@ -38,40 +38,30 @@ static void enable_mappi_irq(unsigned int irq)
38 outl(data, port); 38 outl(data, port);
39} 39}
40 40
41static void mask_and_ack_mappi(unsigned int irq) 41static void mask_mappi(struct irq_data *data)
42{ 42{
43 disable_mappi_irq(irq); 43 disable_mappi_irq(data->irq);
44} 44}
45 45
46static void end_mappi_irq(unsigned int irq) 46static void unmask_mappi(struct irq_data *data)
47{ 47{
48 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 48 enable_mappi_irq(data->irq);
49 enable_mappi_irq(irq);
50} 49}
51 50
52static unsigned int startup_mappi_irq(unsigned int irq) 51static void shutdown_mappi(struct irq_data *data)
53{
54 enable_mappi_irq(irq);
55 return (0);
56}
57
58static void shutdown_mappi_irq(unsigned int irq)
59{ 52{
60 unsigned long port; 53 unsigned long port;
61 54
62 port = irq2port(irq); 55 port = irq2port(data->irq);
63 outl(M32R_ICUCR_ILEVEL7, port); 56 outl(M32R_ICUCR_ILEVEL7, port);
64} 57}
65 58
66static struct irq_chip mappi_irq_type = 59static struct irq_chip mappi_irq_type =
67{ 60{
68 .typename = "MAPPI-IRQ", 61 .name = "MAPPI-IRQ",
69 .startup = startup_mappi_irq, 62 .irq_shutdown = shutdown_mappi,
70 .shutdown = shutdown_mappi_irq, 63 .irq_mask = mask_mappi,
71 .enable = enable_mappi_irq, 64 .irq_unmask = unmask_mappi,
72 .disable = disable_mappi_irq,
73 .ack = mask_and_ack_mappi,
74 .end = end_mappi_irq
75}; 65};
76 66
77void __init init_IRQ(void) 67void __init init_IRQ(void)
@@ -85,70 +75,54 @@ void __init init_IRQ(void)
85 75
86#ifdef CONFIG_NE2000 76#ifdef CONFIG_NE2000
87 /* INT0 : LAN controller (RTL8019AS) */ 77 /* INT0 : LAN controller (RTL8019AS) */
88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 78 irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type,
89 irq_desc[M32R_IRQ_INT0].chip = &mappi_irq_type; 79 handle_level_irq);
90 irq_desc[M32R_IRQ_INT0].action = NULL;
91 irq_desc[M32R_IRQ_INT0].depth = 1;
92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; 80 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
93 disable_mappi_irq(M32R_IRQ_INT0); 81 disable_mappi_irq(M32R_IRQ_INT0);
94#endif /* CONFIG_M32R_NE2000 */ 82#endif /* CONFIG_M32R_NE2000 */
95 83
96 /* MFT2 : system timer */ 84 /* MFT2 : system timer */
97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 85 irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
98 irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; 86 handle_level_irq);
99 irq_desc[M32R_IRQ_MFT2].action = NULL;
100 irq_desc[M32R_IRQ_MFT2].depth = 1;
101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 87 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
102 disable_mappi_irq(M32R_IRQ_MFT2); 88 disable_mappi_irq(M32R_IRQ_MFT2);
103 89
104#ifdef CONFIG_SERIAL_M32R_SIO 90#ifdef CONFIG_SERIAL_M32R_SIO
105 /* SIO0_R : uart receive data */ 91 /* SIO0_R : uart receive data */
106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 92 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
107 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; 93 handle_level_irq);
108 irq_desc[M32R_IRQ_SIO0_R].action = NULL;
109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
110 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 94 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
111 disable_mappi_irq(M32R_IRQ_SIO0_R); 95 disable_mappi_irq(M32R_IRQ_SIO0_R);
112 96
113 /* SIO0_S : uart send data */ 97 /* SIO0_S : uart send data */
114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 98 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
115 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; 99 handle_level_irq);
116 irq_desc[M32R_IRQ_SIO0_S].action = NULL;
117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
118 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 100 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
119 disable_mappi_irq(M32R_IRQ_SIO0_S); 101 disable_mappi_irq(M32R_IRQ_SIO0_S);
120 102
121 /* SIO1_R : uart receive data */ 103 /* SIO1_R : uart receive data */
122 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 104 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
123 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; 105 handle_level_irq);
124 irq_desc[M32R_IRQ_SIO1_R].action = NULL;
125 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
126 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 106 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
127 disable_mappi_irq(M32R_IRQ_SIO1_R); 107 disable_mappi_irq(M32R_IRQ_SIO1_R);
128 108
129 /* SIO1_S : uart send data */ 109 /* SIO1_S : uart send data */
130 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 110 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
131 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; 111 handle_level_irq);
132 irq_desc[M32R_IRQ_SIO1_S].action = NULL;
133 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
134 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 112 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
135 disable_mappi_irq(M32R_IRQ_SIO1_S); 113 disable_mappi_irq(M32R_IRQ_SIO1_S);
136#endif /* CONFIG_SERIAL_M32R_SIO */ 114#endif /* CONFIG_SERIAL_M32R_SIO */
137 115
138#if defined(CONFIG_M32R_PCC) 116#if defined(CONFIG_M32R_PCC)
139 /* INT1 : pccard0 interrupt */ 117 /* INT1 : pccard0 interrupt */
140 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; 118 irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type,
141 irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type; 119 handle_level_irq);
142 irq_desc[M32R_IRQ_INT1].action = NULL;
143 irq_desc[M32R_IRQ_INT1].depth = 1;
144 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; 120 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
145 disable_mappi_irq(M32R_IRQ_INT1); 121 disable_mappi_irq(M32R_IRQ_INT1);
146 122
147 /* INT2 : pccard1 interrupt */ 123 /* INT2 : pccard1 interrupt */
148 irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED; 124 irq_set_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type,
149 irq_desc[M32R_IRQ_INT2].chip = &mappi_irq_type; 125 handle_level_irq);
150 irq_desc[M32R_IRQ_INT2].action = NULL;
151 irq_desc[M32R_IRQ_INT2].depth = 1;
152 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; 126 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
153 disable_mappi_irq(M32R_IRQ_INT2); 127 disable_mappi_irq(M32R_IRQ_INT2);
154#endif /* CONFIG_M32RPCC */ 128#endif /* CONFIG_M32RPCC */
diff --git a/arch/m32r/platforms/mappi2/setup.c b/arch/m32r/platforms/mappi2/setup.c
index 6a65eda0a056..f3ed6b60a5f8 100644
--- a/arch/m32r/platforms/mappi2/setup.c
+++ b/arch/m32r/platforms/mappi2/setup.c
@@ -46,126 +46,97 @@ static void enable_mappi2_irq(unsigned int irq)
46 outl(data, port); 46 outl(data, port);
47} 47}
48 48
49static void mask_and_ack_mappi2(unsigned int irq) 49static void mask_mappi2(struct irq_data *data)
50{ 50{
51 disable_mappi2_irq(irq); 51 disable_mappi2_irq(data->irq);
52} 52}
53 53
54static void end_mappi2_irq(unsigned int irq) 54static void unmask_mappi2(struct irq_data *data)
55{ 55{
56 enable_mappi2_irq(irq); 56 enable_mappi2_irq(data->irq);
57} 57}
58 58
59static unsigned int startup_mappi2_irq(unsigned int irq) 59static void shutdown_mappi2(struct irq_data *data)
60{
61 enable_mappi2_irq(irq);
62 return (0);
63}
64
65static void shutdown_mappi2_irq(unsigned int irq)
66{ 60{
67 unsigned long port; 61 unsigned long port;
68 62
69 port = irq2port(irq); 63 port = irq2port(data->irq);
70 outl(M32R_ICUCR_ILEVEL7, port); 64 outl(M32R_ICUCR_ILEVEL7, port);
71} 65}
72 66
73static struct irq_chip mappi2_irq_type = 67static struct irq_chip mappi2_irq_type =
74{ 68{
75 .typename = "MAPPI2-IRQ", 69 .name = "MAPPI2-IRQ",
76 .startup = startup_mappi2_irq, 70 .irq_shutdown = shutdown_mappi2,
77 .shutdown = shutdown_mappi2_irq, 71 .irq_mask = mask_mappi2,
78 .enable = enable_mappi2_irq, 72 .irq_unmask = unmask_mappi2,
79 .disable = disable_mappi2_irq,
80 .ack = mask_and_ack_mappi2,
81 .end = end_mappi2_irq
82}; 73};
83 74
84void __init init_IRQ(void) 75void __init init_IRQ(void)
85{ 76{
86#if defined(CONFIG_SMC91X) 77#if defined(CONFIG_SMC91X)
87 /* INT0 : LAN controller (SMC91111) */ 78 /* INT0 : LAN controller (SMC91111) */
88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 79 irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type,
89 irq_desc[M32R_IRQ_INT0].chip = &mappi2_irq_type; 80 handle_level_irq);
90 irq_desc[M32R_IRQ_INT0].action = 0;
91 irq_desc[M32R_IRQ_INT0].depth = 1;
92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 81 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
93 disable_mappi2_irq(M32R_IRQ_INT0); 82 disable_mappi2_irq(M32R_IRQ_INT0);
94#endif /* CONFIG_SMC91X */ 83#endif /* CONFIG_SMC91X */
95 84
96 /* MFT2 : system timer */ 85 /* MFT2 : system timer */
97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 86 irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type,
98 irq_desc[M32R_IRQ_MFT2].chip = &mappi2_irq_type; 87 handle_level_irq);
99 irq_desc[M32R_IRQ_MFT2].action = 0;
100 irq_desc[M32R_IRQ_MFT2].depth = 1;
101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 88 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
102 disable_mappi2_irq(M32R_IRQ_MFT2); 89 disable_mappi2_irq(M32R_IRQ_MFT2);
103 90
104#ifdef CONFIG_SERIAL_M32R_SIO 91#ifdef CONFIG_SERIAL_M32R_SIO
105 /* SIO0_R : uart receive data */ 92 /* SIO0_R : uart receive data */
106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 93 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type,
107 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi2_irq_type; 94 handle_level_irq);
108 irq_desc[M32R_IRQ_SIO0_R].action = 0;
109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
110 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 95 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
111 disable_mappi2_irq(M32R_IRQ_SIO0_R); 96 disable_mappi2_irq(M32R_IRQ_SIO0_R);
112 97
113 /* SIO0_S : uart send data */ 98 /* SIO0_S : uart send data */
114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 99 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type,
115 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi2_irq_type; 100 handle_level_irq);
116 irq_desc[M32R_IRQ_SIO0_S].action = 0;
117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
118 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 101 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
119 disable_mappi2_irq(M32R_IRQ_SIO0_S); 102 disable_mappi2_irq(M32R_IRQ_SIO0_S);
120 /* SIO1_R : uart receive data */ 103 /* SIO1_R : uart receive data */
121 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 104 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type,
122 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi2_irq_type; 105 handle_level_irq);
123 irq_desc[M32R_IRQ_SIO1_R].action = 0;
124 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
125 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 106 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
126 disable_mappi2_irq(M32R_IRQ_SIO1_R); 107 disable_mappi2_irq(M32R_IRQ_SIO1_R);
127 108
128 /* SIO1_S : uart send data */ 109 /* SIO1_S : uart send data */
129 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 110 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type,
130 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi2_irq_type; 111 handle_level_irq);
131 irq_desc[M32R_IRQ_SIO1_S].action = 0;
132 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
133 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 112 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
134 disable_mappi2_irq(M32R_IRQ_SIO1_S); 113 disable_mappi2_irq(M32R_IRQ_SIO1_S);
135#endif /* CONFIG_M32R_USE_DBG_CONSOLE */ 114#endif /* CONFIG_M32R_USE_DBG_CONSOLE */
136 115
137#if defined(CONFIG_USB) 116#if defined(CONFIG_USB)
138 /* INT1 : USB Host controller interrupt */ 117 /* INT1 : USB Host controller interrupt */
139 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; 118 irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type,
140 irq_desc[M32R_IRQ_INT1].chip = &mappi2_irq_type; 119 handle_level_irq);
141 irq_desc[M32R_IRQ_INT1].action = 0;
142 irq_desc[M32R_IRQ_INT1].depth = 1;
143 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; 120 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
144 disable_mappi2_irq(M32R_IRQ_INT1); 121 disable_mappi2_irq(M32R_IRQ_INT1);
145#endif /* CONFIG_USB */ 122#endif /* CONFIG_USB */
146 123
147 /* ICUCR40: CFC IREQ */ 124 /* ICUCR40: CFC IREQ */
148 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 125 irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type,
149 irq_desc[PLD_IRQ_CFIREQ].chip = &mappi2_irq_type; 126 handle_level_irq);
150 irq_desc[PLD_IRQ_CFIREQ].action = 0;
151 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
152 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; 127 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
153 disable_mappi2_irq(PLD_IRQ_CFIREQ); 128 disable_mappi2_irq(PLD_IRQ_CFIREQ);
154 129
155#if defined(CONFIG_M32R_CFC) 130#if defined(CONFIG_M32R_CFC)
156 /* ICUCR41: CFC Insert */ 131 /* ICUCR41: CFC Insert */
157 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 132 irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type,
158 irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi2_irq_type; 133 handle_level_irq);
159 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
160 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
161 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; 134 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
162 disable_mappi2_irq(PLD_IRQ_CFC_INSERT); 135 disable_mappi2_irq(PLD_IRQ_CFC_INSERT);
163 136
164 /* ICUCR42: CFC Eject */ 137 /* ICUCR42: CFC Eject */
165 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; 138 irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type,
166 irq_desc[PLD_IRQ_CFC_EJECT].chip = &mappi2_irq_type; 139 handle_level_irq);
167 irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
168 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
169 icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 140 icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
170 disable_mappi2_irq(PLD_IRQ_CFC_EJECT); 141 disable_mappi2_irq(PLD_IRQ_CFC_EJECT);
171#endif /* CONFIG_MAPPI2_CFC */ 142#endif /* CONFIG_MAPPI2_CFC */
diff --git a/arch/m32r/platforms/mappi3/setup.c b/arch/m32r/platforms/mappi3/setup.c
index 9c337aeac94b..2408e356ad10 100644
--- a/arch/m32r/platforms/mappi3/setup.c
+++ b/arch/m32r/platforms/mappi3/setup.c
@@ -46,128 +46,98 @@ static void enable_mappi3_irq(unsigned int irq)
46 outl(data, port); 46 outl(data, port);
47} 47}
48 48
49static void mask_and_ack_mappi3(unsigned int irq) 49static void mask_mappi3(struct irq_data *data)
50{ 50{
51 disable_mappi3_irq(irq); 51 disable_mappi3_irq(data->irq);
52} 52}
53 53
54static void end_mappi3_irq(unsigned int irq) 54static void unmask_mappi3(struct irq_data *data)
55{ 55{
56 enable_mappi3_irq(irq); 56 enable_mappi3_irq(data->irq);
57} 57}
58 58
59static unsigned int startup_mappi3_irq(unsigned int irq) 59static void shutdown_mappi3(struct irq_data *data)
60{
61 enable_mappi3_irq(irq);
62 return (0);
63}
64
65static void shutdown_mappi3_irq(unsigned int irq)
66{ 60{
67 unsigned long port; 61 unsigned long port;
68 62
69 port = irq2port(irq); 63 port = irq2port(data->irq);
70 outl(M32R_ICUCR_ILEVEL7, port); 64 outl(M32R_ICUCR_ILEVEL7, port);
71} 65}
72 66
73static struct irq_chip mappi3_irq_type = 67static struct irq_chip mappi3_irq_type = {
74{ 68 .name = "MAPPI3-IRQ",
75 .typename = "MAPPI3-IRQ", 69 .irq_shutdown = shutdown_mappi3,
76 .startup = startup_mappi3_irq, 70 .irq_mask = mask_mappi3,
77 .shutdown = shutdown_mappi3_irq, 71 .irq_unmask = unmask_mappi3,
78 .enable = enable_mappi3_irq,
79 .disable = disable_mappi3_irq,
80 .ack = mask_and_ack_mappi3,
81 .end = end_mappi3_irq
82}; 72};
83 73
84void __init init_IRQ(void) 74void __init init_IRQ(void)
85{ 75{
86#if defined(CONFIG_SMC91X) 76#if defined(CONFIG_SMC91X)
87 /* INT0 : LAN controller (SMC91111) */ 77 /* INT0 : LAN controller (SMC91111) */
88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 78 irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type,
89 irq_desc[M32R_IRQ_INT0].chip = &mappi3_irq_type; 79 handle_level_irq);
90 irq_desc[M32R_IRQ_INT0].action = 0;
91 irq_desc[M32R_IRQ_INT0].depth = 1;
92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 80 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
93 disable_mappi3_irq(M32R_IRQ_INT0); 81 disable_mappi3_irq(M32R_IRQ_INT0);
94#endif /* CONFIG_SMC91X */ 82#endif /* CONFIG_SMC91X */
95 83
96 /* MFT2 : system timer */ 84 /* MFT2 : system timer */
97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 85 irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type,
98 irq_desc[M32R_IRQ_MFT2].chip = &mappi3_irq_type; 86 handle_level_irq);
99 irq_desc[M32R_IRQ_MFT2].action = 0;
100 irq_desc[M32R_IRQ_MFT2].depth = 1;
101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 87 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
102 disable_mappi3_irq(M32R_IRQ_MFT2); 88 disable_mappi3_irq(M32R_IRQ_MFT2);
103 89
104#ifdef CONFIG_SERIAL_M32R_SIO 90#ifdef CONFIG_SERIAL_M32R_SIO
105 /* SIO0_R : uart receive data */ 91 /* SIO0_R : uart receive data */
106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 92 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type,
107 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi3_irq_type; 93 handle_level_irq);
108 irq_desc[M32R_IRQ_SIO0_R].action = 0;
109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
110 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 94 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
111 disable_mappi3_irq(M32R_IRQ_SIO0_R); 95 disable_mappi3_irq(M32R_IRQ_SIO0_R);
112 96
113 /* SIO0_S : uart send data */ 97 /* SIO0_S : uart send data */
114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 98 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type,
115 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi3_irq_type; 99 handle_level_irq);
116 irq_desc[M32R_IRQ_SIO0_S].action = 0;
117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
118 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 100 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
119 disable_mappi3_irq(M32R_IRQ_SIO0_S); 101 disable_mappi3_irq(M32R_IRQ_SIO0_S);
120 /* SIO1_R : uart receive data */ 102 /* SIO1_R : uart receive data */
121 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 103 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type,
122 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi3_irq_type; 104 handle_level_irq);
123 irq_desc[M32R_IRQ_SIO1_R].action = 0;
124 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
125 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 105 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
126 disable_mappi3_irq(M32R_IRQ_SIO1_R); 106 disable_mappi3_irq(M32R_IRQ_SIO1_R);
127 107
128 /* SIO1_S : uart send data */ 108 /* SIO1_S : uart send data */
129 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 109 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type,
130 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi3_irq_type; 110 handle_level_irq);
131 irq_desc[M32R_IRQ_SIO1_S].action = 0;
132 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
133 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 111 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
134 disable_mappi3_irq(M32R_IRQ_SIO1_S); 112 disable_mappi3_irq(M32R_IRQ_SIO1_S);
135#endif /* CONFIG_M32R_USE_DBG_CONSOLE */ 113#endif /* CONFIG_M32R_USE_DBG_CONSOLE */
136 114
137#if defined(CONFIG_USB) 115#if defined(CONFIG_USB)
138 /* INT1 : USB Host controller interrupt */ 116 /* INT1 : USB Host controller interrupt */
139 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; 117 irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type,
140 irq_desc[M32R_IRQ_INT1].chip = &mappi3_irq_type; 118 handle_level_irq);
141 irq_desc[M32R_IRQ_INT1].action = 0;
142 irq_desc[M32R_IRQ_INT1].depth = 1;
143 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; 119 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
144 disable_mappi3_irq(M32R_IRQ_INT1); 120 disable_mappi3_irq(M32R_IRQ_INT1);
145#endif /* CONFIG_USB */ 121#endif /* CONFIG_USB */
146 122
147 /* CFC IREQ */ 123 /* CFC IREQ */
148 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 124 irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type,
149 irq_desc[PLD_IRQ_CFIREQ].chip = &mappi3_irq_type; 125 handle_level_irq);
150 irq_desc[PLD_IRQ_CFIREQ].action = 0;
151 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
152 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; 126 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
153 disable_mappi3_irq(PLD_IRQ_CFIREQ); 127 disable_mappi3_irq(PLD_IRQ_CFIREQ);
154 128
155#if defined(CONFIG_M32R_CFC) 129#if defined(CONFIG_M32R_CFC)
156 /* ICUCR41: CFC Insert & eject */ 130 /* ICUCR41: CFC Insert & eject */
157 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 131 irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type,
158 irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi3_irq_type; 132 handle_level_irq);
159 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
160 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
161 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; 133 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
162 disable_mappi3_irq(PLD_IRQ_CFC_INSERT); 134 disable_mappi3_irq(PLD_IRQ_CFC_INSERT);
163 135
164#endif /* CONFIG_M32R_CFC */ 136#endif /* CONFIG_M32R_CFC */
165 137
166 /* IDE IREQ */ 138 /* IDE IREQ */
167 irq_desc[PLD_IRQ_IDEIREQ].status = IRQ_DISABLED; 139 irq_set_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type,
168 irq_desc[PLD_IRQ_IDEIREQ].chip = &mappi3_irq_type; 140 handle_level_irq);
169 irq_desc[PLD_IRQ_IDEIREQ].action = 0;
170 irq_desc[PLD_IRQ_IDEIREQ].depth = 1; /* disable nested irq */
171 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 141 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
172 disable_mappi3_irq(PLD_IRQ_IDEIREQ); 142 disable_mappi3_irq(PLD_IRQ_IDEIREQ);
173 143
diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c
index ed865741c38d..83b46b067a17 100644
--- a/arch/m32r/platforms/oaks32r/setup.c
+++ b/arch/m32r/platforms/oaks32r/setup.c
@@ -37,39 +37,30 @@ static void enable_oaks32r_irq(unsigned int irq)
37 outl(data, port); 37 outl(data, port);
38} 38}
39 39
40static void mask_and_ack_mappi(unsigned int irq) 40static void mask_oaks32r(struct irq_data *data)
41{ 41{
42 disable_oaks32r_irq(irq); 42 disable_oaks32r_irq(data->irq);
43} 43}
44 44
45static void end_oaks32r_irq(unsigned int irq) 45static void unmask_oaks32r(struct irq_data *data)
46{ 46{
47 enable_oaks32r_irq(irq); 47 enable_oaks32r_irq(data->irq);
48} 48}
49 49
50static unsigned int startup_oaks32r_irq(unsigned int irq) 50static void shutdown_oaks32r(struct irq_data *data)
51{
52 enable_oaks32r_irq(irq);
53 return (0);
54}
55
56static void shutdown_oaks32r_irq(unsigned int irq)
57{ 51{
58 unsigned long port; 52 unsigned long port;
59 53
60 port = irq2port(irq); 54 port = irq2port(data->irq);
61 outl(M32R_ICUCR_ILEVEL7, port); 55 outl(M32R_ICUCR_ILEVEL7, port);
62} 56}
63 57
64static struct irq_chip oaks32r_irq_type = 58static struct irq_chip oaks32r_irq_type =
65{ 59{
66 .typename = "OAKS32R-IRQ", 60 .name = "OAKS32R-IRQ",
67 .startup = startup_oaks32r_irq, 61 .irq_shutdown = shutdown_oaks32r,
68 .shutdown = shutdown_oaks32r_irq, 62 .irq_mask = mask_oaks32r,
69 .enable = enable_oaks32r_irq, 63 .irq_unmask = unmask_oaks32r,
70 .disable = disable_oaks32r_irq,
71 .ack = mask_and_ack_mappi,
72 .end = end_oaks32r_irq
73}; 64};
74 65
75void __init init_IRQ(void) 66void __init init_IRQ(void)
@@ -83,52 +74,40 @@ void __init init_IRQ(void)
83 74
84#ifdef CONFIG_NE2000 75#ifdef CONFIG_NE2000
85 /* INT3 : LAN controller (RTL8019AS) */ 76 /* INT3 : LAN controller (RTL8019AS) */
86 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; 77 irq_set_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type,
87 irq_desc[M32R_IRQ_INT3].chip = &oaks32r_irq_type; 78 handle_level_irq);
88 irq_desc[M32R_IRQ_INT3].action = 0;
89 irq_desc[M32R_IRQ_INT3].depth = 1;
90 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 79 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
91 disable_oaks32r_irq(M32R_IRQ_INT3); 80 disable_oaks32r_irq(M32R_IRQ_INT3);
92#endif /* CONFIG_M32R_NE2000 */ 81#endif /* CONFIG_M32R_NE2000 */
93 82
94 /* MFT2 : system timer */ 83 /* MFT2 : system timer */
95 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 84 irq_set_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type,
96 irq_desc[M32R_IRQ_MFT2].chip = &oaks32r_irq_type; 85 handle_level_irq);
97 irq_desc[M32R_IRQ_MFT2].action = 0;
98 irq_desc[M32R_IRQ_MFT2].depth = 1;
99 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 86 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
100 disable_oaks32r_irq(M32R_IRQ_MFT2); 87 disable_oaks32r_irq(M32R_IRQ_MFT2);
101 88
102#ifdef CONFIG_SERIAL_M32R_SIO 89#ifdef CONFIG_SERIAL_M32R_SIO
103 /* SIO0_R : uart receive data */ 90 /* SIO0_R : uart receive data */
104 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 91 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type,
105 irq_desc[M32R_IRQ_SIO0_R].chip = &oaks32r_irq_type; 92 handle_level_irq);
106 irq_desc[M32R_IRQ_SIO0_R].action = 0;
107 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
108 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 93 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
109 disable_oaks32r_irq(M32R_IRQ_SIO0_R); 94 disable_oaks32r_irq(M32R_IRQ_SIO0_R);
110 95
111 /* SIO0_S : uart send data */ 96 /* SIO0_S : uart send data */
112 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 97 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type,
113 irq_desc[M32R_IRQ_SIO0_S].chip = &oaks32r_irq_type; 98 handle_level_irq);
114 irq_desc[M32R_IRQ_SIO0_S].action = 0;
115 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
116 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 99 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
117 disable_oaks32r_irq(M32R_IRQ_SIO0_S); 100 disable_oaks32r_irq(M32R_IRQ_SIO0_S);
118 101
119 /* SIO1_R : uart receive data */ 102 /* SIO1_R : uart receive data */
120 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 103 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type,
121 irq_desc[M32R_IRQ_SIO1_R].chip = &oaks32r_irq_type; 104 handle_level_irq);
122 irq_desc[M32R_IRQ_SIO1_R].action = 0;
123 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
124 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 105 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
125 disable_oaks32r_irq(M32R_IRQ_SIO1_R); 106 disable_oaks32r_irq(M32R_IRQ_SIO1_R);
126 107
127 /* SIO1_S : uart send data */ 108 /* SIO1_S : uart send data */
128 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 109 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type,
129 irq_desc[M32R_IRQ_SIO1_S].chip = &oaks32r_irq_type; 110 handle_level_irq);
130 irq_desc[M32R_IRQ_SIO1_S].action = 0;
131 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
132 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 111 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
133 disable_oaks32r_irq(M32R_IRQ_SIO1_S); 112 disable_oaks32r_irq(M32R_IRQ_SIO1_S);
134#endif /* CONFIG_SERIAL_M32R_SIO */ 113#endif /* CONFIG_SERIAL_M32R_SIO */
diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c
index 80d680657019..32660705f5fd 100644
--- a/arch/m32r/platforms/opsput/setup.c
+++ b/arch/m32r/platforms/opsput/setup.c
@@ -46,39 +46,30 @@ static void enable_opsput_irq(unsigned int irq)
46 outl(data, port); 46 outl(data, port);
47} 47}
48 48
49static void mask_and_ack_opsput(unsigned int irq) 49static void mask_opsput(struct irq_data *data)
50{ 50{
51 disable_opsput_irq(irq); 51 disable_opsput_irq(data->irq);
52} 52}
53 53
54static void end_opsput_irq(unsigned int irq) 54static void unmask_opsput(struct irq_data *data)
55{ 55{
56 enable_opsput_irq(irq); 56 enable_opsput_irq(data->irq);
57} 57}
58 58
59static unsigned int startup_opsput_irq(unsigned int irq) 59static void shutdown_opsput(struct irq_data *data)
60{
61 enable_opsput_irq(irq);
62 return (0);
63}
64
65static void shutdown_opsput_irq(unsigned int irq)
66{ 60{
67 unsigned long port; 61 unsigned long port;
68 62
69 port = irq2port(irq); 63 port = irq2port(data->irq);
70 outl(M32R_ICUCR_ILEVEL7, port); 64 outl(M32R_ICUCR_ILEVEL7, port);
71} 65}
72 66
73static struct irq_chip opsput_irq_type = 67static struct irq_chip opsput_irq_type =
74{ 68{
75 .typename = "OPSPUT-IRQ", 69 .name = "OPSPUT-IRQ",
76 .startup = startup_opsput_irq, 70 .irq_shutdown = shutdown_opsput,
77 .shutdown = shutdown_opsput_irq, 71 .irq_mask = mask_opsput,
78 .enable = enable_opsput_irq, 72 .irq_unmask = unmask_opsput,
79 .disable = disable_opsput_irq,
80 .ack = mask_and_ack_opsput,
81 .end = end_opsput_irq
82}; 73};
83 74
84/* 75/*
@@ -100,7 +91,6 @@ static void disable_opsput_pld_irq(unsigned int irq)
100 unsigned int pldirq; 91 unsigned int pldirq;
101 92
102 pldirq = irq2pldirq(irq); 93 pldirq = irq2pldirq(irq);
103// disable_opsput_irq(M32R_IRQ_INT1);
104 port = pldirq2port(pldirq); 94 port = pldirq2port(pldirq);
105 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7; 95 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
106 outw(data, port); 96 outw(data, port);
@@ -112,50 +102,38 @@ static void enable_opsput_pld_irq(unsigned int irq)
112 unsigned int pldirq; 102 unsigned int pldirq;
113 103
114 pldirq = irq2pldirq(irq); 104 pldirq = irq2pldirq(irq);
115// enable_opsput_irq(M32R_IRQ_INT1);
116 port = pldirq2port(pldirq); 105 port = pldirq2port(pldirq);
117 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6; 106 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
118 outw(data, port); 107 outw(data, port);
119} 108}
120 109
121static void mask_and_ack_opsput_pld(unsigned int irq) 110static void mask_opsput_pld(struct irq_data *data)
122{
123 disable_opsput_pld_irq(irq);
124// mask_and_ack_opsput(M32R_IRQ_INT1);
125}
126
127static void end_opsput_pld_irq(unsigned int irq)
128{ 111{
129 enable_opsput_pld_irq(irq); 112 disable_opsput_pld_irq(data->irq);
130 end_opsput_irq(M32R_IRQ_INT1);
131} 113}
132 114
133static unsigned int startup_opsput_pld_irq(unsigned int irq) 115static void unmask_opsput_pld(struct irq_data *data)
134{ 116{
135 enable_opsput_pld_irq(irq); 117 enable_opsput_pld_irq(data->irq);
136 return (0); 118 enable_opsput_irq(M32R_IRQ_INT1);
137} 119}
138 120
139static void shutdown_opsput_pld_irq(unsigned int irq) 121static void shutdown_opsput_pld(struct irq_data *data)
140{ 122{
141 unsigned long port; 123 unsigned long port;
142 unsigned int pldirq; 124 unsigned int pldirq;
143 125
144 pldirq = irq2pldirq(irq); 126 pldirq = irq2pldirq(data->irq);
145// shutdown_opsput_irq(M32R_IRQ_INT1);
146 port = pldirq2port(pldirq); 127 port = pldirq2port(pldirq);
147 outw(PLD_ICUCR_ILEVEL7, port); 128 outw(PLD_ICUCR_ILEVEL7, port);
148} 129}
149 130
150static struct irq_chip opsput_pld_irq_type = 131static struct irq_chip opsput_pld_irq_type =
151{ 132{
152 .typename = "OPSPUT-PLD-IRQ", 133 .name = "OPSPUT-PLD-IRQ",
153 .startup = startup_opsput_pld_irq, 134 .irq_shutdown = shutdown_opsput_pld,
154 .shutdown = shutdown_opsput_pld_irq, 135 .irq_mask = mask_opsput_pld,
155 .enable = enable_opsput_pld_irq, 136 .irq_unmask = unmask_opsput_pld,
156 .disable = disable_opsput_pld_irq,
157 .ack = mask_and_ack_opsput_pld,
158 .end = end_opsput_pld_irq
159}; 137};
160 138
161/* 139/*
@@ -189,42 +167,33 @@ static void enable_opsput_lanpld_irq(unsigned int irq)
189 outw(data, port); 167 outw(data, port);
190} 168}
191 169
192static void mask_and_ack_opsput_lanpld(unsigned int irq) 170static void mask_opsput_lanpld(struct irq_data *data)
193{
194 disable_opsput_lanpld_irq(irq);
195}
196
197static void end_opsput_lanpld_irq(unsigned int irq)
198{ 171{
199 enable_opsput_lanpld_irq(irq); 172 disable_opsput_lanpld_irq(data->irq);
200 end_opsput_irq(M32R_IRQ_INT0);
201} 173}
202 174
203static unsigned int startup_opsput_lanpld_irq(unsigned int irq) 175static void unmask_opsput_lanpld(struct irq_data *data)
204{ 176{
205 enable_opsput_lanpld_irq(irq); 177 enable_opsput_lanpld_irq(data->irq);
206 return (0); 178 enable_opsput_irq(M32R_IRQ_INT0);
207} 179}
208 180
209static void shutdown_opsput_lanpld_irq(unsigned int irq) 181static void shutdown_opsput_lanpld(struct irq_data *data)
210{ 182{
211 unsigned long port; 183 unsigned long port;
212 unsigned int pldirq; 184 unsigned int pldirq;
213 185
214 pldirq = irq2lanpldirq(irq); 186 pldirq = irq2lanpldirq(data->irq);
215 port = lanpldirq2port(pldirq); 187 port = lanpldirq2port(pldirq);
216 outw(PLD_ICUCR_ILEVEL7, port); 188 outw(PLD_ICUCR_ILEVEL7, port);
217} 189}
218 190
219static struct irq_chip opsput_lanpld_irq_type = 191static struct irq_chip opsput_lanpld_irq_type =
220{ 192{
221 .typename = "OPSPUT-PLD-LAN-IRQ", 193 .name = "OPSPUT-PLD-LAN-IRQ",
222 .startup = startup_opsput_lanpld_irq, 194 .irq_shutdown = shutdown_opsput_lanpld,
223 .shutdown = shutdown_opsput_lanpld_irq, 195 .irq_mask = mask_opsput_lanpld,
224 .enable = enable_opsput_lanpld_irq, 196 .irq_unmask = unmask_opsput_lanpld,
225 .disable = disable_opsput_lanpld_irq,
226 .ack = mask_and_ack_opsput_lanpld,
227 .end = end_opsput_lanpld_irq
228}; 197};
229 198
230/* 199/*
@@ -258,143 +227,109 @@ static void enable_opsput_lcdpld_irq(unsigned int irq)
258 outw(data, port); 227 outw(data, port);
259} 228}
260 229
261static void mask_and_ack_opsput_lcdpld(unsigned int irq) 230static void mask_opsput_lcdpld(struct irq_data *data)
262{
263 disable_opsput_lcdpld_irq(irq);
264}
265
266static void end_opsput_lcdpld_irq(unsigned int irq)
267{ 231{
268 enable_opsput_lcdpld_irq(irq); 232 disable_opsput_lcdpld_irq(data->irq);
269 end_opsput_irq(M32R_IRQ_INT2);
270} 233}
271 234
272static unsigned int startup_opsput_lcdpld_irq(unsigned int irq) 235static void unmask_opsput_lcdpld(struct irq_data *data)
273{ 236{
274 enable_opsput_lcdpld_irq(irq); 237 enable_opsput_lcdpld_irq(data->irq);
275 return (0); 238 enable_opsput_irq(M32R_IRQ_INT2);
276} 239}
277 240
278static void shutdown_opsput_lcdpld_irq(unsigned int irq) 241static void shutdown_opsput_lcdpld(struct irq_data *data)
279{ 242{
280 unsigned long port; 243 unsigned long port;
281 unsigned int pldirq; 244 unsigned int pldirq;
282 245
283 pldirq = irq2lcdpldirq(irq); 246 pldirq = irq2lcdpldirq(data->irq);
284 port = lcdpldirq2port(pldirq); 247 port = lcdpldirq2port(pldirq);
285 outw(PLD_ICUCR_ILEVEL7, port); 248 outw(PLD_ICUCR_ILEVEL7, port);
286} 249}
287 250
288static struct irq_chip opsput_lcdpld_irq_type = 251static struct irq_chip opsput_lcdpld_irq_type = {
289{ 252 .name = "OPSPUT-PLD-LCD-IRQ",
290 "OPSPUT-PLD-LCD-IRQ", 253 .irq_shutdown = shutdown_opsput_lcdpld,
291 startup_opsput_lcdpld_irq, 254 .irq_mask = mask_opsput_lcdpld,
292 shutdown_opsput_lcdpld_irq, 255 .irq_unmask = unmask_opsput_lcdpld,
293 enable_opsput_lcdpld_irq,
294 disable_opsput_lcdpld_irq,
295 mask_and_ack_opsput_lcdpld,
296 end_opsput_lcdpld_irq
297}; 256};
298 257
299void __init init_IRQ(void) 258void __init init_IRQ(void)
300{ 259{
301#if defined(CONFIG_SMC91X) 260#if defined(CONFIG_SMC91X)
302 /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ 261 /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
303 irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED; 262 irq_set_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type,
304 irq_desc[OPSPUT_LAN_IRQ_LAN].chip = &opsput_lanpld_irq_type; 263 handle_level_irq);
305 irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0;
306 irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
307 lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ 264 lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
308 disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN); 265 disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
309#endif /* CONFIG_SMC91X */ 266#endif /* CONFIG_SMC91X */
310 267
311 /* MFT2 : system timer */ 268 /* MFT2 : system timer */
312 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 269 irq_set_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type,
313 irq_desc[M32R_IRQ_MFT2].chip = &opsput_irq_type; 270 handle_level_irq);
314 irq_desc[M32R_IRQ_MFT2].action = 0;
315 irq_desc[M32R_IRQ_MFT2].depth = 1;
316 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 271 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
317 disable_opsput_irq(M32R_IRQ_MFT2); 272 disable_opsput_irq(M32R_IRQ_MFT2);
318 273
319 /* SIO0 : receive */ 274 /* SIO0 : receive */
320 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 275 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type,
321 irq_desc[M32R_IRQ_SIO0_R].chip = &opsput_irq_type; 276 handle_level_irq);
322 irq_desc[M32R_IRQ_SIO0_R].action = 0;
323 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
324 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 277 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
325 disable_opsput_irq(M32R_IRQ_SIO0_R); 278 disable_opsput_irq(M32R_IRQ_SIO0_R);
326 279
327 /* SIO0 : send */ 280 /* SIO0 : send */
328 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 281 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type,
329 irq_desc[M32R_IRQ_SIO0_S].chip = &opsput_irq_type; 282 handle_level_irq);
330 irq_desc[M32R_IRQ_SIO0_S].action = 0;
331 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
332 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 283 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
333 disable_opsput_irq(M32R_IRQ_SIO0_S); 284 disable_opsput_irq(M32R_IRQ_SIO0_S);
334 285
335 /* SIO1 : receive */ 286 /* SIO1 : receive */
336 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 287 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type,
337 irq_desc[M32R_IRQ_SIO1_R].chip = &opsput_irq_type; 288 handle_level_irq);
338 irq_desc[M32R_IRQ_SIO1_R].action = 0;
339 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
340 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 289 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
341 disable_opsput_irq(M32R_IRQ_SIO1_R); 290 disable_opsput_irq(M32R_IRQ_SIO1_R);
342 291
343 /* SIO1 : send */ 292 /* SIO1 : send */
344 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 293 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type,
345 irq_desc[M32R_IRQ_SIO1_S].chip = &opsput_irq_type; 294 handle_level_irq);
346 irq_desc[M32R_IRQ_SIO1_S].action = 0;
347 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
348 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 295 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
349 disable_opsput_irq(M32R_IRQ_SIO1_S); 296 disable_opsput_irq(M32R_IRQ_SIO1_S);
350 297
351 /* DMA1 : */ 298 /* DMA1 : */
352 irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; 299 irq_set_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type,
353 irq_desc[M32R_IRQ_DMA1].chip = &opsput_irq_type; 300 handle_level_irq);
354 irq_desc[M32R_IRQ_DMA1].action = 0;
355 irq_desc[M32R_IRQ_DMA1].depth = 1;
356 icu_data[M32R_IRQ_DMA1].icucr = 0; 301 icu_data[M32R_IRQ_DMA1].icucr = 0;
357 disable_opsput_irq(M32R_IRQ_DMA1); 302 disable_opsput_irq(M32R_IRQ_DMA1);
358 303
359#ifdef CONFIG_SERIAL_M32R_PLDSIO 304#ifdef CONFIG_SERIAL_M32R_PLDSIO
360 /* INT#1: SIO0 Receive on PLD */ 305 /* INT#1: SIO0 Receive on PLD */
361 irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; 306 irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type,
362 irq_desc[PLD_IRQ_SIO0_RCV].chip = &opsput_pld_irq_type; 307 handle_level_irq);
363 irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
364 irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
365 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 308 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
366 disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); 309 disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
367 310
368 /* INT#1: SIO0 Send on PLD */ 311 /* INT#1: SIO0 Send on PLD */
369 irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; 312 irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type,
370 irq_desc[PLD_IRQ_SIO0_SND].chip = &opsput_pld_irq_type; 313 handle_level_irq);
371 irq_desc[PLD_IRQ_SIO0_SND].action = 0;
372 irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
373 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 314 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
374 disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); 315 disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
375#endif /* CONFIG_SERIAL_M32R_PLDSIO */ 316#endif /* CONFIG_SERIAL_M32R_PLDSIO */
376 317
377 /* INT#1: CFC IREQ on PLD */ 318 /* INT#1: CFC IREQ on PLD */
378 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 319 irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type,
379 irq_desc[PLD_IRQ_CFIREQ].chip = &opsput_pld_irq_type; 320 handle_level_irq);
380 irq_desc[PLD_IRQ_CFIREQ].action = 0;
381 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
382 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ 321 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
383 disable_opsput_pld_irq(PLD_IRQ_CFIREQ); 322 disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
384 323
385 /* INT#1: CFC Insert on PLD */ 324 /* INT#1: CFC Insert on PLD */
386 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 325 irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type,
387 irq_desc[PLD_IRQ_CFC_INSERT].chip = &opsput_pld_irq_type; 326 handle_level_irq);
388 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
389 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
390 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ 327 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
391 disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); 328 disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
392 329
393 /* INT#1: CFC Eject on PLD */ 330 /* INT#1: CFC Eject on PLD */
394 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; 331 irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type,
395 irq_desc[PLD_IRQ_CFC_EJECT].chip = &opsput_pld_irq_type; 332 handle_level_irq);
396 irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
397 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
398 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ 333 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
399 disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); 334 disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
400 335
@@ -413,14 +348,11 @@ void __init init_IRQ(void)
413 enable_opsput_irq(M32R_IRQ_INT1); 348 enable_opsput_irq(M32R_IRQ_INT1);
414 349
415#if defined(CONFIG_USB) 350#if defined(CONFIG_USB)
416 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ 351 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
417 352 irq_set_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1,
418 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; 353 &opsput_lcdpld_irq_type, handle_level_irq);
419 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].chip = &opsput_lcdpld_irq_type; 354 lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
420 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0; 355 disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
421 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1;
422 lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
423 disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
424#endif 356#endif
425 /* 357 /*
426 * INT2# is used for BAT, USB, AUDIO 358 * INT2# is used for BAT, USB, AUDIO
@@ -433,10 +365,8 @@ void __init init_IRQ(void)
433 /* 365 /*
434 * INT3# is used for AR 366 * INT3# is used for AR
435 */ 367 */
436 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; 368 irq_set_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type,
437 irq_desc[M32R_IRQ_INT3].chip = &opsput_irq_type; 369 handle_level_irq);
438 irq_desc[M32R_IRQ_INT3].action = 0;
439 irq_desc[M32R_IRQ_INT3].depth = 1;
440 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 370 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
441 disable_opsput_irq(M32R_IRQ_INT3); 371 disable_opsput_irq(M32R_IRQ_INT3);
442#endif /* CONFIG_VIDEO_M32R_AR */ 372#endif /* CONFIG_VIDEO_M32R_AR */
diff --git a/arch/m32r/platforms/usrv/setup.c b/arch/m32r/platforms/usrv/setup.c
index 757302660af8..0c7a1e8c77b0 100644
--- a/arch/m32r/platforms/usrv/setup.c
+++ b/arch/m32r/platforms/usrv/setup.c
@@ -37,39 +37,30 @@ static void enable_mappi_irq(unsigned int irq)
37 outl(data, port); 37 outl(data, port);
38} 38}
39 39
40static void mask_and_ack_mappi(unsigned int irq) 40static void mask_mappi(struct irq_data *data)
41{ 41{
42 disable_mappi_irq(irq); 42 disable_mappi_irq(data->irq);
43} 43}
44 44
45static void end_mappi_irq(unsigned int irq) 45static void unmask_mappi(struct irq_data *data)
46{ 46{
47 enable_mappi_irq(irq); 47 enable_mappi_irq(data->irq);
48} 48}
49 49
50static unsigned int startup_mappi_irq(unsigned int irq) 50static void shutdown_mappi(struct irq_data *data)
51{
52 enable_mappi_irq(irq);
53 return 0;
54}
55
56static void shutdown_mappi_irq(unsigned int irq)
57{ 51{
58 unsigned long port; 52 unsigned long port;
59 53
60 port = irq2port(irq); 54 port = irq2port(data->irq);
61 outl(M32R_ICUCR_ILEVEL7, port); 55 outl(M32R_ICUCR_ILEVEL7, port);
62} 56}
63 57
64static struct irq_chip mappi_irq_type = 58static struct irq_chip mappi_irq_type =
65{ 59{
66 .typename = "M32700-IRQ", 60 .name = "M32700-IRQ",
67 .startup = startup_mappi_irq, 61 .irq_shutdown = shutdown_mappi,
68 .shutdown = shutdown_mappi_irq, 62 .irq_mask = mask_mappi,
69 .enable = enable_mappi_irq, 63 .irq_unmask = unmask_mappi,
70 .disable = disable_mappi_irq,
71 .ack = mask_and_ack_mappi,
72 .end = end_mappi_irq
73}; 64};
74 65
75/* 66/*
@@ -107,42 +98,33 @@ static void enable_m32700ut_pld_irq(unsigned int irq)
107 outw(data, port); 98 outw(data, port);
108} 99}
109 100
110static void mask_and_ack_m32700ut_pld(unsigned int irq) 101static void mask_m32700ut_pld(struct irq_data *data)
111{ 102{
112 disable_m32700ut_pld_irq(irq); 103 disable_m32700ut_pld_irq(data->irq);
113} 104}
114 105
115static void end_m32700ut_pld_irq(unsigned int irq) 106static void unmask_m32700ut_pld(struct irq_data *data)
116{ 107{
117 enable_m32700ut_pld_irq(irq); 108 enable_m32700ut_pld_irq(data->irq);
118 end_mappi_irq(M32R_IRQ_INT1); 109 enable_mappi_irq(M32R_IRQ_INT1);
119}
120
121static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
122{
123 enable_m32700ut_pld_irq(irq);
124 return 0;
125} 110}
126 111
127static void shutdown_m32700ut_pld_irq(unsigned int irq) 112static void shutdown_m32700ut_pld(struct irq_data *data)
128{ 113{
129 unsigned long port; 114 unsigned long port;
130 unsigned int pldirq; 115 unsigned int pldirq;
131 116
132 pldirq = irq2pldirq(irq); 117 pldirq = irq2pldirq(data->irq);
133 port = pldirq2port(pldirq); 118 port = pldirq2port(pldirq);
134 outw(PLD_ICUCR_ILEVEL7, port); 119 outw(PLD_ICUCR_ILEVEL7, port);
135} 120}
136 121
137static struct irq_chip m32700ut_pld_irq_type = 122static struct irq_chip m32700ut_pld_irq_type =
138{ 123{
139 .typename = "USRV-PLD-IRQ", 124 .name = "USRV-PLD-IRQ",
140 .startup = startup_m32700ut_pld_irq, 125 .irq_shutdown = shutdown_m32700ut_pld,
141 .shutdown = shutdown_m32700ut_pld_irq, 126 .irq_mask = mask_m32700ut_pld,
142 .enable = enable_m32700ut_pld_irq, 127 .irq_unmask = unmask_m32700ut_pld,
143 .disable = disable_m32700ut_pld_irq,
144 .ack = mask_and_ack_m32700ut_pld,
145 .end = end_m32700ut_pld_irq
146}; 128};
147 129
148void __init init_IRQ(void) 130void __init init_IRQ(void)
@@ -156,53 +138,42 @@ void __init init_IRQ(void)
156 once++; 138 once++;
157 139
158 /* MFT2 : system timer */ 140 /* MFT2 : system timer */
159 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 141 irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
160 irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; 142 handle_level_irq);
161 irq_desc[M32R_IRQ_MFT2].action = 0;
162 irq_desc[M32R_IRQ_MFT2].depth = 1;
163 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 143 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
164 disable_mappi_irq(M32R_IRQ_MFT2); 144 disable_mappi_irq(M32R_IRQ_MFT2);
165 145
166#if defined(CONFIG_SERIAL_M32R_SIO) 146#if defined(CONFIG_SERIAL_M32R_SIO)
167 /* SIO0_R : uart receive data */ 147 /* SIO0_R : uart receive data */
168 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 148 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
169 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; 149 handle_level_irq);
170 irq_desc[M32R_IRQ_SIO0_R].action = 0;
171 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
172 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 150 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
173 disable_mappi_irq(M32R_IRQ_SIO0_R); 151 disable_mappi_irq(M32R_IRQ_SIO0_R);
174 152
175 /* SIO0_S : uart send data */ 153 /* SIO0_S : uart send data */
176 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 154 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
177 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; 155 handle_level_irq);
178 irq_desc[M32R_IRQ_SIO0_S].action = 0;
179 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
180 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 156 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
181 disable_mappi_irq(M32R_IRQ_SIO0_S); 157 disable_mappi_irq(M32R_IRQ_SIO0_S);
182 158
183 /* SIO1_R : uart receive data */ 159 /* SIO1_R : uart receive data */
184 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 160 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
185 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; 161 handle_level_irq);
186 irq_desc[M32R_IRQ_SIO1_R].action = 0;
187 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
188 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 162 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
189 disable_mappi_irq(M32R_IRQ_SIO1_R); 163 disable_mappi_irq(M32R_IRQ_SIO1_R);
190 164
191 /* SIO1_S : uart send data */ 165 /* SIO1_S : uart send data */
192 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 166 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
193 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; 167 handle_level_irq);
194 irq_desc[M32R_IRQ_SIO1_S].action = 0;
195 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
196 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 168 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
197 disable_mappi_irq(M32R_IRQ_SIO1_S); 169 disable_mappi_irq(M32R_IRQ_SIO1_S);
198#endif /* CONFIG_SERIAL_M32R_SIO */ 170#endif /* CONFIG_SERIAL_M32R_SIO */
199 171
200 /* INT#67-#71: CFC#0 IREQ on PLD */ 172 /* INT#67-#71: CFC#0 IREQ on PLD */
201 for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) { 173 for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) {
202 irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED; 174 irq_set_chip_and_handler(PLD_IRQ_CF0 + i,
203 irq_desc[PLD_IRQ_CF0 + i].chip = &m32700ut_pld_irq_type; 175 &m32700ut_pld_irq_type,
204 irq_desc[PLD_IRQ_CF0 + i].action = 0; 176 handle_level_irq);
205 irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */
206 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr 177 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
207 = PLD_ICUCR_ISMOD01; /* 'L' level sense */ 178 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
208 disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i); 179 disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i);
@@ -210,19 +181,15 @@ void __init init_IRQ(void)
210 181
211#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 182#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
212 /* INT#76: 16552D#0 IREQ on PLD */ 183 /* INT#76: 16552D#0 IREQ on PLD */
213 irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED; 184 irq_set_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type,
214 irq_desc[PLD_IRQ_UART0].chip = &m32700ut_pld_irq_type; 185 handle_level_irq);
215 irq_desc[PLD_IRQ_UART0].action = 0;
216 irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */
217 pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr 186 pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
218 = PLD_ICUCR_ISMOD03; /* 'H' level sense */ 187 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
219 disable_m32700ut_pld_irq(PLD_IRQ_UART0); 188 disable_m32700ut_pld_irq(PLD_IRQ_UART0);
220 189
221 /* INT#77: 16552D#1 IREQ on PLD */ 190 /* INT#77: 16552D#1 IREQ on PLD */
222 irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED; 191 irq_set_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type,
223 irq_desc[PLD_IRQ_UART1].chip = &m32700ut_pld_irq_type; 192 handle_level_irq);
224 irq_desc[PLD_IRQ_UART1].action = 0;
225 irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */
226 pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr 193 pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
227 = PLD_ICUCR_ISMOD03; /* 'H' level sense */ 194 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
228 disable_m32700ut_pld_irq(PLD_IRQ_UART1); 195 disable_m32700ut_pld_irq(PLD_IRQ_UART1);
@@ -230,10 +197,8 @@ void __init init_IRQ(void)
230 197
231#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) 198#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
232 /* INT#80: AK4524 IREQ on PLD */ 199 /* INT#80: AK4524 IREQ on PLD */
233 irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED; 200 irq_set_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type,
234 irq_desc[PLD_IRQ_SNDINT].chip = &m32700ut_pld_irq_type; 201 handle_level_irq);
235 irq_desc[PLD_IRQ_SNDINT].action = 0;
236 irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */
237 pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr 202 pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
238 = PLD_ICUCR_ISMOD01; /* 'L' level sense */ 203 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
239 disable_m32700ut_pld_irq(PLD_IRQ_SNDINT); 204 disable_m32700ut_pld_irq(PLD_IRQ_SNDINT);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-31 02:52:43 -0400