diff options
author | Trond Myklebust <Trond.Myklebust@netapp.com> | 2006-07-03 13:49:45 -0400 |
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committer | Trond Myklebust <Trond.Myklebust@netapp.com> | 2006-07-03 13:49:45 -0400 |
commit | 026477c1141b67e98e3bd8bdedb7d4b88a3ecd09 (patch) | |
tree | 2624a44924c625c367f3cebf937853b9da2de282 /arch/m32r/kernel/setup_opsput.c | |
parent | 9f2fa466383ce100b90fe52cb4489d7a26bf72a9 (diff) | |
parent | 29454dde27d8e340bb1987bad9aa504af7081eba (diff) |
Merge branch 'master' of /home/trondmy/kernel/linux-2.6/
Diffstat (limited to 'arch/m32r/kernel/setup_opsput.c')
-rw-r--r-- | arch/m32r/kernel/setup_opsput.c | 29 |
1 files changed, 14 insertions, 15 deletions
diff --git a/arch/m32r/kernel/setup_opsput.c b/arch/m32r/kernel/setup_opsput.c index 548e8fc7949b..61d3b01cbe07 100644 --- a/arch/m32r/kernel/setup_opsput.c +++ b/arch/m32r/kernel/setup_opsput.c | |||
@@ -12,7 +12,6 @@ | |||
12 | * archive for more details. | 12 | * archive for more details. |
13 | */ | 13 | */ |
14 | 14 | ||
15 | #include <linux/config.h> | ||
16 | #include <linux/irq.h> | 15 | #include <linux/irq.h> |
17 | #include <linux/kernel.h> | 16 | #include <linux/kernel.h> |
18 | #include <linux/init.h> | 17 | #include <linux/init.h> |
@@ -302,7 +301,7 @@ void __init init_IRQ(void) | |||
302 | #if defined(CONFIG_SMC91X) | 301 | #if defined(CONFIG_SMC91X) |
303 | /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ | 302 | /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ |
304 | irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED; | 303 | irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED; |
305 | irq_desc[OPSPUT_LAN_IRQ_LAN].handler = &opsput_lanpld_irq_type; | 304 | irq_desc[OPSPUT_LAN_IRQ_LAN].chip = &opsput_lanpld_irq_type; |
306 | irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0; | 305 | irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0; |
307 | irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */ | 306 | irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */ |
308 | lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ | 307 | lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ |
@@ -311,7 +310,7 @@ void __init init_IRQ(void) | |||
311 | 310 | ||
312 | /* MFT2 : system timer */ | 311 | /* MFT2 : system timer */ |
313 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 312 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; |
314 | irq_desc[M32R_IRQ_MFT2].handler = &opsput_irq_type; | 313 | irq_desc[M32R_IRQ_MFT2].chip = &opsput_irq_type; |
315 | irq_desc[M32R_IRQ_MFT2].action = 0; | 314 | irq_desc[M32R_IRQ_MFT2].action = 0; |
316 | irq_desc[M32R_IRQ_MFT2].depth = 1; | 315 | irq_desc[M32R_IRQ_MFT2].depth = 1; |
317 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 316 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
@@ -319,7 +318,7 @@ void __init init_IRQ(void) | |||
319 | 318 | ||
320 | /* SIO0 : receive */ | 319 | /* SIO0 : receive */ |
321 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 320 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; |
322 | irq_desc[M32R_IRQ_SIO0_R].handler = &opsput_irq_type; | 321 | irq_desc[M32R_IRQ_SIO0_R].chip = &opsput_irq_type; |
323 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | 322 | irq_desc[M32R_IRQ_SIO0_R].action = 0; |
324 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | 323 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; |
325 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 324 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
@@ -327,7 +326,7 @@ void __init init_IRQ(void) | |||
327 | 326 | ||
328 | /* SIO0 : send */ | 327 | /* SIO0 : send */ |
329 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 328 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; |
330 | irq_desc[M32R_IRQ_SIO0_S].handler = &opsput_irq_type; | 329 | irq_desc[M32R_IRQ_SIO0_S].chip = &opsput_irq_type; |
331 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | 330 | irq_desc[M32R_IRQ_SIO0_S].action = 0; |
332 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | 331 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; |
333 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 332 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
@@ -335,7 +334,7 @@ void __init init_IRQ(void) | |||
335 | 334 | ||
336 | /* SIO1 : receive */ | 335 | /* SIO1 : receive */ |
337 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 336 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; |
338 | irq_desc[M32R_IRQ_SIO1_R].handler = &opsput_irq_type; | 337 | irq_desc[M32R_IRQ_SIO1_R].chip = &opsput_irq_type; |
339 | irq_desc[M32R_IRQ_SIO1_R].action = 0; | 338 | irq_desc[M32R_IRQ_SIO1_R].action = 0; |
340 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | 339 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; |
341 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 340 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
@@ -343,7 +342,7 @@ void __init init_IRQ(void) | |||
343 | 342 | ||
344 | /* SIO1 : send */ | 343 | /* SIO1 : send */ |
345 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 344 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; |
346 | irq_desc[M32R_IRQ_SIO1_S].handler = &opsput_irq_type; | 345 | irq_desc[M32R_IRQ_SIO1_S].chip = &opsput_irq_type; |
347 | irq_desc[M32R_IRQ_SIO1_S].action = 0; | 346 | irq_desc[M32R_IRQ_SIO1_S].action = 0; |
348 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | 347 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; |
349 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 348 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
@@ -351,7 +350,7 @@ void __init init_IRQ(void) | |||
351 | 350 | ||
352 | /* DMA1 : */ | 351 | /* DMA1 : */ |
353 | irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; | 352 | irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; |
354 | irq_desc[M32R_IRQ_DMA1].handler = &opsput_irq_type; | 353 | irq_desc[M32R_IRQ_DMA1].chip = &opsput_irq_type; |
355 | irq_desc[M32R_IRQ_DMA1].action = 0; | 354 | irq_desc[M32R_IRQ_DMA1].action = 0; |
356 | irq_desc[M32R_IRQ_DMA1].depth = 1; | 355 | irq_desc[M32R_IRQ_DMA1].depth = 1; |
357 | icu_data[M32R_IRQ_DMA1].icucr = 0; | 356 | icu_data[M32R_IRQ_DMA1].icucr = 0; |
@@ -360,7 +359,7 @@ void __init init_IRQ(void) | |||
360 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | 359 | #ifdef CONFIG_SERIAL_M32R_PLDSIO |
361 | /* INT#1: SIO0 Receive on PLD */ | 360 | /* INT#1: SIO0 Receive on PLD */ |
362 | irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; | 361 | irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; |
363 | irq_desc[PLD_IRQ_SIO0_RCV].handler = &opsput_pld_irq_type; | 362 | irq_desc[PLD_IRQ_SIO0_RCV].chip = &opsput_pld_irq_type; |
364 | irq_desc[PLD_IRQ_SIO0_RCV].action = 0; | 363 | irq_desc[PLD_IRQ_SIO0_RCV].action = 0; |
365 | irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */ | 364 | irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */ |
366 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; | 365 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; |
@@ -368,7 +367,7 @@ void __init init_IRQ(void) | |||
368 | 367 | ||
369 | /* INT#1: SIO0 Send on PLD */ | 368 | /* INT#1: SIO0 Send on PLD */ |
370 | irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; | 369 | irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; |
371 | irq_desc[PLD_IRQ_SIO0_SND].handler = &opsput_pld_irq_type; | 370 | irq_desc[PLD_IRQ_SIO0_SND].chip = &opsput_pld_irq_type; |
372 | irq_desc[PLD_IRQ_SIO0_SND].action = 0; | 371 | irq_desc[PLD_IRQ_SIO0_SND].action = 0; |
373 | irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */ | 372 | irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */ |
374 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; | 373 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; |
@@ -378,7 +377,7 @@ void __init init_IRQ(void) | |||
378 | #if defined(CONFIG_M32R_CFC) | 377 | #if defined(CONFIG_M32R_CFC) |
379 | /* INT#1: CFC IREQ on PLD */ | 378 | /* INT#1: CFC IREQ on PLD */ |
380 | irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; | 379 | irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; |
381 | irq_desc[PLD_IRQ_CFIREQ].handler = &opsput_pld_irq_type; | 380 | irq_desc[PLD_IRQ_CFIREQ].chip = &opsput_pld_irq_type; |
382 | irq_desc[PLD_IRQ_CFIREQ].action = 0; | 381 | irq_desc[PLD_IRQ_CFIREQ].action = 0; |
383 | irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ | 382 | irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ |
384 | pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ | 383 | pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ |
@@ -386,7 +385,7 @@ void __init init_IRQ(void) | |||
386 | 385 | ||
387 | /* INT#1: CFC Insert on PLD */ | 386 | /* INT#1: CFC Insert on PLD */ |
388 | irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; | 387 | irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; |
389 | irq_desc[PLD_IRQ_CFC_INSERT].handler = &opsput_pld_irq_type; | 388 | irq_desc[PLD_IRQ_CFC_INSERT].chip = &opsput_pld_irq_type; |
390 | irq_desc[PLD_IRQ_CFC_INSERT].action = 0; | 389 | irq_desc[PLD_IRQ_CFC_INSERT].action = 0; |
391 | irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ | 390 | irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ |
392 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ | 391 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ |
@@ -394,7 +393,7 @@ void __init init_IRQ(void) | |||
394 | 393 | ||
395 | /* INT#1: CFC Eject on PLD */ | 394 | /* INT#1: CFC Eject on PLD */ |
396 | irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; | 395 | irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; |
397 | irq_desc[PLD_IRQ_CFC_EJECT].handler = &opsput_pld_irq_type; | 396 | irq_desc[PLD_IRQ_CFC_EJECT].chip = &opsput_pld_irq_type; |
398 | irq_desc[PLD_IRQ_CFC_EJECT].action = 0; | 397 | irq_desc[PLD_IRQ_CFC_EJECT].action = 0; |
399 | irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ | 398 | irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ |
400 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ | 399 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ |
@@ -420,7 +419,7 @@ void __init init_IRQ(void) | |||
420 | outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ | 419 | outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ |
421 | 420 | ||
422 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; | 421 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; |
423 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].handler = &opsput_lcdpld_irq_type; | 422 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].chip = &opsput_lcdpld_irq_type; |
424 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0; | 423 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0; |
425 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1; | 424 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1; |
426 | lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ | 425 | lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ |
@@ -438,7 +437,7 @@ void __init init_IRQ(void) | |||
438 | * INT3# is used for AR | 437 | * INT3# is used for AR |
439 | */ | 438 | */ |
440 | irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; | 439 | irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; |
441 | irq_desc[M32R_IRQ_INT3].handler = &opsput_irq_type; | 440 | irq_desc[M32R_IRQ_INT3].chip = &opsput_irq_type; |
442 | irq_desc[M32R_IRQ_INT3].action = 0; | 441 | irq_desc[M32R_IRQ_INT3].action = 0; |
443 | irq_desc[M32R_IRQ_INT3].depth = 1; | 442 | irq_desc[M32R_IRQ_INT3].depth = 1; |
444 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; | 443 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |