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authorRuss Anderson <rja@sgi.com>2008-01-03 11:23:49 -0500
committerTony Luck <tony.luck@intel.com>2008-01-03 16:22:54 -0500
commit2022c1f136067f673964dcaffa1cae1008ddcd74 (patch)
treee62db392a3d730156fe8ca62d9e7d507f3e1a8de /arch/ia64/sn
parent4ca8ad7e4c38cd7f32b11e60418d06fa912a1a37 (diff)
[IA64] Update Altix nofault code
Montecito and Montvale behaves slightly differently than previous Itanium processors, resulting in the MCA due to a failed PIO read to sometimes surfacing outside the nofault code. This code is based on discussions with Intel CPU architects and verified at customer sites. Signed-off-by: Russ Anderson <rja@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/sn')
-rw-r--r--arch/ia64/sn/kernel/xp_nofault.S10
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/ia64/sn/kernel/xp_nofault.S b/arch/ia64/sn/kernel/xp_nofault.S
index 54e8973b6e99..98e7c7dbfdd8 100644
--- a/arch/ia64/sn/kernel/xp_nofault.S
+++ b/arch/ia64/sn/kernel/xp_nofault.S
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (c) 2004-2005 Silicon Graphics, Inc. All Rights Reserved. 6 * Copyright (c) 2004-2007 Silicon Graphics, Inc. All Rights Reserved.
7 */ 7 */
8 8
9 9
@@ -14,6 +14,11 @@
14 * PIO read fails, the MCA handler will force the error to look 14 * PIO read fails, the MCA handler will force the error to look
15 * corrected and vector to the xp_error_PIOR which will return an error. 15 * corrected and vector to the xp_error_PIOR which will return an error.
16 * 16 *
17 * The definition of "consumption" and the time it takes for an MCA
18 * to surface is processor implementation specific. This code
19 * is sufficient on Itanium through the Montvale processor family.
20 * It may need to be adjusted for future processor implementations.
21 *
17 * extern int xp_nofault_PIOR(void *remote_register); 22 * extern int xp_nofault_PIOR(void *remote_register);
18 */ 23 */
19 24
@@ -22,11 +27,10 @@ xp_nofault_PIOR:
22 mov r8=r0 // Stage a success return value 27 mov r8=r0 // Stage a success return value
23 ld8.acq r9=[r32];; // PIO Read the specified register 28 ld8.acq r9=[r32];; // PIO Read the specified register
24 adds r9=1,r9;; // Add to force consumption 29 adds r9=1,r9;; // Add to force consumption
25 or r9=r9,r9;; // Or to force consumption 30 srlz.i;; // Allow time for MCA to surface
26 br.ret.sptk.many b0;; // Return success 31 br.ret.sptk.many b0;; // Return success
27 32
28 .global xp_error_PIOR 33 .global xp_error_PIOR
29xp_error_PIOR: 34xp_error_PIOR:
30 mov r8=1 // Return value of 1 35 mov r8=1 // Return value of 1
31 br.ret.sptk.many b0;; // Return failure 36 br.ret.sptk.many b0;; // Return failure
32