aboutsummaryrefslogtreecommitdiffstats
path: root/arch/ia64/kernel/perfmon_montecito.h
diff options
context:
space:
mode:
authorRuss Anderson <rja@sgi.com>2006-10-25 18:59:47 -0400
committerTony Luck <tony.luck@intel.com>2006-10-31 17:30:34 -0500
commit264b0f99308436deaee38bab99e586612d012fc1 (patch)
treea262e6f320c19d47e5842dfe8ccdd3823704072f /arch/ia64/kernel/perfmon_montecito.h
parent5ee7737379b1d7f0c977c0f1661fbaf01a8d4721 (diff)
[IA64] MCA recovery: Montecito support
The information in MCA records is filled in slightly differently on Montecito than on Madison/McKinley. Usually, the cache check and bus check target identifiers have the same address. On Montecito the cache check and bus check target identifiers can be different if a corrected error (ie SBE or unconsumed poison data) was encountered and then an uncorrected error (ie DBE) was consumed. In that case, the cache check target identifier is the physical address of the DBE (that caused the MCA to surface) while the bus check target identifier is the physical address of the SBE. This patch correctly finds the target identifier that triggered the MCA. If there are multiple valid cache target identifiers in the same error record then use the one with the lowest cache level. Signed-off-by: Russ Anderson (rja@sgi.com) Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/kernel/perfmon_montecito.h')
0 files changed, 0 insertions, 0 deletions