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authorRuss Anderson <rja@sgi.com>2007-10-31 12:10:38 -0400
committerTony Luck <tony.luck@intel.com>2007-11-06 18:40:31 -0500
commit1f3b6045f783ee394076ad6dba2d72ecaaecd243 (patch)
treec20820794846f45db619991d0ddc26832ccf75e8 /arch/ia64/kernel/mca.c
parentadb34022eb7a11126fecef6b5abb4741a17360c6 (diff)
[IA64] Disable/re-enable CPE interrupts on Altix
When the CPE handler encounters too many CPEs (such as a solid single bit memory error), it sets up a polling timer and disables the CPE interrupt (to avoid excessive overhead logging the stream of single bit errors). disable_irq_nosync() calls chip->disable() to provide a chipset specifiec interface for disabling the interrupt. This patch adds the Altix specific support to disable and re-enable the CPE interrupt. Signed-off-by: Russ Anderson (rja@sgi.com) Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/kernel/mca.c')
-rw-r--r--arch/ia64/kernel/mca.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c
index cc87025e8f54..10b48cd15a87 100644
--- a/arch/ia64/kernel/mca.c
+++ b/arch/ia64/kernel/mca.c
@@ -571,7 +571,7 @@ out:
571 * Outputs 571 * Outputs
572 * None 572 * None
573 */ 573 */
574static void __init 574void
575ia64_mca_register_cpev (int cpev) 575ia64_mca_register_cpev (int cpev)
576{ 576{
577 /* Register the CPE interrupt vector with SAL */ 577 /* Register the CPE interrupt vector with SAL */