diff options
author | Bryan O'Donoghue <bryan.odonoghue@linux.intel.com> | 2012-04-18 12:37:39 -0400 |
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committer | H. Peter Anvin <hpa@linux.intel.com> | 2012-04-18 12:44:31 -0400 |
commit | cbf2829b61c136edcba302a5e1b6b40e97d32c00 (patch) | |
tree | 69d3bd826c03793b35e0906915a441ede58d17a7 /arch/ia64/install.sh | |
parent | 089f9fba56faf33cc6dd2a6442b7ac92c58b8209 (diff) |
x86, apic: APIC code touches invalid MSR on P5 class machines
Current APIC code assumes MSR_IA32_APICBASE is present for all systems.
Pentium Classic P5 and friends didn't have this MSR. MSR_IA32_APICBASE
was introduced as an architectural MSR by Intel @ P6.
Code paths that can touch this MSR invalidly are when vendor == Intel &&
cpu-family == 5 and APIC bit is set in CPUID - or when you simply pass
lapic on the kernel command line, on a P5.
The below patch stops Linux incorrectly interfering with the
MSR_IA32_APICBASE for P5 class machines. Other code paths exist that
touch the MSR - however those paths are not currently reachable for a
conformant P5.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linux.intel.com>
Link: http://lkml.kernel.org/r/4F8EEDD3.1080404@linux.intel.com
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Cc: <stable@vger.kernel.org>
Diffstat (limited to 'arch/ia64/install.sh')
0 files changed, 0 insertions, 0 deletions