Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6

7 files changed, 84 insertions, 75 deletions

diff --git a/arch/i386/pci/common.c b/arch/i386/pci/common.c
index cdfcf971098b..53ca6e897984 100644
--- a/arch/i386/pci/common.c
+++ b/arch/i386/pci/common.c
@@ -20,7 +20,7 @@
 unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 |
                                 PCI_PROBE_MMCONF;
 
-int pci_bf_sort;
+static int pci_bf_sort;
 int pci_routeirq;
 int pcibios_last_bus = -1;
 unsigned long pirq_table_addr;
diff --git a/arch/i386/pci/early.c b/arch/i386/pci/early.c
index 713d6c866cae..42df4b6606df 100644
--- a/arch/i386/pci/early.c
+++ b/arch/i386/pci/early.c
@@ -45,6 +45,13 @@ void write_pci_config(u8 bus, u8 slot, u8 func, u8 offset,
         outl(val, 0xcfc);
 }
 
+void write_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset, u8 val)
+{
+        PDprintk("%x writing to %x: %x\n", slot, offset, val);
+        outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8);
+        outb(val, 0xcfc);
+}
+
 int early_pci_allowed(void)
 {
         return (pci_probe & (PCI_PROBE_CONF1|PCI_PROBE_NOEARLY)) ==
diff --git a/arch/i386/pci/fixup.c b/arch/i386/pci/fixup.c
index c1949ff38d61..8053b17ab647 100644
--- a/arch/i386/pci/fixup.c
+++ b/arch/i386/pci/fixup.c
@@ -74,52 +74,6 @@ static void __devinit  pci_fixup_ncr53c810(struct pci_dev *d)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810);
 
-static void __devinit pci_fixup_ide_bases(struct pci_dev *d)
-{
-        int i;
-
-        /*
-         * PCI IDE controllers use non-standard I/O port decoding, respect it.
-         */
-        if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
-                return;
-        DBG("PCI: IDE base address fixup for %s\n", pci_name(d));
-        for(i=0; i<4; i++) {
-                struct resource *r = &d->resource[i];
-                if ((r->start & ~0x80) == 0x374) {
-                        r->start |= 2;
-                        r->end = r->start;
-                }
-        }
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
-
-static void __devinit  pci_fixup_ide_trash(struct pci_dev *d)
-{
-        int i;
-
-        /*
-         * Runs the fixup only for the first IDE controller
-         * (Shai Fultheim - shai@ftcon.com)
-         */
-        static int called = 0;
-        if (called)
-                return;
-        called = 1;
-
-        /*
-         * There exist PCI IDE controllers which have utter garbage
-         * in first four base registers. Ignore that.
-         */
-        DBG("PCI: IDE base address trash cleared for %s\n", pci_name(d));
-        for(i=0; i<4; i++)
-                d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash);
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, pci_fixup_ide_trash);
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11, pci_fixup_ide_trash);
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_9, pci_fixup_ide_trash);
-
 static void __devinit  pci_fixup_latency(struct pci_dev *d)
 {
         /*
@@ -161,7 +115,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci
 #define VIA_8363_KL133_REVISION_ID 0x81
 #define VIA_8363_KM133_REVISION_ID 0x84
 
-static void __devinit pci_fixup_via_northbridge_bug(struct pci_dev *d)
+static void pci_fixup_via_northbridge_bug(struct pci_dev *d)
 {
         u8 v;
         u8 revision;
@@ -197,6 +151,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
 
 /*
  * For some reasons Intel decided that certain parts of their
@@ -227,7 +185,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_
  * issue another HALT within 80 ns of the initial HALT, the failure condition
  * is avoided.
  */
-static void __init pci_fixup_nforce2(struct pci_dev *dev)
+static void pci_fixup_nforce2(struct pci_dev *dev)
 {
         u32 val;
 
@@ -250,6 +208,7 @@ static void __init pci_fixup_nforce2(struct pci_dev *dev)
         }
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
 
 /* Max PCI Express root ports */
 #define MAX_PCIEROOT    6
@@ -465,7 +424,7 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
  * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device
  * configuration space.
  */
-static void __devinit pci_early_fixup_cyrix_5530(struct pci_dev *dev)
+static void pci_early_fixup_cyrix_5530(struct pci_dev *dev)
 {
         u8 r;
         /* clear 'F4 Video Configuration Trap' bit */
@@ -475,3 +434,5 @@ static void __devinit pci_early_fixup_cyrix_5530(struct pci_dev *dev)
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
                         pci_early_fixup_cyrix_5530);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
+                        pci_early_fixup_cyrix_5530);
diff --git a/arch/i386/pci/i386.c b/arch/i386/pci/i386.c
index 98580292f0d4..43005f044424 100644
--- a/arch/i386/pci/i386.c
+++ b/arch/i386/pci/i386.c
@@ -104,16 +104,24 @@ static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
         /* Depth-First Search on bus tree */
         list_for_each_entry(bus, bus_list, node) {
                 if ((dev = bus->self)) {
-                        for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
+                        for (idx = PCI_BRIDGE_RESOURCES;
+                            idx < PCI_NUM_RESOURCES; idx++) {
                                 r = &dev->resource[idx];
                                 if (!r->flags)
                                         continue;
                                 pr = pci_find_parent_resource(dev, r);
-                                if (!r->start || !pr || request_resource(pr, r) < 0) {
-                                        printk(KERN_ERR "PCI: Cannot allocate resource region %d of bridge %s\n", idx, pci_name(dev));
-                                        /* Something is wrong with the region.
-                                           Invalidate the resource to prevent child
-                                           resource allocations in this range. */
+                                if (!r->start || !pr ||
+                                    request_resource(pr, r) < 0) {
+                                        printk(KERN_ERR "PCI: Cannot allocate "
+                                                "resource region %d "
+                                                "of bridge %s\n",
+                                                idx, pci_name(dev));
+                                        /*
+                                         * Something is wrong with the region.
+                                         * Invalidate the resource to prevent
+                                         * child resource allocations in this
+                                         * range.
+                                         */
                                         r->flags = 0;
                                 }
                         }
@@ -131,7 +139,7 @@ static void __init pcibios_allocate_resources(int pass)
 
         for_each_pci_dev(dev) {
                 pci_read_config_word(dev, PCI_COMMAND, &command);
-                for(idx = 0; idx < 6; idx++) {
+                for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
                         r = &dev->resource[idx];
                         if (r->parent)          /* Already allocated */
                                 continue;
@@ -142,11 +150,15 @@ static void __init pcibios_allocate_resources(int pass)
                         else
                                 disabled = !(command & PCI_COMMAND_MEMORY);
                         if (pass == disabled) {
-                                DBG("PCI: Resource %08lx-%08lx (f=%lx, d=%d, p=%d)\n",
+                                DBG("PCI: Resource %08lx-%08lx "
+                                    "(f=%lx, d=%d, p=%d)\n",
                                     r->start, r->end, r->flags, disabled, pass);
                                 pr = pci_find_parent_resource(dev, r);
                                 if (!pr || request_resource(pr, r) < 0) {
-                                        printk(KERN_ERR "PCI: Cannot allocate resource region %d of device %s\n", idx, pci_name(dev));
+                                        printk(KERN_ERR "PCI: Cannot allocate "
+                                                "resource region %d "
+                                                "of device %s\n",
+                                                idx, pci_name(dev));
                                         /* We'll assign a new address later */
                                         r->end -= r->start;
                                         r->start = 0;
@@ -156,12 +168,16 @@ static void __init pcibios_allocate_resources(int pass)
                 if (!pass) {
                         r = &dev->resource[PCI_ROM_RESOURCE];
                         if (r->flags & IORESOURCE_ROM_ENABLE) {
-                                /* Turn the ROM off, leave the resource region, but keep it unregistered. */
+                                /* Turn the ROM off, leave the resource region,
+                                 * but keep it unregistered. */
                                 u32 reg;
-                                DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
+                                DBG("PCI: Switching off ROM of %s\n",
+                                        pci_name(dev));
                                 r->flags &= ~IORESOURCE_ROM_ENABLE;
-                                pci_read_config_dword(dev, dev->rom_base_reg, &reg);
-                                pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE);
+                                pci_read_config_dword(dev,
+                                                dev->rom_base_reg, &reg);
+                                pci_write_config_dword(dev, dev->rom_base_reg,
+                                                reg & ~PCI_ROM_ADDRESS_ENABLE);
                         }
                 }
         }
@@ -173,9 +189,11 @@ static int __init pcibios_assign_resources(void)
         struct resource *r, *pr;
 
         if (!(pci_probe & PCI_ASSIGN_ROMS)) {
-                /* Try to use BIOS settings for ROMs, otherwise let
-                   pci_assign_unassigned_resources() allocate the new
-                   addresses. */
+                /*
+                 * Try to use BIOS settings for ROMs, otherwise let
+                 * pci_assign_unassigned_resources() allocate the new
+                 * addresses.
+                 */
                 for_each_pci_dev(dev) {
                         r = &dev->resource[PCI_ROM_RESOURCE];
                         if (!r->flags || !r->start)
@@ -215,9 +233,9 @@ int pcibios_enable_resources(struct pci_dev *dev, int mask)
 
         pci_read_config_word(dev, PCI_COMMAND, &cmd);
         old_cmd = cmd;
-        for(idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
+        for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
                 /* Only set up the requested stuff */
-                if (!(mask & (1<<idx)))
+                if (!(mask & (1 << idx)))
                         continue;
 
                 r = &dev->resource[idx];
@@ -227,7 +245,9 @@ int pcibios_enable_resources(struct pci_dev *dev, int mask)
                                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
                         continue;
                 if (!r->start && r->end) {
-                        printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
+                        printk(KERN_ERR "PCI: Device %s not available "
+                                "because of resource collisions\n",
+                                pci_name(dev));
                         return -EINVAL;
                 }
                 if (r->flags & IORESOURCE_IO)
@@ -236,7 +256,8 @@ int pcibios_enable_resources(struct pci_dev *dev, int mask)
                         cmd |= PCI_COMMAND_MEMORY;
         }
         if (cmd != old_cmd) {
-                printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
+                printk("PCI: Enabling device %s (%04x -> %04x)\n",
+                        pci_name(dev), old_cmd, cmd);
                 pci_write_config_word(dev, PCI_COMMAND, cmd);
         }
         return 0;
@@ -258,7 +279,8 @@ void pcibios_set_master(struct pci_dev *dev)
                 lat = pcibios_max_latency;
         else
                 return;
-        printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
+        printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
+                pci_name(dev), lat);
         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 }
 
diff --git a/arch/i386/pci/irq.c b/arch/i386/pci/irq.c
index 69163998adeb..f2cb942f8281 100644
--- a/arch/i386/pci/irq.c
+++ b/arch/i386/pci/irq.c
@@ -543,6 +543,12 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route
                 case PCI_DEVICE_ID_INTEL_ICH8_2:
                 case PCI_DEVICE_ID_INTEL_ICH8_3:
                 case PCI_DEVICE_ID_INTEL_ICH8_4:
+                case PCI_DEVICE_ID_INTEL_ICH9_0:
+                case PCI_DEVICE_ID_INTEL_ICH9_1:
+                case PCI_DEVICE_ID_INTEL_ICH9_2:
+                case PCI_DEVICE_ID_INTEL_ICH9_3:
+                case PCI_DEVICE_ID_INTEL_ICH9_4:
+                case PCI_DEVICE_ID_INTEL_ICH9_5:
                         r->name = "PIIX/ICH";
                         r->get = pirq_piix_get;
                         r->set = pirq_piix_set;
@@ -758,7 +764,7 @@ static void __init pirq_find_router(struct irq_router *r)
         DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for %04x:%04x\n",
             rt->rtr_vendor, rt->rtr_device);
 
-        pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn);
+        pirq_router_dev = pci_get_bus_and_slot(rt->rtr_bus, rt->rtr_devfn);
         if (!pirq_router_dev) {
                 DBG(KERN_DEBUG "PCI: Interrupt router not found at "
                         "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
@@ -778,6 +784,8 @@ static void __init pirq_find_router(struct irq_router *r)
                 pirq_router_dev->vendor,
                 pirq_router_dev->device,
                 pci_name(pirq_router_dev));
+
+        /* The device remains referenced for the kernel lifetime */
 }
 
 static struct irq_info *pirq_get_info(struct pci_dev *dev)
diff --git a/arch/i386/pci/mmconfig.c b/arch/i386/pci/mmconfig.c
index c6b6d9bbc453..e2616a266e13 100644
--- a/arch/i386/pci/mmconfig.c
+++ b/arch/i386/pci/mmconfig.c
@@ -26,6 +26,7 @@
 
 /* The base address of the last MMCONFIG device accessed */
 static u32 mmcfg_last_accessed_device;
+static int mmcfg_last_accessed_cpu;
 
 static DECLARE_BITMAP(fallback_slots, MAX_CHECK_BUS*32);
 
@@ -73,8 +74,11 @@ static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
 static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
 {
         u32 dev_base = base | (bus << 20) | (devfn << 12);
-        if (dev_base != mmcfg_last_accessed_device) {
+        int cpu = smp_processor_id();
+        if (dev_base != mmcfg_last_accessed_device ||
+            cpu != mmcfg_last_accessed_cpu) {
                 mmcfg_last_accessed_device = dev_base;
+                mmcfg_last_accessed_cpu = cpu;
                 set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
         }
 }
diff --git a/arch/i386/pci/pcbios.c b/arch/i386/pci/pcbios.c
index ed1512a175ab..5f5193401bea 100644
--- a/arch/i386/pci/pcbios.c
+++ b/arch/i386/pci/pcbios.c
@@ -5,6 +5,7 @@
 #include <linux/pci.h>
 #include <linux/init.h>
 #include <linux/module.h>
+#include <linux/uaccess.h>
 #include "pci.h"
 #include "pci-functions.h"
 
@@ -314,6 +315,10 @@ static struct pci_raw_ops * __devinit pci_find_bios(void)
         for (check = (union bios32 *) __va(0xe0000);
              check <= (union bios32 *) __va(0xffff0);
              ++check) {
+                long sig;
+                if (probe_kernel_address(&check->fields.signature, sig))
+                        continue;
+
                 if (check->fields.signature != BIOS32_SIGNATURE)
                         continue;
                 length = check->fields.length * 16;
@@ -331,11 +336,13 @@ static struct pci_raw_ops * __devinit pci_find_bios(void)
                 }
                 DBG("PCI: BIOS32 Service Directory structure at 0x%p\n", check);
                 if (check->fields.entry >= 0x100000) {
-                        printk("PCI: BIOS32 entry (0x%p) in high memory, cannot use.\n", check);
+                        printk("PCI: BIOS32 entry (0x%p) in high memory, "
+                                        "cannot use.\n", check);
                         return NULL;
                 } else {
                         unsigned long bios32_entry = check->fields.entry;
-                        DBG("PCI: BIOS32 Service Directory entry at 0x%lx\n", bios32_entry);
+                        DBG("PCI: BIOS32 Service Directory entry at 0x%lx\n",
+                                        bios32_entry);
                         bios32_indirect.address = bios32_entry + PAGE_OFFSET;
                         if (check_pcibios())
                                 return &pci_bios_access;