[PATCH] x86_64: Force correct address space size for MTRR on some 64bit Intel Xeons

They report 40bit, but only have 36bits of physical address space.
This caused problems with setting up the correct masks for MTRR.

CPUID workaround for steppings 0F33h(supporting x86) and 0F34h(supporting x86
and EM64T). Detail info can be found at:
http://download.intel.com/design/Xeon/specupdt/30240216.pdf
http://download.intel.com/design/Pentium4/specupdt/30235221.pdf

Signed-off-by: Shaohua Li<shaohua.li@intel.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 8 insertions, 0 deletions

diff --git a/arch/i386/kernel/cpu/mtrr/main.c b/arch/i386/kernel/cpu/mtrr/main.c
index dd4ebd6af7e4..1e9db198c440 100644
--- a/arch/i386/kernel/cpu/mtrr/main.c
+++ b/arch/i386/kernel/cpu/mtrr/main.c
@@ -626,6 +626,14 @@ void __init mtrr_bp_init(void)
                 if (cpuid_eax(0x80000000) >= 0x80000008) {
                         u32 phys_addr;
                         phys_addr = cpuid_eax(0x80000008) & 0xff;
+                        /* CPUID workaround for Intel 0F33/0F34 CPU */
+                        if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
+                            boot_cpu_data.x86 == 0xF &&
+                            boot_cpu_data.x86_model == 0x3 &&
+                            (boot_cpu_data.x86_mask == 0x3 ||
+                             boot_cpu_data.x86_mask == 0x4))
+                                phys_addr = 36;
+
                         size_or_mask = ~((1 << (phys_addr - PAGE_SHIFT)) - 1);
                         size_and_mask = ~size_or_mask & 0xfff00000;
                 } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&