Merge branch 'for-linus' of git://www.jni.nu/cris

* 'for-linus' of git://www.jni.nu/cris: (51 commits)
  CRIS: Fix alignment problem for older ld
  CRIS: Always dump registers for segfaulting process.
  CRIS: Add config for pausing a seg-faulting process
  CRIS: Don't take faults while in_atomic
  CRIS: Fixup lookup for delay slot faults
  CRIS: Discard exit.text and .data at runtime
  CRIS: Add cache aligned and read mostly data sections
  CRIS: Return something from profile write
  CRIS: Add ARTPEC-3 and timestamps for sync-serial
  CRIS: Better ARTPEC-3 support for gpio
  CRIS: Add include guard
  CRIS: Better handling of pinmux settings
  CRIS: New DMA defines for ARTPEC-3
  CRIS: __do_strncpy_from_user: Don't read the byte beyond the nil
  CRIS: Pagetable for ARTPEC-3
  CRIS: Machine dependent memmap.h
  CRIS: Check if pointer is set before using it
  CRIS: Machine dependent dma.h
  CRIS: Define __read_mostly for CRISv32
  CRIS: Discard .note.gnu.build-id section
  ...

13 files changed, 292 insertions, 136 deletions

diff --git a/arch/cris/include/arch-v32/arch/cache.h b/arch/cris/include/arch-v32/arch/cache.h
index dfc73050e6b4..1de779f4f240 100644
--- a/arch/cris/include/arch-v32/arch/cache.h
+++ b/arch/cris/include/arch-v32/arch/cache.h
@@ -7,6 +7,8 @@
 #define L1_CACHE_BYTES 32
 #define L1_CACHE_SHIFT 5
 
+#define __read_mostly __attribute__((__section__(".data.read_mostly")))
+
 void flush_dma_list(dma_descr_data *descr);
 void flush_dma_descr(dma_descr_data *descr, int flush_buf);
 
diff --git a/arch/cris/include/arch-v32/arch/dma.h b/arch/cris/include/arch-v32/arch/dma.h
index 3674081389fd..61906153a9af 100644
--- a/arch/cris/include/arch-v32/arch/dma.h
+++ b/arch/cris/include/arch-v32/arch/dma.h
@@ -1,79 +1 @@
-#ifndef _ASM_ARCH_CRIS_DMA_H
-#define _ASM_ARCH_CRIS_DMA_H
-
-/* Defines for using and allocating dma channels. */
-
-#define MAX_DMA_CHANNELS        10
-
-#define NETWORK_ETH0_TX_DMA_NBR 0       /* Ethernet 0 out. */
-#define NETWORK_ETH0 RX_DMA_NBR 1       /* Ethernet 0 in. */
-
-#define IO_PROC_DMA0_TX_DMA_NBR 2       /* IO processor DMA0 out. */
-#define IO_PROC_DMA0_RX_DMA_NBR 3       /* IO processor DMA0 in. */
-
-#define ATA_TX_DMA_NBR 2                /* ATA interface out. */
-#define ATA_RX_DMA_NBR 3                /* ATA interface in. */
-
-#define ASYNC_SER2_TX_DMA_NBR 2         /* Asynchronous serial port 2 out. */
-#define ASYNC_SER2_RX_DMA_NBR 3         /* Asynchronous serial port 2 in. */
-
-#define IO_PROC_DMA1_TX_DMA_NBR 4       /* IO processor DMA1 out. */
-#define IO_PROC_DMA1_RX_DMA_NBR 5       /* IO processor DMA1 in. */
-
-#define ASYNC_SER1_TX_DMA_NBR 4         /* Asynchronous serial port 1 out. */
-#define ASYNC_SER1_RX_DMA_NBR 5         /* Asynchronous serial port 1 in. */
-
-#define SYNC_SER0_TX_DMA_NBR 4          /* Synchronous serial port 0 out. */
-#define SYNC_SER0_RX_DMA_NBR 5          /* Synchronous serial port 0 in. */
-
-#define EXTDMA0_TX_DMA_NBR 6            /* External DMA 0 out. */
-#define EXTDMA1_RX_DMA_NBR 7            /* External DMA 1 in. */
-
-#define ASYNC_SER0_TX_DMA_NBR 6         /* Asynchronous serial port 0 out. */
-#define ASYNC_SER0_RX_DMA_NBR 7         /* Asynchronous serial port 0 in. */
-
-#define SYNC_SER1_TX_DMA_NBR 6          /* Synchronous serial port 1 out. */
-#define SYNC_SER1_RX_DMA_NBR 7          /* Synchronous serial port 1 in. */
-
-#define NETWORK_ETH1_TX_DMA_NBR 6       /* Ethernet 1 out. */
-#define NETWORK_ETH1_RX_DMA_NBR 7       /* Ethernet 1 in. */
-
-#define EXTDMA2_TX_DMA_NBR 8            /* External DMA 2 out. */
-#define EXTDMA3_RX_DMA_NBR 9            /* External DMA 3 in. */
-
-#define STRCOP_TX_DMA_NBR 8             /* Stream co-processor out. */
-#define STRCOP_RX_DMA_NBR 9             /* Stream co-processor in. */
-
-#define ASYNC_SER3_TX_DMA_NBR 8         /* Asynchronous serial port 3 out. */
-#define ASYNC_SER3_RX_DMA_NBR 9         /* Asynchronous serial port 3 in. */
-
-enum dma_owner
-{
-  dma_eth0,
-  dma_eth1,
-  dma_iop0,
-  dma_iop1,
-  dma_ser0,
-  dma_ser1,
-  dma_ser2,
-  dma_ser3,
-  dma_sser0,
-  dma_sser1,
-  dma_ata,
-  dma_strp,
-  dma_ext0,
-  dma_ext1,
-  dma_ext2,
-  dma_ext3
-};
-
-int crisv32_request_dma(unsigned int dmanr, const char * device_id,
-                        unsigned options, unsigned bandwidth, enum dma_owner owner);
-void crisv32_free_dma(unsigned int dmanr);
-
-/* Masks used by crisv32_request_dma options: */
-#define DMA_VERBOSE_ON_ERROR 1
-#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
-#define DMA_INT_MEM 4
-
-#endif /* _ASM_ARCH_CRIS_DMA_H */
+#include "mach/dma.h"
diff --git a/arch/cris/include/arch-v32/arch/io.h b/arch/cris/include/arch-v32/arch/io.h
index 72024452cea9..adc5484351bf 100644
--- a/arch/cris/include/arch-v32/arch/io.h
+++ b/arch/cris/include/arch-v32/arch/io.h
@@ -46,10 +46,12 @@ static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val)
         unsigned long flags;
         spin_lock_irqsave(&iopin->port->lock, flags);
 
-        if (val)
-                *iopin->port->data |= iopin->bit;
-        else
-                *iopin->port->data &= ~iopin->bit;
+        if (iopin->port->data) {
+                if (val)
+                        *iopin->port->data |= iopin->bit;
+                else
+                        *iopin->port->data &= ~iopin->bit;
+        }
 
         spin_unlock_irqrestore(&iopin->port->lock, flags);
 }
@@ -60,10 +62,12 @@ static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin,
         unsigned long flags;
         spin_lock_irqsave(&iopin->port->lock, flags);
 
-        if (dir == crisv32_io_dir_in)
-                *iopin->port->oe &= ~iopin->bit;
-        else
-                *iopin->port->oe |= iopin->bit;
+        if (iopin->port->oe) {
+                if (dir == crisv32_io_dir_in)
+                        *iopin->port->oe &= ~iopin->bit;
+                else
+                        *iopin->port->oe |= iopin->bit;
+        }
 
         spin_unlock_irqrestore(&iopin->port->lock, flags);
 }
diff --git a/arch/cris/include/arch-v32/arch/memmap.h b/arch/cris/include/arch-v32/arch/memmap.h
index d29df5644d3e..81985c0a6789 100644
--- a/arch/cris/include/arch-v32/arch/memmap.h
+++ b/arch/cris/include/arch-v32/arch/memmap.h
@@ -1,24 +1 @@
-#ifndef _ASM_ARCH_MEMMAP_H
-#define _ASM_ARCH_MEMMAP_H
-
-#define MEM_CSE0_START (0x00000000)
-#define MEM_CSE0_SIZE (0x04000000)
-#define MEM_CSE1_START (0x04000000)
-#define MEM_CSE1_SIZE (0x04000000)
-#define MEM_CSR0_START (0x08000000)
-#define MEM_CSR1_START (0x0c000000)
-#define MEM_CSP0_START (0x10000000)
-#define MEM_CSP1_START (0x14000000)
-#define MEM_CSP2_START (0x18000000)
-#define MEM_CSP3_START (0x1c000000)
-#define MEM_CSP4_START (0x20000000)
-#define MEM_CSP5_START (0x24000000)
-#define MEM_CSP6_START (0x28000000)
-#define MEM_CSP7_START (0x2c000000)
-#define MEM_INTMEM_START (0x38000000)
-#define MEM_INTMEM_SIZE (0x00020000)
-#define MEM_DRAM_START (0x40000000)
-
-#define MEM_NON_CACHEABLE (0x80000000)
-
-#endif
+#include <mach/memmap.h>
diff --git a/arch/cris/include/arch-v32/arch/pgtable.h b/arch/cris/include/arch-v32/arch/pgtable.h
index 08cb7ff7e4e7..c1051a8da33d 100644
--- a/arch/cris/include/arch-v32/arch/pgtable.h
+++ b/arch/cris/include/arch-v32/arch/pgtable.h
@@ -2,8 +2,16 @@
 #define _ASM_CRIS_ARCH_PGTABLE_H
 
 /* Define the kernels virtual memory area. */
+
+/* See head.S for differences between ARTPEC-3 and ETRAX FS. */
+#ifdef CONFIG_CRIS_MACH_ARTPEC3
+#define VMALLOC_START          KSEG_E
+#define VMALLOC_END            KSEG_F
+#else
 #define VMALLOC_START           KSEG_D
 #define VMALLOC_END             KSEG_E
+#endif
+
 #define VMALLOC_VMADDR(x)       ((unsigned long)(x))
 
 #endif /* _ASM_CRIS_ARCH_PGTABLE_H */
diff --git a/arch/cris/include/arch-v32/arch/uaccess.h b/arch/cris/include/arch-v32/arch/uaccess.h
index 6b207f1b6622..3196019706cb 100644
--- a/arch/cris/include/arch-v32/arch/uaccess.h
+++ b/arch/cris/include/arch-v32/arch/uaccess.h
@@ -122,14 +122,14 @@ __do_strncpy_from_user(char *dst, const char *src, long count)
         __asm__ __volatile__ (
                 "       move.d %3,%0\n"
                 "5:     move.b [%2+],$acr\n"
-                "1:     beq 2f\n"
+                "1:     beq 6f\n"
                 "       move.b $acr,[%1+]\n"
 
                 "       subq 1,%0\n"
                 "2:     bne 1b\n"
                 "       move.b [%2+],$acr\n"
 
-                "       sub.d %3,%0\n"
+                "6:     sub.d %3,%0\n"
                 "       neg.d %0,%0\n"
                 "3:\n"
                 "       .section .fixup,\"ax\"\n"
@@ -140,8 +140,7 @@ __do_strncpy_from_user(char *dst, const char *src, long count)
                 /* The address for a fault at the first move is trivial.
                    The address for a fault at the second move is that of
                    the preceding branch insn, since the move insn is in
-                   its delay-slot.  That address is also a branch
-                   target.  Just so you don't get confused...  */
+                   its delay-slot.  Just so you don't get confused...  */
                 "       .previous\n"
                 "       .section __ex_table,\"a\"\n"
                 "       .dword 5b,4b\n"
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/dma.h b/arch/cris/include/arch-v32/mach-a3/mach/dma.h
index 9e8eb13b601d..f01dca1ad108 100644
--- a/arch/cris/include/arch-v32/mach-a3/mach/dma.h
+++ b/arch/cris/include/arch-v32/mach-a3/mach/dma.h
@@ -5,6 +5,33 @@
 
 #define MAX_DMA_CHANNELS        12 /* 8 and 10 not used. */
 
+#define NETWORK_ETH_TX_DMA_NBR 0        /* Ethernet 0 out. */
+#define NETWORK_ETH_RX_DMA_NBR 1        /* Ethernet 0 in. */
+
+#define IO_PROC_DMA_TX_DMA_NBR 4        /* IO processor DMA0 out. */
+#define IO_PROC_DMA_RX_DMA_NBR 5        /* IO processor DMA0 in. */
+
+#define ASYNC_SER3_TX_DMA_NBR 2         /* Asynchronous serial port 3 out. */
+#define ASYNC_SER3_RX_DMA_NBR 3         /* Asynchronous serial port 3 in. */
+
+#define ASYNC_SER2_TX_DMA_NBR 6         /* Asynchronous serial port 2 out. */
+#define ASYNC_SER2_RX_DMA_NBR 7         /* Asynchronous serial port 2 in. */
+
+#define ASYNC_SER1_TX_DMA_NBR 4         /* Asynchronous serial port 1 out. */
+#define ASYNC_SER1_RX_DMA_NBR 5         /* Asynchronous serial port 1 in. */
+
+#define SYNC_SER_TX_DMA_NBR 6           /* Synchronous serial port 0 out. */
+#define SYNC_SER_RX_DMA_NBR 7           /* Synchronous serial port 0 in. */
+
+#define ASYNC_SER0_TX_DMA_NBR 0         /* Asynchronous serial port 0 out. */
+#define ASYNC_SER0_RX_DMA_NBR 1         /* Asynchronous serial port 0 in. */
+
+#define STRCOP_TX_DMA_NBR 2             /* Stream co-processor out. */
+#define STRCOP_RX_DMA_NBR 3             /* Stream co-processor in. */
+
+#define dma_eth0 dma_eth
+#define dma_eth1 dma_eth
+
 enum dma_owner {
         dma_eth,
         dma_ser0,
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/startup.inc b/arch/cris/include/arch-v32/mach-a3/mach/startup.inc
index 2f23e5e16f4a..2d52bcc96ed5 100644
--- a/arch/cris/include/arch-v32/mach-a3/mach/startup.inc
+++ b/arch/cris/include/arch-v32/mach-a3/mach/startup.inc
@@ -1,9 +1,19 @@
+#ifndef STARTUP_INC_INCLUDED
+#define STARTUP_INC_INCLUDED
+
 #include <hwregs/asm/reg_map_asm.h>
 #include <hwregs/asm/gio_defs_asm.h>
 #include <hwregs/asm/pio_defs_asm.h>
 #include <hwregs/asm/clkgen_defs_asm.h>
 #include <hwregs/asm/pinmux_defs_asm.h>
 
+        .macro GIO_SET_P BITS, OUTREG
+        bmi     1f              ; btstq: bit -> N flag
+        nop
+        or.d    \BITS, \OUTREG
+1:
+        .endm
+
         .macro GIO_INIT
         move.d  CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
         move.d  REG_ADDR(gio, regi_gio, rw_pa_dout), $r1
@@ -32,10 +42,23 @@
         move.d  0xFFFFFFFF, $r0
         move.d  REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1
         move.d  $r0, [$r1]
-        move.d  REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1
-        move.d  $r0, [$r1]
         move.d  REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1
         move.d  $r0, [$r1]
+
+        ;; If eth_mdio, eth, geth bits are set in hwprot, don't
+        ;; set them to gpio, as this means they have been configured
+        ;; earlier and shouldn't be changed.
+        move.d  0xFC000000, $r2 ; pins 25..0 are eth_mdio, eth, geth
+        move.d  REG_ADDR(pinmux, regi_pinmux, rw_hwprot), $r1
+        move.d  [$r1], $r0
+        btstq   REG_BIT(pinmux, rw_hwprot, eth), $r0
+        GIO_SET_P 0x00FFFF00, $r2               ;; pins 8..23 are eth
+        btstq   REG_BIT(pinmux, rw_hwprot, eth_mdio), $r0
+        GIO_SET_P 0x03000000, $r2               ;; pins 24..25 are eth_mdio
+        btstq   REG_BIT(pinmux, rw_hwprot, geth), $r0
+        GIO_SET_P 0x000000FF, $r2               ;; pins 0..7 are geth
+        move.d  REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1
+        move.d  $r2, [$r1]
         .endm
 
         .macro START_CLOCKS
@@ -58,3 +81,4 @@
         move.d CONFIG_ETRAX_PIO_CE2_CFG, $r1
         move.d $r1, [$r0]
         .endm
+#endif
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/dma.h b/arch/cris/include/arch-v32/mach-fs/mach/dma.h
new file mode 100644
index 000000000000..a8c59292586a
--- /dev/null
+++ b/arch/cris/include/arch-v32/mach-fs/mach/dma.h
@@ -0,0 +1,79 @@
+#ifndef _ASM_ARCH_CRIS_DMA_H
+#define _ASM_ARCH_CRIS_DMA_H
+
+/* Defines for using and allocating dma channels. */
+
+#define MAX_DMA_CHANNELS        10
+
+#define NETWORK_ETH0_TX_DMA_NBR 0       /* Ethernet 0 out. */
+#define NETWORK_ETH0 RX_DMA_NBR 1       /* Ethernet 0 in. */
+
+#define IO_PROC_DMA0_TX_DMA_NBR 2       /* IO processor DMA0 out. */
+#define IO_PROC_DMA0_RX_DMA_NBR 3       /* IO processor DMA0 in. */
+
+#define ATA_TX_DMA_NBR 2                /* ATA interface out. */
+#define ATA_RX_DMA_NBR 3                /* ATA interface in. */
+
+#define ASYNC_SER2_TX_DMA_NBR 2         /* Asynchronous serial port 2 out. */
+#define ASYNC_SER2_RX_DMA_NBR 3         /* Asynchronous serial port 2 in. */
+
+#define IO_PROC_DMA1_TX_DMA_NBR 4       /* IO processor DMA1 out. */
+#define IO_PROC_DMA1_RX_DMA_NBR 5       /* IO processor DMA1 in. */
+
+#define ASYNC_SER1_TX_DMA_NBR 4         /* Asynchronous serial port 1 out. */
+#define ASYNC_SER1_RX_DMA_NBR 5         /* Asynchronous serial port 1 in. */
+
+#define SYNC_SER0_TX_DMA_NBR 4          /* Synchronous serial port 0 out. */
+#define SYNC_SER0_RX_DMA_NBR 5          /* Synchronous serial port 0 in. */
+
+#define EXTDMA0_TX_DMA_NBR 6            /* External DMA 0 out. */
+#define EXTDMA1_RX_DMA_NBR 7            /* External DMA 1 in. */
+
+#define ASYNC_SER0_TX_DMA_NBR 6         /* Asynchronous serial port 0 out. */
+#define ASYNC_SER0_RX_DMA_NBR 7         /* Asynchronous serial port 0 in. */
+
+#define SYNC_SER1_TX_DMA_NBR 6          /* Synchronous serial port 1 out. */
+#define SYNC_SER1_RX_DMA_NBR 7          /* Synchronous serial port 1 in. */
+
+#define NETWORK_ETH1_TX_DMA_NBR 6       /* Ethernet 1 out. */
+#define NETWORK_ETH1_RX_DMA_NBR 7       /* Ethernet 1 in. */
+
+#define EXTDMA2_TX_DMA_NBR 8            /* External DMA 2 out. */
+#define EXTDMA3_RX_DMA_NBR 9            /* External DMA 3 in. */
+
+#define STRCOP_TX_DMA_NBR 8             /* Stream co-processor out. */
+#define STRCOP_RX_DMA_NBR 9             /* Stream co-processor in. */
+
+#define ASYNC_SER3_TX_DMA_NBR 8         /* Asynchronous serial port 3 out. */
+#define ASYNC_SER3_RX_DMA_NBR 9         /* Asynchronous serial port 3 in. */
+
+enum dma_owner {
+  dma_eth0,
+  dma_eth1,
+  dma_iop0,
+  dma_iop1,
+  dma_ser0,
+  dma_ser1,
+  dma_ser2,
+  dma_ser3,
+  dma_sser0,
+  dma_sser1,
+  dma_ata,
+  dma_strp,
+  dma_ext0,
+  dma_ext1,
+  dma_ext2,
+  dma_ext3
+};
+
+int crisv32_request_dma(unsigned int dmanr, const char *device_id,
+                        unsigned options, unsigned bandwidth,
+                        enum dma_owner owner);
+void crisv32_free_dma(unsigned int dmanr);
+
+/* Masks used by crisv32_request_dma options: */
+#define DMA_VERBOSE_ON_ERROR 1
+#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
+#define DMA_INT_MEM 4
+
+#endif /* _ASM_ARCH_CRIS_DMA_H */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/memmap.h b/arch/cris/include/arch-v32/mach-fs/mach/memmap.h
new file mode 100644
index 000000000000..d29df5644d3e
--- /dev/null
+++ b/arch/cris/include/arch-v32/mach-fs/mach/memmap.h
@@ -0,0 +1,24 @@
+#ifndef _ASM_ARCH_MEMMAP_H
+#define _ASM_ARCH_MEMMAP_H
+
+#define MEM_CSE0_START (0x00000000)
+#define MEM_CSE0_SIZE (0x04000000)
+#define MEM_CSE1_START (0x04000000)
+#define MEM_CSE1_SIZE (0x04000000)
+#define MEM_CSR0_START (0x08000000)
+#define MEM_CSR1_START (0x0c000000)
+#define MEM_CSP0_START (0x10000000)
+#define MEM_CSP1_START (0x14000000)
+#define MEM_CSP2_START (0x18000000)
+#define MEM_CSP3_START (0x1c000000)
+#define MEM_CSP4_START (0x20000000)
+#define MEM_CSP5_START (0x24000000)
+#define MEM_CSP6_START (0x28000000)
+#define MEM_CSP7_START (0x2c000000)
+#define MEM_INTMEM_START (0x38000000)
+#define MEM_INTMEM_SIZE (0x00020000)
+#define MEM_DRAM_START (0x40000000)
+
+#define MEM_NON_CACHEABLE (0x80000000)
+
+#endif
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/startup.inc b/arch/cris/include/arch-v32/mach-fs/mach/startup.inc
index 4a10ccbd6cc1..dd1abbdcbc7a 100644
--- a/arch/cris/include/arch-v32/mach-fs/mach/startup.inc
+++ b/arch/cris/include/arch-v32/mach-fs/mach/startup.inc
@@ -1,3 +1,6 @@
+#ifndef STARTUP_INC_INCLUDED
+#define STARTUP_INC_INCLUDED
+
 #include <hwregs/asm/reg_map_asm.h>
 #include <hwregs/asm/bif_core_defs_asm.h>
 #include <hwregs/asm/gio_defs_asm.h>
@@ -75,3 +78,5 @@
         move.d $r10, [$r11]
 #endif
         .endm
+
+#endif
diff --git a/arch/cris/include/asm/etraxgpio.h b/arch/cris/include/asm/etraxgpio.h
index 38f1c8e1770c..d474818a537e 100644
--- a/arch/cris/include/asm/etraxgpio.h
+++ b/arch/cris/include/asm/etraxgpio.h
@@ -21,31 +21,35 @@
  * /dev/leds   minor 2, Access to leds depending on kernelconfig
  *
  * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3):
- * /dev/gpioa  minor 0,  8 bit GPIO, each bit can change direction
- * /dev/gpiob  minor 1, 18 bit GPIO, each bit can change direction
- * /dev/gpioc  minor 3, 18 bit GPIO, each bit can change direction
- * /dev/gpiod  minor 4, 18 bit GPIO, each bit can change direction
+ * /dev/gpioa  minor 0, 32 bit GPIO, each bit can change direction
+ * /dev/gpiob  minor 1, 32 bit GPIO, each bit can change direction
+ * /dev/gpioc  minor 3, 16 bit GPIO, each bit can change direction
+ * /dev/gpiod  minor 4, 32 bit GPIO, input only
  * /dev/leds   minor 2, Access to leds depending on kernelconfig
  * /dev/pwm0   minor 16, PWM channel 0 on PA30
  * /dev/pwm1   minor 17, PWM channel 1 on PA31
  * /dev/pwm2   minor 18, PWM channel 2 on PB26
+ * /dev/ppwm   minor 19, PPWM channel
  *
  */
 #ifndef _ASM_ETRAXGPIO_H
 #define _ASM_ETRAXGPIO_H
 
+#define GPIO_MINOR_FIRST 0
+
+#define ETRAXGPIO_IOCTYPE 43
+
 /* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */
 #ifdef CONFIG_ETRAX_ARCH_V10
-#define ETRAXGPIO_IOCTYPE 43
 #define GPIO_MINOR_A 0
 #define GPIO_MINOR_B 1
 #define GPIO_MINOR_LEDS 2
 #define GPIO_MINOR_G 3
 #define GPIO_MINOR_LAST 3
+#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
 #endif
 
 #ifdef CONFIG_ETRAXFS
-#define ETRAXGPIO_IOCTYPE 43
 #define GPIO_MINOR_A 0
 #define GPIO_MINOR_B 1
 #define GPIO_MINOR_LEDS 2
@@ -58,10 +62,10 @@
 #else
 #define GPIO_MINOR_LAST 5
 #endif
+#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
 #endif
 
 #ifdef CONFIG_CRIS_MACH_ARTPEC3
-#define ETRAXGPIO_IOCTYPE 43
 #define GPIO_MINOR_A 0
 #define GPIO_MINOR_B 1
 #define GPIO_MINOR_LEDS 2
@@ -73,12 +77,17 @@
 #else
 #define GPIO_MINOR_LAST 4
 #endif
-#define GPIO_MINOR_PWM0 16
-#define GPIO_MINOR_PWM1 17
-#define GPIO_MINOR_PWM2 18
-#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PWM2
+#define GPIO_MINOR_FIRST_PWM 16
+#define GPIO_MINOR_PWM0 (GPIO_MINOR_FIRST_PWM+0)
+#define GPIO_MINOR_PWM1 (GPIO_MINOR_FIRST_PWM+1)
+#define GPIO_MINOR_PWM2 (GPIO_MINOR_FIRST_PWM+2)
+#define GPIO_MINOR_PPWM (GPIO_MINOR_FIRST_PWM+3)
+#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PPWM
+#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST_PWM
 #endif
 
+
+
 /* supported ioctl _IOC_NR's */
 
 #define IO_READBITS  0x1  /* read and return current port bits (obsolete) */
@@ -125,12 +134,10 @@
  */
 #define IO_READ_INBITS   0x10 /* *arg is result of reading the input pins */
 #define IO_READ_OUTBITS  0x11 /* *arg is result of reading the output shadow */
-#define IO_SETGET_INPUT  0x12 /* bits set in *arg is set to input,
-                               * *arg updated with current input pins.
-                               */
-#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output,
-                               * *arg updated with current output pins.
-                               */
+#define IO_SETGET_INPUT  0x12 /* bits set in *arg is set to input, */
+                              /* *arg updated with current input pins. */
+#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */
+                              /* *arg updated with current output pins. */
 
 /* The following ioctl's are applicable to the PWM channels only */
 
@@ -140,7 +147,8 @@ enum io_pwm_mode {
         PWM_OFF = 0,            /* disabled, deallocated */
         PWM_STANDARD = 1,       /* 390 kHz, duty cycle 0..255/256 */
         PWM_FAST = 2,           /* variable freq, w/ 10ns active pulse len */
-        PWM_VARFREQ = 3         /* individually configurable high/low periods */
+        PWM_VARFREQ = 3,        /* individually configurable high/low periods */
+        PWM_SOFT = 4            /* software generated */
 };
 
 struct io_pwm_set_mode {
@@ -176,4 +184,56 @@ struct io_pwm_set_duty {
         int duty;               /* 0..255 */
 };
 
+/* Returns information about the latest PWM pulse.
+ * lo: Length of the latest low period, in units of 10ns.
+ * hi: Length of the latest high period, in units of 10ns.
+ * cnt: Time since last detected edge, in units of 10ns.
+ *
+ * The input source to PWM is decied by IO_PWM_SET_INPUT_SRC.
+ *
+ * NOTE: All PWM devices is connected to the same input source.
+ */
+#define IO_PWM_GET_PERIOD   0x23
+
+struct io_pwm_get_period {
+        unsigned int lo;
+        unsigned int hi;
+        unsigned int cnt;
+};
+
+/* Sets the input source for the PWM input. For the src value see the
+ * register description for gio:rw_pwm_in_cfg.
+ *
+ * NOTE: All PWM devices is connected to the same input source.
+ */
+#define IO_PWM_SET_INPUT_SRC   0x24
+struct io_pwm_set_input_src {
+        unsigned int src;       /* 0..7 */
+};
+
+/* Sets the duty cycles in steps of 1/256, 0 = 0%, 255 = 100% duty cycle */
+#define IO_PPWM_SET_DUTY     0x25
+
+struct io_ppwm_set_duty {
+        int duty;               /* 0..255 */
+};
+
+/* Configuraton struct for the IO_PWMCLK_SET_CONFIG ioctl to configure
+ * PWM capable gpio pins:
+ */
+#define IO_PWMCLK_SETGET_CONFIG 0x26
+struct gpio_pwmclk_conf {
+  unsigned int gpiopin; /* The pin number based on the opened device */
+  unsigned int baseclk; /* The base clock to use, or sw will select one close*/
+  unsigned int low;     /* The number of low periods of the baseclk */
+  unsigned int high;    /* The number of high periods of the baseclk */
+};
+
+/* Examples:
+ * To get a symmetric 12 MHz clock without knowing anything about the hardware:
+ * baseclk = 12000000, low = 0, high = 0
+ * To just get info of current setting:
+ * baseclk = 0, low = 0, high = 0, the values will be updated by driver.
+ */
+
 #endif
diff --git a/arch/cris/include/asm/sync_serial.h b/arch/cris/include/asm/sync_serial.h
index d87c24df2b38..7f827fea30e7 100644
--- a/arch/cris/include/asm/sync_serial.h
+++ b/arch/cris/include/asm/sync_serial.h
@@ -19,6 +19,7 @@
 #define SSP_OPOLARITY  _IOR('S', 4, unsigned int)
 #define SSP_SPI        _IOR('S', 5, unsigned int)
 #define SSP_INBUFCHUNK _IOR('S', 6, unsigned int)
+#define SSP_INPUT      _IOR('S', 7, unsigned int)
 
 /* Values for SSP_SPEED */
 #define SSP150        0
@@ -37,6 +38,7 @@
 #define SSP921600    13
 #define SSP3125000   14
 #define CODEC        15
+#define CODEC_f32768 16
 
 #define FREQ_4MHz   0
 #define FREQ_2MHz   1
@@ -46,9 +48,14 @@
 #define FREQ_128kHz 5
 #define FREQ_64kHz  6
 #define FREQ_32kHz  7
+/* FREQ_* with values where bit (value & 0x10) is set are */
+/* used for CODEC_f32768 */
+#define FREQ_4096kHz 16 /* CODEC_f32768 */
 
 /* Used by application to set CODEC divider, word rate and frame rate */
-#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) (CODEC | (freq << 8) | (clk_per_sync << 16) | (sync_per_frame << 28))
+#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) \
+        ((CODEC + ((freq & 0x10) >> 4)) | (freq << 8) | \
+                   (clk_per_sync << 16) | (sync_per_frame << 28))
 
 /* Used by driver to extract speed */
 #define GET_SPEED(x) (x & 0xff)
@@ -68,6 +75,7 @@
 #define NORMAL_SYNC                1
 #define EARLY_SYNC                 2
 #define SECOND_WORD_SYNC     0x40000
+#define LATE_SYNC            0x80000
 
 #define BIT_SYNC                   4
 #define WORD_SYNC                  8
@@ -104,4 +112,21 @@
 /* Values for SSP_INBUFCHUNK */
 /* plain integer with the size of DMA chunks */
 
+/* To ensure that the timestamps are aligned with the data being read
+ * the read length MUST be a multiple of the length of the DMA buffers.
+ *
+ * Use a multiple of SSP_INPUT_CHUNK_SIZE defined below.
+ */
+#define SSP_INPUT_CHUNK_SIZE  256
+
+/* Request struct to pass through the ioctl interface to read
+ * data with timestamps.
+ */
+struct ssp_request {
+        char __user *buf;       /* Where to put the data. */
+        size_t len;             /* Size of buf. MUST be a multiple of */
+                                /* SSP_INPUT_CHUNK_SIZE! */
+        struct timespec ts;     /* The time the data was sampled. */
+};
+
 #endif