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authorSimon Arlott <simon@fire.lp0.eu>2007-10-19 19:08:50 -0400
committerAdrian Bunk <bunk@kernel.org>2007-10-19 19:08:50 -0400
commit49b4ff3304b52b18c490fc4deb400b61bb7ed142 (patch)
treeec9bf61cec6c195e34630882bea801fadf44629a /arch/cris/arch-v32/kernel/time.c
parentc3a2ddee16e67c86f3b469ccdd396cda034756a9 (diff)
spelling fixes: arch/cris/
Spelling fixes in arch/cris/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: Adrian Bunk <bunk@kernel.org>
Diffstat (limited to 'arch/cris/arch-v32/kernel/time.c')
-rw-r--r--arch/cris/arch-v32/kernel/time.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/cris/arch-v32/kernel/time.c b/arch/cris/arch-v32/kernel/time.c
index be0a01657d4f..2f7e8e200f2c 100644
--- a/arch/cris/arch-v32/kernel/time.c
+++ b/arch/cris/arch-v32/kernel/time.c
@@ -99,7 +99,7 @@ unsigned long do_slow_gettimeoffset(void)
99/* From timer MDS describing the hardware watchdog: 99/* From timer MDS describing the hardware watchdog:
100 * 4.3.1 Watchdog Operation 100 * 4.3.1 Watchdog Operation
101 * The watchdog timer is an 8-bit timer with a configurable start value. 101 * The watchdog timer is an 8-bit timer with a configurable start value.
102 * Once started the whatchdog counts downwards with a frequency of 763 Hz 102 * Once started the watchdog counts downwards with a frequency of 763 Hz
103 * (100/131072 MHz). When the watchdog counts down to 1, it generates an 103 * (100/131072 MHz). When the watchdog counts down to 1, it generates an
104 * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the 104 * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the
105 * chip. 105 * chip.